JP2001189389A - Semiconductor memory and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an SRAM memory cell comprising load elements, employing polysilicon as a basic body in which high speed operation is realized by decreasing node contact resistance using salicidation technology. SOLUTION: A gate electrode 104ab of a driving transistor and a contact hole 109a, reaching an N-type diffusion layer 106b are formed in an interlayer film 108 covering a memory cell and a silicide layer 110, are formed selectively by silicidation, prior of forming a high resistance load thereon by growing polysilicon. Node contact resistance can be decreased because the N type diffusion layers 106ba, the gate electrodes 104ab, and the heavily-doped polysilicon region 111aa of the high resistance load are interconnected by the silicide layer 110.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a structure and a method of manufacturing a static random access memory (SRAM) cell.

[0002]

2. Description of the Related Art In recent years, RA which requires finer and faster
In the case of M, research and development of a method of applying a salicidation technique has been active in order to reduce the resistance of a fine diffusion layer and a gate electrode, reduce the operation delay due to parasitic resistance, and increase the speed. . This method is particularly important in a one-chip processor or the like in which an SRAM and a logic circuit are mixed.

A conventional technique for realizing such a method will be described with reference to FIGS. FIG. 6A shows an SRAM.
FIG. 7B is a plan view showing the memory cell, FIG. 7B is a sectional view of the same, and FIG. 7 is an equivalent circuit diagram.

A P well 301 is provided on an N-type silicon substrate, and a field 302 and a gate oxide film 303 are provided.
Are provided on the surface of the P well 301 provided with the first MOS transistor TD1, the second MOS transistor TD2, and the first MOS transistor TA for transfer.
1, a second transfer MOS transistor TA2, a first high-resistance load HR1, and a second high-resistance load HR2 are provided. The transistor TD1 includes a gate electrode 304aa, an N-type diffusion layer 306ba serving as a drain, and an N-type diffusion layer 306a serving as a source. The transistor TD2 includes a gate electrode 304ab and an N-type diffusion layer 306b serving as a drain.
b, an N-type diffusion layer 306a serving as a source, and the transistor TA1 has a gate electrode 304b and N serving as a drain.
Diffusion layer 306c, N-type diffusion layer 306da serving as a source
And the transistor TA2 has a gate electrode 304b,
N-type diffusion layer 306bb serving as a drain, N-type serving as a source
The gate electrode 304b made of the type diffusion layer 306db is used as a word line WL, and the N type diffusion layer 306a is connected to the ground GND. The high resistance load HR1 is composed of a high resistance polysilicon region 304ac,
ab and the power supply wiring 304ae. The high resistance load HR2 is composed of a high resistance polysilicon region 304ad, and is connected to the gate electrode 304aa and the power supply wiring 304ae. The power supply wiring 304ae is connected to the power supply Vcc. N-type diffusion layer 306ba and gate electrode 304ab
Are connected via the connection hole 309ac and the gate electrode 304a.
b and the N-type diffusion layer 306c are connected to each other via a connection hole 309aa, and constitute a first node N1. The N-type diffusion layer 306bb and the gate electrode 304aa are connected via a connection hole 309ab to form a second node N2. The N-type diffusion layer 306da has a connection hole 309ba.
Are connected to the bit line BL1 via the N-type diffusion layer 30.
6db is connected to the bit line BL2 via the connection hole 309bb. Gate electrodes 304aa, 304ab, 304
b, power wiring 304ae, high resistance polysilicon region 30
4ac and 304ad are formed in the same layer, and the portions other than the high-resistance polysilicon regions 304ac and 304ad are selectively doped with impurities to reduce the resistance. Furthermore, high resistance polysilicon regions 304ac, 30
Gate electrodes 304aa, 304ab, 30 excluding 4ad
4b, a silicide layer 307 having a thickness of, for example, 50 to 100 nm
It is formed to a thickness of about. Next, a method for manufacturing the SRAM memory cell according to the above-described conventional technique will be described with reference to FIG.

First, as shown in FIG. 8A, after a P well 301 is formed, a field 302 having a thickness of about 600 nm is formed in an element isolation region by a selective oxidation method or the like. A gate oxide film 303 having a thickness of about 20 nm is formed by thermal oxidation.

Next, an undoped polysilicon film having a thickness of about 300 nm is formed on the entire surface by the CVD method, and a photoresist pattern for selectively covering the high resistance load element forming region is formed thereon. As a mask, phosphorus is, for example, 30 keV 1E15 cm ^-2
After the ion implantation is performed under the conditions described above and the photoresist pattern is removed, patterning is performed by photoetching, and the gate electrodes 304aa, 304ab, 304b,
High resistance polysilicon regions 304ac and 304ad and power supply wiring 304ae are formed. Then phosphorus is 10
Ions are implanted over the entire surface under the condition of keV 2E13 cm ⁻² , and an oxide film 305 of about 150 nm is grown over the entire surface by the CVD method. Here, N ⁻ region 311 is formed.

Next, as shown in FIG. 8B, a photoresist (not shown) is formed on the oxide film 305 to cover the high-resistance polysilicon region, and is formed on the high-resistance polysilicon region by anisotropic dry etching. The pattern of the oxide film 305 remains on the gate electrodes 301aa and 304a.
b, 304b, high-resistance polysilicon region 304ac,
04ad, a side wall made of an oxide film 305 is formed on the side surface of the power supply wiring 304ae.

[0008] Next, as shown in FIG.
Gate electrodes 304aa, 304a having
b, 304b, power supply wiring 304ae and high-resistance polysilicon.
Arsenic is used as an example using the oxide film 305 covering the capacitor region as a mask.
For example, 30keV 4E15cm ^-2Ion implanted under the conditions
And N-type diffusion layers 306a, 306ba, 306bb, 3
06c, 306da, and 306db are formed. Further
Next, as shown in FIG.
High melting point metal such as titanium having a film thickness of about 50 to 60 nm
A layer is formed on the entire surface and, for example, heat at 650 ° C.
Treated titanium layer and silicon substrate surface in contact with it
And react with the polysilicon layer surface, for example, ammonia
+ Hydrogen peroxide solution removes unreacted titanium layer,
Gate electrodes 304aa, 304ab, 304b, power supply
Line 304ae, N-type diffusion layers 306a, 306ba, 30
Select over 6bb, 306c, 306da, 306db
A silicide layer 307 having a thickness of about 100 nm is formed.
It is. Next, as shown in FIG.
 Heat treatment for about 20 seconds is performed, and the silicide layer 307 is
Lower resistance.

Thereafter, as shown in FIG. 8E, an interlayer insulating film 308 is formed on the entire surface, and connection holes 309aa, 309ab, 309ac, 309 are formed on the interlayer film 308.
Ba and 309bb are opened and a metal electrode 310 is formed to complete a prior art SRAM memory cell.

[0010]

The prior art described above is
Four MOS transistors TD1, TD2, TA1, T
Since the high resistance loads HR1 and HR2 are formed on the same plane as A2, the cell area increases by that amount, which is disadvantageous for high integration.

To solve this problem and achieve high integration, four MOS transistors TD1, TD2, TA1, TA2
When the high-resistance loads HR1 and HR2 are to be stacked on the above, the following problems occur.

That is, as shown in FIG. 9, in the case of stacking, connection holes 309aa, 30a serving as node contacts are formed.
In 9ab, the high-concentration polysilicon region 312 connected to the low-concentration polysilicon region 313 to be the high-resistance load elements HR1 and HR2 is used instead of the metal electrode 310.

In general, a silicide layer has low heat resistance, and when subjected to a high-temperature heat treatment, aggregates, resulting in high resistance. Therefore, the heat treatment after the formation of the silicide layer needs to be performed at a low temperature and for a short time. At this time, the resistance of the high-concentration polysilicon region 312 significantly increases even though it contains high-concentration impurities, and thereby the gate electrode 304
ab and N-type diffusion layer 306c or gate electrode 304
A high resistance is parasitically generated between aa and the N-type diffusion layer 306bb, causing a significant delay in the operation speed. An object of the present invention is to provide a structure and a manufacturing method of an SRAM cell which solves such a problem and has a high degree of integration and can operate at high speed.

[0014]

In order to achieve the above object, a semiconductor memory device according to the present invention is a semiconductor memory device having a structure of a static random access memory cell, wherein the static random access memory cell comprises a semiconductor substrate. Sources selectively formed on the surface of
A first driving MOS transistor having a drain region, a second driving MOS transistor, a first transfer MOS transistor connected to a drain region of the first driving MOS transistor, and a second driving MOS transistor. A second transfer transistor connected to a drain region of the driving MOS transistor; and a first and second load element, wherein the source and drain regions of the first and second driving MOS transistor are included. A metal silicide layer is selectively formed on the upper surface of the gate electrode, the source and drain regions of the first and second transfer MOS transistors, and the gate electrode. Has first and second connection holes formed therein, and the first connection hole is provided with the first driving MOS.
A drain region of the transistor and the second driving MO;
The second connection hole is formed on the gate electrode of the second driving MOS transistor and the second connection hole is formed on the gate electrode of the first driving MOS transistor. The drain region of the first driving N-channel MOS transistor and the gate electrode of the second driving MOS transistor are mutually connected by a metal silicide layer selectively formed inside the first connection hole. A non-single-crystal silicon-based thin film which is to be a part of the first load element is formed thereon, and a drain region of the second drive MOS transistor and the first drive MOS transistor Are connected to each other by a metal silicide layer selectively formed inside the second connection hole, and the second negative electrode is formed thereon. In which polycrystalline thin film serving as a part of the element is formed.

Further, a method of manufacturing a semiconductor memory device according to the present invention includes a MOS transistor forming step, an insulating film side wall forming step, a first metal silicide layer forming step, a connection hole forming step, and a second step. A method of manufacturing a semiconductor memory device including a metal silicide layer forming step and a load element forming step, wherein the MOS transistor forming step includes: forming a first driving MOS transistor on a surface of a semiconductor substrate; Forming a second MOS transistor, a second driving MOS transistor, and a second transfer MOS transistor. The insulating film sidewall forming step includes forming an insulating film side wall on a side surface of a gate electrode of each MOS transistor. In the first metal silicide layer forming step, a first metal layer is formed over the entire surface of the substrate, and then a heat treatment is performed. Selectively forming a first metal silicide layer on the upper surface of the drain region, the source region, and the gate electrode, and the step of forming a contact hole removes an unreacted layer of the first metal layer. After that, an interlayer insulating film is formed on the entire surface of the substrate, and the interlayer insulating film is selectively etched to form a first connection hole reaching the first drain region and the third gate electrode; Forming a second connection hole reaching the drain region and the first gate electrode so that a sidewall of an insulating film does not remain on a side surface of each gate electrode inside each connection hole; In the silicide layer forming step, after forming a second metal layer on the entire surface of the substrate, a second metal layer is selectively formed on the drain region, the upper surface of the gate electrode, and the side surface of the gate electrode at the bottom of each connection hole by heat treatment. The load element forming step is a step of forming a side layer, and after removing an unreacted layer of the second metal layer, a polycrystalline thin film is formed on the entire surface of the substrate, and the polycrystalline thin film is used as a component. This is a process for forming a load element to be performed.

Further, between the step of removing an unreacted layer of the second metal layer and the step of forming a load element, the surface of the second metal silicide layer is treated in ammonia plasma to be nitrided. Forming a thin film.

[0017]

Embodiments of the present invention will be described below with reference to the drawings.

Embodiment 1 FIGS. 1A and 1B are plan views showing an SRAM memory cell using a high resistance load as a load element according to Embodiment 1 of the present invention, and FIG. , FIG.
It is AA 'line sectional drawing of (a) and (b). FIG.
FIG. 3 is an equivalent circuit diagram of the SRAM memory cell.

In the figure, the SR according to the first embodiment of the present invention is shown.
The structure of the AM memory cell is as follows. That is, on the P-type silicon substrate 101, a field 102 having a film thickness of about 400 nm by selective oxidation or the like in a device isolation region and a device formation region, and a gate oxide film 103 having a film thickness of about 10 nm by thermal oxidation or the like, respectively. Provided, the P-type silicon substrate 101 is 10 ¹⁶ to 10 ¹⁸ cm
^-3 having an impurity concentration of about
On the surface, the first and second driving MOS transistors TD
1 and TD2, and first and second transfer MOS transistors TA1 and TA2.

The semiconductor substrate 1 is interposed via the gate oxide film 103.
A gate electrode 104aa, 1 having a sidewall 105 of about 100 nm width made of an oxide film
04ba, 104ab, and 104bb are provided.
The gate electrode 104aa and the like are made of N having a thickness of about 300 nm.
Made of a polysilicon film. In the element formation region on the surface of the P-type silicon substrate 101, N-type diffusion layers 106aa, 106ba, 106ca,
106ab, 106bb, and 106cd are formed. The impurity concentration of these N-type diffusion layers 106aa and the like is 1
It is about 0 ²⁰ to 10 ²¹ cm ^-3 .

First driving MOS transistor TD1
Are the gate electrode 104aa, the gate oxide film 103,
An N-type diffusion layer 106aa as a first source region;
And an N-type diffusion layer 106ba as a drain region. First transfer MOS transistor TA1
Are a gate electrode 104ba, a gate oxide film 103,
An N-type diffusion layer 106ca serving as a second source region;
And the first drain region of N
And the diffusion layer 106ba. The second driving MOS transistor TD2 includes a gate electrode 104ab
And an N-type diffusion layer 106ab as a third source region;
And an N-type diffusion layer 106bb as a third drain region. Second transfer MOS transistor TA
Reference numeral 2 denotes a gate electrode 104bb, an N-type diffusion layer 106cb as a fourth source region, and an N-type diffusion layer 106bb as a fourth drain region and a third drain region.
It is composed of The gate electrodes 104ba, 104bb also serving as the word lines WL are connected outside the memory cells. The surfaces of the gate electrode 104aa and the like and the N-type diffusion layer 106aa and the like are covered with a selectively formed silicide layer 107, and the gate electrode and the N-type diffusion layer adjacent thereto are insulated by the sidewall 105. I have.

Each of these four N-channel MOS transistors has a flat surface, and at least the bottom and top surfaces are covered with an interlayer film 108 made of an undoped oxide film. This interlayer film has, for example, an oxide film having a thickness of about 100 nm as a lower layer, a BPSG film as an intermediate layer, and a thickness of 100 nm.
It is composed of a laminated film having an oxide film of about nm in the upper layer. The thickness of the interlayer film 108 is about 200 nm at the thinnest part and about 600 nm at the thickest part. The interlayer film 108 has a connection hole 109 serving as a first node contact reaching the gate electrode 104ab and the N-type diffusion layer 106ba.
a, the gate electrode 104aa and the N-type diffusion layer 106b
connection hole 10 as the second node contact reaching
9b is provided.

At the bottom of the connection holes 109a and 109b, the gate electrode 1 is formed inside the connection holes 109a and 109b.
04ba, 104aa Top and Side, N-Type Diffusion Layer 10
A silicide layer 110 selectively formed on the upper surfaces of 6ba and 106bb is provided.

Interlayer film 108 including silicide layer 110
Are provided with first and second polysilicon patterns made of a polysilicon film having a thickness of about 50 to 100 nm. The first polysilicon pattern includes high-concentration polysilicon regions 111aa and 111ba and a low-concentration polysilicon region 111ca. The second polysilicon pattern includes high-concentration polysilicon regions 111ab and 111ab.
bb, low-concentration polysilicon region 111cd. High concentration polysilicon regions 111aa, 111ba, 111
The impurity concentrations of ab and 111bb are 10 ¹⁹ to 10 ²⁰ cm ^-3.
Degree, low concentration polysilicon regions 111ca, 111cd
Has an impurity concentration of about 10 ¹⁶ to 10 ¹⁹ cm ⁻³ . The high-concentration polysilicon regions 111ba and 111bb each form a part of a power supply line, and both are connected to a power supply Vcc outside the memory cell. High concentration polysilicon region 11
1aa is connected to the silicide layer 110 at the connection hole 109a, and the high-concentration polysilicon region 111ab is connected to the silicide layer 110 at the connection hole 109b. The low-concentration polysilicon region 111ca has a high resistance load H
The low-concentration polysilicon region 111cb functions as a high-resistance portion of the high-resistance load HR2.

The high-concentration polysilicon region 111aa, the gate electrode 104ab, and the N-type diffusion layer 106ba
At 9a, they are connected to each other by a silicide layer 110 to form a node N1. The high-concentration polysilicon region 111ab, the gate electrode 104aa, and the N-type diffusion layer 106bb are
0 connects each other to form a node N2.

The high-concentration polysilicon region 111aa,
111 ba, 111 ab, 111 bb and the interlayer film 108 including the low-concentration polysilicon regions 111 ca, 111 cd
Has a flat surface, and at least the bottom surface is covered with an interlayer film 112 made of an oxide film. This interlayer film 112 is formed of a laminated film having, for example, an oxide film having a thickness of about 100 nm as a lower layer and a BPSG film as an upper layer, and is formed on the high-concentration polysilicon region 111aa and the like.
Has a thickness of about 200 nm. In the interlayer film 112, connection holes 113a (which are first ground contacts) reaching the N-type diffusion layers 106aa and 106ab, respectively, and (second
Connection hole 113b). The N-type diffusion layers 106aa and 106ab are connected to the ground wiring 114 provided on the surface of the interlayer film 112 through these connection holes 113a and 113b. The ground wiring 111 is made of, for example, a tungsten film having a thickness of about 200 nm, and is connected to the ground GND.

The surface of the interlayer film 112 including the ground wiring 114 is covered with an interlayer film 115 having a flat surface. This interlayer film 115 is made of, for example, a plasma oxide film or the like. The thickness of the interlayer film on the ground line 114 is 200
nm. A connection hole 116a serving as a first bit contact penetrating the interlayer films 115, 112, and 108 and reaching the N-type diffusion layer 106ca is opened. Diffusion layer 106
connection hole 1 which is the second bit contact reaching cb
16b is open. The inside of the connection holes 117a and 117b is a metal plug 117 made of, for example, tungsten or the like.
a, 117b. Metal wiring 118a serving as a pair of bit lines provided on interlayer film 115
(BL1) and the metal wiring 118b (BL2) are respectively connected to the N-type diffusion layer 1 through the connection holes 116a and 116b.
06ca and 106cd.

Next, referring to FIG. 2, a first embodiment of the present invention will be described.
The method for manufacturing the SRAM memory cell according to

First, as shown in FIG. 2A, a field 102 having a thickness of about 400 nm is formed in a device isolation region on the surface of a P-type silicon substrate 101 by a selective oxidation method or the like.
A gate oxide film 103 having a thickness of about 10 nm is formed in the element formation region by thermal oxidation or the like. Next, for example, LP
N with a thickness of about 300 nm by CVD and ion implantation.
Type polysilicon film is formed on the entire surface and patterned by anisotropic dry etching to form gate electrodes 104aa, 1
04ba, 104ab and 104bb are formed.

LDD (Lightly Doped D)
In order to form a (rain) structure, phosphorus or arsenic ions are implanted at a dose of about 2E13 cm ^{−2 using} the field 102 and the gate electrode 101aa as a mask, and an oxide film of about 100 nm is grown on the entire surface by, eg, LPCVD. Then, a sidewall 105 is formed on the side surface of the gate electrode 101aa and the like by performing anisotropic dry etching. At this time, the N-type diffusion layer 10
The upper surfaces of 6aa and the like and the gate electrode 104aa and the like are in a state where silicon is exposed. Subsequently, the field 102 and the gate electrodes 104aa, 104ba, 104ab, 104bb
And arsenic ion implantation using the sidewalls 105 as a mask with a dose of about 5E15 cm ⁻² ,
10 ²⁰ to 10 ²¹ cm on the surface of the P-type silicon substrate 101
N-type diffusion layers 106aa and 106b having a concentration of about ³
a, 106ca, 106ab, 106bb, 106cd
To form Next, a metal layer such as titanium is deposited on the entire surface by a sputtering method or the like, and the metal layer in contact with silicon is silicidized by a rapid heat treatment at 700 ° C. or lower to form a silicide layer 107. After etching the unreacted metal layer with ammonia + hydrogen peroxide solution or the like, a rapid heat treatment at a higher temperature (800 ° C. or more) than the above-described rapid heat treatment is performed to reduce the resistance of the silicide layer 107.

Next, an interlayer film 108 having a flat surface and at least a bottom surface and an upper surface made of an oxide film is formed on the entire surface by, for example, LPCVD or chemical mechanical polishing (CMP). This interlayer film 108 is formed, for example, as follows. An oxide film having a thickness of about 100 nm is formed on the entire surface by a normal pressure CVD method or the like.
A BPSG film of about 0 nm is formed. For example, after performing heat treatment at about 800 ° C., the surface is flattened by CMP or the like. Further, an oxide film having a thickness of about 100 nm is formed on the entire surface by a normal pressure CVD method or the like.

Next, as shown in FIG.
8, an N-type diffusion layer 1 is formed by anisotropic dry etching.
06ba and the connection hole 10 reaching the gate electrode 104ab
9a, N-type diffusion layer 106bb and gate electrode 104aa
Is formed. Here, the connection hole 10
Overetching is performed so that no sidewall remains on the side surface of the gate electrode 104ab or the like inside 9a or the like. In the first embodiment, the silicide layer 107 on the N-type diffusion layer and the gate electrode is illustrated as being removed by etching. However, the silicide layer 107 is etched by etching with a high oxide / silicide etching selectivity. May be stopped. continue,
As shown in FIG. 2C, a metal layer such as titanium is deposited on the entire surface by sputtering or the like, and the metal layer in contact with silicon is silicidized by a rapid heat treatment at 700 ° C. or less. N-type diffusion layer 10
A silicide layer 110 is formed on the upper surface of 6ba and the upper and side surfaces of the gate electrode 104ab. After etching the unreacted metal layer with an ammonia + hydrogen peroxide solution or the like, a rapid heat treatment at a temperature higher than the rapid heat treatment (800 ° C. or higher) is performed to lower the resistance of the silicide layer 110.
Next, as shown in FIG. 2D, the entire surface of the interlayer film 108 including the silicide layer 110 is 50 to 100 nm thick.
Polysilicon layer or SIPOS
(Semi-Insulating PolySili
con) is formed by an LPCVD method or the like. At this time, in order to prevent the silicon and silicide layer from reacting with active silicon formed by decomposition of the growth gas during growth of the polysilicon layer or SIPOS, a treatment is performed in ammonia plasma to form nitride on the surface of the silicide layer 110. May be. An N-type impurity is introduced at a dose of about 1E13 cm ⁻² by ion implantation or the like to increase the resistance value, and is further patterned by anisotropic dry etching.
A low concentration polysilicon region 111 is formed.

Then, as shown in FIG. 2E, phosphorus or arsenic ions are implanted at a dose of about 1E15 cm ⁻² using the photoresist 119 as a mask to form high-concentration polysilicon regions 111aa, 111ba, 111ab, and 11ab.
1bb, and low-concentration polysilicon regions 111ca and 111
cb is left.

Subsequently, an interlayer film 112 having a flat surface and at least a bottom surface made of an oxide film is formed on the entire surface by, for example, normal pressure CVD or CMP. This interlayer film 11
2 is formed, for example, as follows. An oxide film having a thickness of about 100 nm is formed on the entire surface by a normal pressure CVD method or the like, and then a BPSG film having a thickness of about 600 nm is formed by a normal pressure CVD method or the like. For example, after performing a heat treatment at about 800 ° C.,
The surface is flattened by CMP or the like.

Subsequently, connection holes 113 reaching the N-type diffusion layers 106aa and 106ab by anisotropic dry etching.
a and 113b are formed. Thereafter, using a known wiring process, ground wiring 114, interlayer film 115, connection hole 116
a, 116b, metal plugs 117a, 117b, and metal wirings 118a, 118b are formed.
Complete M memory cells.

According to such a structure and a manufacturing method, even in a process in which the heat treatment is performed at a low temperature and in a short time, the resistance load type SRA having a small parasitic resistance at the node / contact portion.
M memory cells can be realized.

(Embodiment 2) FIGS. 3 (a) and 3 (b) are plan views and views showing an SRAM memory cell having a polysilicon-based thin film transistor (TFT) as a load according to Embodiment 2 of the present invention. 3 (c) is a sectional view taken along line AA 'of FIGS. 3 (a) and 3 (b), and FIG. 4 is an equivalent circuit diagram of the SRAM memory cell.

In the figure, S according to the second embodiment of the present invention
The structure of the RAM memory cell is as follows. That is, the P-type silicon substrate 201 has a size of 10 ¹⁶ to 10 ¹⁸ cm.
A field 202 having an impurity concentration of about ^-3 , and a film thickness of about 400 nm in each of an element isolation region and an element formation region by selective oxidation or the like; and 10 n by thermal oxidation or the like.
a gate oxide film 203 having a thickness of about m
On the surface of the P-type silicon substrate 201, first and second driving MOS transistors TD1 and TD2 and first and second transfer MOS transistors TA1 and TA2 are provided. Gate electrodes 204aa and 204b each having a sidewall 205 of about 100 nm in width made of an oxide film on the surface of the semiconductor substrate 201 via the gate oxide film 203.
a, 204ab, and 204bb are provided. The gate electrode 204aa and the like are made of an N-type polysilicon film having a thickness of about 300 nm. A field 202 and a gate electrode 204 are formed in an element formation region on the surface of the P-type silicon substrate 201.
aa and the like,
Type diffusion layers 206aa, 206ba, 206ca, 206
ab, 206bb and 206cb are formed. The impurity concentration of these N-type diffusion layers 206aa and the like is 10 ²⁰ to 1
It is about 0 ²¹ cm ^-3 . A gate electrode 204aa, a gate oxide film 203, an N-type diffusion layer 206aa as a first source region, and an N-type diffusion layer 2 as a first drain region.
06ba, the first driving MOS transistor TD
1 is configured. A gate electrode 204ba, a gate oxide film 203, and an N-type diffusion layer 2 serving as a second source region.
06ca and the N-type diffusion layer 206ba serving as the second drain region and the first drain region constitute a first transfer MOS transistor TA1. The second driving MOS transistor T includes a gate electrode 204ab, an N-type diffusion layer 206ab as a third source region, and an N-type diffusion layer 206bb as a third drain region.
D2 is configured. The gate electrode 204bb and the fourth
The second transfer MOS transistor TA2 is composed of the N-type diffusion layer 206cb, which is the source region, and the N-type diffusion layer 206bb, which is the fourth drain region and the third drain region. The gate electrodes 204ba, 204bb which also serve as the word lines WL are connected outside the memory cells. Gate electrode 204aa etc. and N
The surface of the type diffusion layer 206aa and the like is covered with a selectively formed silicide layer 207, and the gate electrode and the N-type diffusion layer adjacent thereto are
5 insulated.

Each of these four N-channel MOS transistors has a flat surface, and at least the bottom and top surfaces are covered with an interlayer film 208 made of an undoped oxide film. This interlayer film has, for example, an oxide film having a thickness of about 100 nm as a lower layer, a BPSG film as an intermediate layer, and a thickness of 100 nm.
It is composed of a laminated film having an oxide film of about nm in the upper layer. The thickness of the interlayer film 208 is about 200 nm at the thinnest part and about 600 nm at the thickest part. The interlayer film 208 has a connection hole 209 serving as a first node contact reaching the gate electrode 204ab and the N-type diffusion layer 206ba.
a, the gate electrode 204aa and the N-type diffusion layer 206b
connection hole 20 which is the second node contact reaching
9b is provided. These connection holes 209a, 209b
A silicide layer 210 selectively formed on the upper surfaces and side surfaces of the gate electrodes 204ba, 204aa and the upper surfaces of the N-type diffusion layers 206ba, 206bb is provided inside the connection holes 209a, 209b. On the surface of the interlayer film 208 including the silicide layer 210,
T made of a polysilicon film having a thickness of about 50 to 100 nm
FT gate electrodes 211a and 211b are provided. The gate electrode 211a of the TFT is connected to the silicide layer 210 through the connection hole 209b, and the gate electrode 211b of the TFT is connected to the silicide layer 21 through the connection hole 209a.
0 is connected. TFT gate electrodes 211a, 21
A gate oxide film 212 of a TFT having a thickness of about 5 to 20 nm is formed on the surface of the interlayer film 208 including 1b.
In the gate oxide film 212 of the FT, a connection hole 213a is opened almost immediately above the connection hole 209a.
A connection hole 213b is formed immediately above 09b. The gate oxide film 2 of the TFT including the connection holes 213a and 213b
The first and second polysilicon patterns made of a polysilicon film having a thickness of about 10 to 100 nm are provided on the surface of the substrate 12. The first polysilicon pattern is a first polysilicon pattern.
, A high-concentration P-type polysilicon region 214aa as a P-type drain region, and a high-concentration P-type
And a low-concentration polysilicon region 214ca that is a first channel region.
Is a high-concentration P-type polysilicon region 214ab that is a second P-type drain region and a high-concentration P-type polysilicon region 2 that is a second P-type source region.
14bb and a low-concentration polysilicon region 214cb as a second channel region. High concentration polysilicon region 2
14aa, 214ba, 214ab and 214bb have an impurity concentration of about 10 ¹⁰ to 10 ²⁰ cm ⁻³ , and the low-concentration polysilicon regions 214ca and 214cd have an impurity concentration of 10 ¹⁶ to
It is about 10 ¹⁸ cm ^-3 . In order to reduce the leakage current of the TFT, a high-concentration P-type polysilicon region 214aa,
214ab and the low-concentration polysilicon region 214ca,
14cb, a low-concentration P-type polysilicon region may be provided. The high-concentration P-type polysilicon regions 214ba and 214bb each form part of a power supply line, and both are connected to a power supply Vcc outside the memory cell. High concentration P
The polysilicon region 214aa is connected to the gate electrode 211b of the TFT at the connection hole 213a, and the high-concentration P-type polysilicon region 214ab is connected to the gate electrode 211a of the TFT at the connection hole 209b. TF
T gate electrode 211a, TFT gate oxide film 21
2. High concentration P-type polysilicon regions 214aa, 214b
a, low-concentration polysilicon region 214ca is a load TFT
TL1 is formed, and the TFT gate electrode 211b, TF
T gate oxide film 212, high-concentration P-type polysilicon regions 214ab and 214bb, low-concentration polysilicon region 21
4cb constitutes the load TFT TL2. The high-concentration P-type polysilicon region 214aa and the gate electrode 211b of the TFT are connected via a connection hole 213a, and the gate electrode 211b, the gate electrode 204ab, and the N-type diffusion layer 206ba of the TFT are connected to the silicide layer 21 at the connection hole 209a.
0 connects each other to form a node N1. Also, a high-concentration P-type polysilicon region 214ab and TF
The T gate electrode 211a is connected through the connection hole 213b, and the TFT gate electrode 211a and the gate electrode 204a are connected to each other.
a, the N-type diffusion layer 206bb is connected to each other by the silicide layer 210 in the connection hole 209b, and the node N2
Is composed. The high-concentration polysilicon region 214a
The surface of the gate oxide film 212 of the TFT including the a, 214ba, 214ab, 214bb and the low-concentration polysilicon regions 214ca, 214cb has a flat surface, and at least the bottom surface is covered with an interlayer film 215 made of an oxide film. I have. This interlayer film 215 is formed of a laminated film having, for example, an oxide film having a thickness of about 100 nm as a lower layer and a BPSG film as an upper layer, and has a thickness of 200 nm on the high-concentration polysilicon region 214aa and the like. It is about. N-type diffusion layers 206aa and 206aa are provided in the interlayer film 215, respectively.
connection hole 21 which is the first ground contact reaching ab
6a and a connection hole 216b as a second ground contact are provided. The N-type diffusion layers 206aa and 206ab form the interlayer film 2 through these connection holes 216a and 216b.
15 is connected to the ground wiring 217 provided on the surface of the F.15. The ground wiring 217 is made of, for example, a tungsten film having a thickness of about 200 nm, and is connected to the ground GND.

The surface of the interlayer film 215 including the ground wiring 217 is covered with an interlayer film 218 having a flat surface. This interlayer film 218 is made of, for example, a plasma oxide film or the like. The thickness of the interlayer film on the ground line 217 is 200
nm.

The N type diffusion layer 2 penetrates through the interlayer films 218 and 215, the gate oxide film 212 of the TFT, and the interlayer film 208.
A connection hole 219a, which is a first bit contact reaching 06ca, is opened, and interlayer films 218, 215, T
Penetrating through the gate oxide film 212 and the interlayer film 208 of FT;
A connection hole 219b, which is a second bit contact reaching the mold diffusion layer 206cb, is opened. Connection hole 219
a and 219b are filled with metal plugs 220a and 220b made of, for example, tungsten or the like.
A metal wiring 221a (BL1) and a metal wiring 221b (BL) serving as a pair of bit lines provided on the interlayer film 218 are formed.
2) is connected to the N-type diffusion layers 206ca and 206cb via connection holes 219a and 219b, respectively. SRAM according to Embodiment 2 of the present invention with reference to FIG.
A method for manufacturing a memory cell will be described.

First, as shown in FIG. 5A, a field 202 having a thickness of about 400 nm is formed in the element isolation region on the surface of the P-type silicon substrate 201 by selective oxidation or the like, and a thermal oxidation or the like is formed in the element formation region. As a result, a gate oxide film 203 having a thickness of about 10 nm is formed. Next, for example, LPC
An N-type polysilicon film having a thickness of about 300 nm is formed on the entire surface by a VD method and an ion implantation method, and is patterned by anisotropic dry etching.
04ba, 204ab and 204bb are formed.

LDD (Lightly Doped D)
In order to form a (rain) structure, phosphorus or arsenic ions are implanted at a dose of about 2E13 cm ^{−2 using} the field 202 and the gate electrode 204aa as a mask, and an oxide film of about 100 nm is grown on the entire surface by, eg, LPCVD. Then, a sidewall 205 is formed on the side surface of the gate electrode 204aa and the like by performing anisotropic dry etching. At this time, the N-type diffusion layer 206
The upper surfaces of the aa and the like and the gate electrode 204aa and the like are in a state where silicon is exposed. Subsequently field 202 and the gate electrode 204aa, 204ba, 204ab, by ion implantation of arsenic was 204bb and the sidewalls 205 as a mask in the dose of about 5E15 cm ^-2, 10 ²⁰ ~ the surface of the P-type silicon substrate 201 N-type diffusion layers 206aa and 206ba having a concentration of about 10 ²¹ cm ^-3
206ca, 206ab, 206bb, and 206cb are formed. Next, a metal layer such as titanium is deposited on the entire surface by sputtering or the like, and the metal layer in contact with silicon is silicided by a rapid heat treatment at 700 ° C. to form a silicide layer 207. After etching the unreacted metal layer with an ammonia + hydrogen peroxide solution or the like, a rapid heat treatment at a higher temperature (800 ° C. or higher) than the above-described rapid heat treatment is performed to reduce the resistance of the silicide layer 207.

Next, an interlayer film 208 having a flat surface and at least a bottom surface and an upper surface made of an oxide film is formed on the entire surface by, for example, LPCVD and chemical mechanical polishing (CMP). This interlayer film 208 is formed, for example, as follows. An oxide film having a thickness of about 100 nm is formed on the entire surface by a normal pressure CVD method or the like.
A BPSG film of about 0 nm is formed. For example, after performing heat treatment at about 800 ° C., the surface is flattened by CMP or the like. Further, an oxide film having a thickness of about 100 nm is formed on the entire surface by a normal pressure CVD method or the like.

The N-type diffusion layer 206ba and the gate electrode 204 are formed on the interlayer film 208 by anisotropic dry etching.
A connection hole 209a reaching ab, an N-type diffusion layer 206bb, and a connection hole 209b reaching the gate electrode 204aa are formed. Here, over-etching is performed so that a sidewall does not remain on the side surface of the gate electrode 204ab or the like inside the connection hole 209a or the like. The silicide layer 207 on the N-type diffusion layer and the gate electrode may be removed by etching, or the etching may be stopped at the silicide layer 207 by etching having a high etching selectivity of oxide film / silicide. Subsequently, a metal layer such as titanium is deposited on the entire surface by sputtering or the like,
The metal layer in contact with silicon is silicided by a rapid thermal treatment at 700 ° C. or lower, and a silicide layer 210 is formed on the upper surface of the N-type diffusion layer 206ba and the upper surface and side surfaces of the gate electrode 204ab inside the connection hole 209a. After etching the unreacted metal layer with an ammonia + hydrogen peroxide solution or the like, a temperature higher than the rapid heat treatment (800 ° C.)
The above-described rapid heat treatment is performed to reduce the resistance of the silicide layer 210. Next, as shown in FIG. 5B, the surface of the interlayer film 208 including the silicide layer 210 is
A polysilicon layer having a thickness of about 0 to 100 nm is represented by L
It is formed by a PCVD method or the like. At this time, in order to prevent a reaction between active silicon formed by decomposition of a growth gas and a silicide layer during the growth of the polysilicon layer, a treatment is performed in an ammonia plasma to form a nitride on the surface of the silicide layer 210. Is also good. An N-type impurity is introduced at a dose of about 1E13 to 1E15 cm ⁻² by ion implantation or the like, and is further patterned by anisotropic dry etching, so that the gate electrodes 211a and 211b of the TFT are formed.
To form

Next, the entire surface is formed to a thickness of 5 to 5
A 20 nm TFT gate oxide film 212 is formed, and the TFT gate oxide film 212 is formed by anisotropic dry etching.
Connection hole 213 reaching the gate electrode 211b of the TFT
a, connection hole 213 reaching gate electrode 211a of TFT
b is opened.

Next, as shown in FIG.
Growing a 10~100nm of amorphous silicon by the CVD method, and crystallized at a temperature of about 600 ° C., after a polysilicon film, N at doses of 1E12～1E13cm ^-2
Type impurities are ion-implanted and patterned by anisotropic dry etching to form a low-concentration polysilicon region 214a,
Form 214b.

Then, as shown in FIG. 5D, using the photoresist 222 as a mask, boron or BF2 ions are implanted at a dose of about 1E14 to 1E15 cm ^-2 , and the high-concentration P-type polysilicon regions 214aa and 214b are formed.
a, 214ab, 214bb are formed, and the low-concentration polysilicon regions 214ca, 214cb are left in the region covered with the photoresist 222. After that, as in the first embodiment, the interlayer film 215 and the connection holes 216a and 216a
6b, ground wiring 217, interlayer film 218, connection hole 219
a, 219b, metal plugs 220a, 220b, and metal wirings 221a, 222b are formed.
Complete M memory cells.

According to such a structure and a manufacturing method, even in a process in which the heat treatment is performed at a low temperature for a short time, the TFT load type SR having a small parasitic resistance at the node / contact portion.
An AM memory cell can be realized.

In the first and second embodiments, the lower gate type in which the gate electrode of the TFT is lower than the channel region of the TFT has been described. Is also applicable.

[0051]

As described above, according to the present invention, the gate electrode of the driving MOS transistor and the N electrode are formed by the silicide layer selectively formed inside the node contact.
Since the type diffusion layer is connected and a resistance element or a TFT element is formed thereon, a small memory cell area can be realized, and the heat treatment corresponding to the salicidation process is performed at a low temperature and in a short time. Even if the process is adopted, it is possible to realize a memory cell capable of reducing the parasitic resistance between the gate and the diffusion layer and operating at high speed.

In fact, in the conventional memory cell, the cell area increases by the length of the lowest resistance element, but according to the present invention, since there is no such overhead, the cell area can be reduced by about 30%. In addition, the present invention can reduce the parasitic resistance between the gate and the diffusion layer by two digits or more in the present invention, so that the RC delay is improved by two digits or more.

[Brief description of the drawings]

1A and 1B are plan views showing a first embodiment of the present invention, and FIG. 1C is a cross-sectional view taken along the line AA ′ of FIGS. 1A and 1B.

FIG. 2 is a sectional view illustrating a method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps.

3 (a) and 3 (b) are plan views showing a second embodiment of the present invention, and FIG. 3 (c) is a cross-sectional view taken along line AA ′ of FIGS. 3 (a) and 3 (b).

FIG. 4 is an equivalent circuit diagram of an SRAM memory cell having a P-channel transistor as a load element.

FIG. 5 is a cross-sectional view showing a method of manufacturing a semiconductor device according to Embodiment 2 of the present invention in the order of steps.

FIG. 6 is an equivalent circuit diagram of an SRAM memory cell having a high resistance load as a load element.

FIG. 7 is a cross-sectional view showing a conventional manufacturing method.

FIG. 8 is a cross-sectional view showing a problem of the related art.

FIG. 9 is a sectional view showing a conventional example.

[Explanation of symbols]

101, 201 P-type silicon substrate 102, 202, 302 Field 103, 203,
303 Gate oxide film 104aa, 104ba, 104ab, 104bb, 2
04aa, 204ba, 204ab, 204bb, 30
4aa, 304ab, 304b Gate electrode 105, 205 Sidewall 106aa, 106ba, 106ca, 106ab, 1
06bb, 106cb, 206aa, 206ba, 20
6ca, 206ab, 206bb, 206cb, 306
a, 306ba, 306bb, 306c, 306da,
306db N-type diffusion layers 107, 110, 207, 210, 307 Silicide layers 108, 112, 115, 208, 215, 218, 3
08 interlayer films 109a, 109b, 113a, 113b, 116a,
116b, 209a, 209b, 213a, 213b,
216a, 216b, 219a, 219b, 309a
a, 309ab, 309ba, 309bb, 309c
Connection holes 111aa, 111ba, 111ab, 111bb, 3
12 High concentration polysilicon region 111, 111ca, 111cd, 214a, 214a
a, 214ba, 214ab, 214bb, 313 Low-concentration polysilicon region 114, 217 Ground wiring 117a, 117b, 220a, 220b Metal plug 118a, 118b, 221a, 221b, 310 Metal wiring 119, 222 Photoresist 211a, 211b TFT gate Electrode 212 TFT gate oxide film 214aa, 214ba, 214ab, 214bb High-concentration P-type polysilicon region 301 P well 305 Oxide film 304ae Power supply line 311 N ⁻ region TD1, TD2 Driving MOS transistor TA1, TA2 Transfer MOS transistor HR1, HR2 High resistance load TL1, TL2 Load TFT GND Ground Vcc Power supply N1, N2 Node WL Word line BL1, BL2 Bit line

Claims (3)

[Claims] 1. A semiconductor memory device having a structure of a static random access memory cell, wherein the static random access memory cell has a first drive having a source / drain region selectively formed on a surface portion of a semiconductor substrate. MOS transistor and second driving MO
An S transistor, a first transfer MOS transistor connected to a drain region of the first drive MOS transistor, and a second transfer transistor connected to a drain region of the second drive MOS transistor. ,
A first load element and a second load element.
And the source and drain regions of the second driving MOS transistor, the gate electrode, and the first and second transfer MO transistors.
A metal silicide layer is selectively formed on the source and drain regions of the S transistor and the upper surface of the gate electrode, and first and second connection holes are formed in the interlayer insulating film covering each transistor. The first connection hole is formed in a drain region of the first drive MOS transistor and a gate electrode of the second drive MOS transistor, and the second connection hole is A hole is formed in a drain region of the second driving MOS transistor and a gate electrode of the first driving MOS transistor, and a drain region of the first driving N-channel MOS transistor and the second driving MOS transistor; The gate electrode of the driving MOS transistor is connected to each other by a metal silicide layer selectively formed inside the first connection hole. A non-single-crystal silicon-based thin film which is a part of the first load element is formed, and a drain region of the second driving MOS transistor and a gate electrode of the first driving MOS transistor are The second connection hole is connected to each other by a metal silicide layer selectively formed therein, and a polycrystalline thin film serving as a part of the second load element is formed thereon. A semiconductor memory device characterized by the following. 2. A MOS transistor forming step, an insulating film side wall forming step, a first metal silicide layer forming step, a connection hole forming step, a second metal silicide layer forming step, a load element forming step. Wherein the MOS transistor forming step comprises the steps of: forming a first driving MOS transistor, a first transfer MOS transistor, and a second driving MOS transistor on a surface of a semiconductor substrate; And a second transfer MOS transistor. The insulating film sidewall forming step is a process of forming an insulating film sidewall on a side surface of a gate electrode of each of the MOS transistors.
In the first metal silicide layer forming step, after forming the first metal layer on the entire surface of the substrate, the drain region,
The first metal silicide layer is selectively formed on the source region and the upper surface of the gate electrode. The step of forming a connection hole includes removing an unreacted layer of the first metal layer.
Forming an interlayer insulating film over the entire surface of the substrate, selectively etching the interlayer insulating film, and forming a first connection hole reaching the first drain region and the third gate electrode; the third drain region; Forming a second connection hole reaching the first gate electrode so that a sidewall of an insulating film does not remain on the side surface of each gate electrode inside each connection hole; and forming a second metal silicide layer. Forming a second metal layer on the entire surface of the substrate and then selectively forming a second metal silicide layer on the drain region, the upper surface of the gate electrode, and the side surface of the gate electrode at the bottom of each connection hole by heat treatment; And the load element forming step is the second step.
Removing a non-reacted layer of the metal layer, forming a polycrystalline thin film over the entire surface of the substrate, and forming a load element having the polycrystalline thin film as a constituent element. Production method. 3. A process in which a surface of the second metal silicide layer is treated in an ammonia plasma and nitrided between a step of removing an unreacted layer of the second metal layer and a step of forming a load element. 3. The method according to claim 2, further comprising the step of forming a film.