JP2000232076A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a high speed operation for a semiconductor device by making the device in the form of a high-speed logic, having a silicide structure having a silicided gate electrode and providing operating characteristics equivalent to those of an independent high-speed logic element to the device. SOLUTION: This semiconductor device includes first and second semiconductor devices 30 and 40 on an identical semiconductor substrate 11. In the first device 30, cobalt silicide films 36 to 38 are formed self-aligned on surfaces of source and drain diffused layers 34 and 35 and on an upper surface of a gate wiring 31 as a compound films of a semiconductor and a metal. In the second device 40, a compound film of semiconductor and metal of a tungsten silicide film 18 as a metallic film is formed on an upper part of at least a gate wiring 41. And a nitride silicon film 19 and a sidewall insulating film 20, having an etching rate slower than that of an interlayer insulating film 22, are formed around the gate wiring 41, and a contact hole 23 is made self- alignedly therein.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device in which a memory device and a logic device are mixed and a method of manufacturing the same.

[0002]

2. Description of the Related Art Reduction of system cost, lower power consumption,
For the purpose of speeding up, a memory device and a logic device are mounted on the same chip. In particular,
In application to three-dimensional graphics and the like, a memory device having a wide bandwidth is required for high-speed data transfer, and this is achieved by embedding a large-capacity memory device in a high-speed logic device.

In a high-speed logic device, a self-aligned silicide (hereinafter referred to as salicide) in which a compound of a semiconductor and a metal is formed in a self-aligned manner on a source / drain diffusion layer and a gate electrode for the purpose of reducing parasitic resistance and parasitic capacitance. (Self-Aligned Silicidation)] is applied, and the resistance of the source and drain diffusion layers is reduced to several Ω.

On the other hand, in a memory device, a self-aligned contact (hereinafter referred to as SAC (Self-Aligned Contact)) for forming a contact hole in a self-aligned manner with respect to a wiring layer is used for the purpose of reducing the memory size. ing. In particular, in recent years, a manufacturing method has been adopted in which a contact hole is formed by covering the periphery of a wiring layer with an insulating film having a lower etching rate than a film to be etched when forming the contact hole.

[0005]

However, when a high-speed logic device and a memory device are mixedly mounted on the same semiconductor substrate (same chip), the following problems occur. In the high-speed logic section, the gate wiring (including the gate electrode) and the source and drain diffusion layers are simultaneously salicided. On the other hand, in the memory device, the above-described SAC structure is employed to reduce the memory cell size. Therefore, the gate wiring (including the gate electrode) of the memory portion is covered with an insulating film having a low etching rate. Therefore, when the high-speed logic unit is salicidized, the source / drain diffusion layers of the memory unit and the gate wiring cannot be salicidated at the same time.

Conventionally, the following method has been used. In order to reduce the wiring resistance without using a salicide gate for both the high-speed logic device and the memory device, a structure consisting of a two-layer film of polysilicon and a compound of metal and silicon (polycide gate structure) or polysilicon And a metal (polymetal gate structure) composed of two or more layers.

In this case, there is a problem that each cell of the high-speed logic device used in the mixed LSI of the high-speed logic device and the memory device cannot be shared with the cell of the logic LSI without the memory device. That is, in the case of polycide gate,
It is difficult to make the resistance exactly the same as the salicide gate, and the transistor characteristics are different between the two.

[0008]

SUMMARY OF THE INVENTION The present invention is directed to a semiconductor device and a method of manufacturing the same to solve the above-mentioned problems.

A semiconductor device according to the present invention is formed on a semiconductor substrate. A compound film of a semiconductor and a metal is formed in a self-aligned manner on the surface of a source / drain diffusion layer and the upper surface of a gate electrode. A first semiconductor device and a second semiconductor device formed on the same semiconductor substrate and having a compound film or a metal film of a semiconductor and a metal formed on at least an upper surface of a gate electrode And
An insulating film is formed around the gate electrode of the second semiconductor device, the insulating film having a lower etching rate than the insulating film in which the contact holes leading to the source and drain diffusion layers of the second semiconductor device are formed. is there.

In the above semiconductor device, a compound film of a semiconductor and a metal is formed in a self-aligned manner on the surfaces of the source / drain diffusion layers of the first semiconductor device and the upper surface of the gate electrode. A high-speed logic having a silicide salicide structure is obtained, and has the same operating characteristics as those obtained by forming a high-speed logic element alone, thereby achieving high-speed operation. On the other hand, around the gate electrode of the second semiconductor device, an insulating film having a lower etching rate than the insulating film in which the contact holes leading to the source and drain diffusion layers of the second semiconductor device are formed. Therefore, the second semiconductor device is self-aligned.
The memory device has a contact (SAC) structure. Therefore, the high-speed logic element and the memory element can be mixedly mounted on the same semiconductor substrate.

According to the method of manufacturing a semiconductor device of the present invention, a first semiconductor device having a gate electrode, a source and a drain diffusion layer on a semiconductor substrate, and a second semiconductor having a gate electrode, a source and a drain diffusion layer are provided. Forming a semiconductor film forming a gate electrode of a first semiconductor device and a semiconductor film forming a gate electrode of a second semiconductor device with the same semiconductor film in a method of manufacturing a semiconductor device forming the device Forming an etching stopper film having a lower etching rate than a film forming a gate electrode of the second semiconductor device on a region of the semiconductor film where the first semiconductor device is formed; In a state where the semiconductor film in the region where the gate is to be formed is covered with the etching stopper film, the second
Forming the gate electrode of the first semiconductor device by processing the gate electrode of the semiconductor device by etching, and then processing the semiconductor film in the region where the first semiconductor device is formed.

Further, after processing the semiconductor film in a region where the first semiconductor device is to be formed to form a gate electrode of the first semiconductor device, a film that does not cause a silicide reaction so as to cover the second semiconductor device is formed. Then, the first semiconductor device is formed in a salicide structure. Further, an insulating film having an etching rate lower than that of the insulating film in which a contact hole leading to the source / drain diffusion layer of the second semiconductor device is formed around the gate electrode of the second semiconductor device.

In the method of manufacturing a semiconductor device, the semiconductor film forming the gate electrode of the first semiconductor device and the semiconductor film forming the gate electrode of the second semiconductor device are formed of the same semiconductor film. Since an etching stopper film having an etching rate lower than that of the film forming the gate electrode of the second semiconductor device is formed over the region of the same semiconductor film where the first semiconductor device is formed, the second semiconductor device is formed. It is possible to form a film that forms a polycide structure or a polymetal structure that forms the gate electrode on the semiconductor film in the region where the film is to be formed. Then, the gate electrode of the second semiconductor device is processed by etching in a state where the semiconductor film in the region where the first semiconductor device is formed is covered with the etching stopper film. It can be processed into a structure or a polymetal structure.

In addition, after processing the semiconductor film in the region where the first semiconductor device is to be formed to form the gate electrode of the first semiconductor device, a film that does not cause a silicide reaction to cover the second semiconductor device is formed. After the formation, the first semiconductor device is formed into a salicide structure, so that the first semiconductor device has the same characteristics as those formed by high-speed logic alone.

Further, an insulating film having a lower etching rate than an insulating film in which a contact hole leading to a source / drain diffusion layer of the second semiconductor device is formed around a gate electrode of the second semiconductor device. Therefore, the second semiconductor device is formed in a memory element having a self-aligned contact (SAC) structure.

As described above, the first semiconductor device and the second semiconductor device can be mixedly mounted on the same semiconductor substrate. The semiconductor device is mixedly mounted on the same semiconductor substrate as a memory element.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment According to a Semiconductor Device of the Present Invention
Will be described with reference to the schematic cross-sectional view of FIG. FIG. 1 illustrates a semiconductor device in which high-speed logic and a DRAM are mounted as an example.

As shown in FIG. 1, an N-type semiconductor substrate (for example, silicon substrate 11) has a depth of, for example, 400 nm.
The element isolation is formed by the field insulating film 12 embedded in the trench. Further, a P-type well 13 and an N-type well (not shown) are formed in the semiconductor substrate 11, and a gate insulating film 14 is formed on the surface of the semiconductor substrate 11 to a thickness of, for example, 10 nm. Have been.

The semiconductor substrate 11 (gate insulating film 14)
In the high-speed logic formation region, a gate wiring 31 (including a gate electrode) including a semiconductor film 15 formed by depositing a polysilicon film to a thickness of 200 nm, for example, is formed. A side wall insulating film 20 is formed on the side wall of the gate wiring 31.

A source / drain diffusion layer 34 is formed on the semiconductor substrate 11 on one side of the gate wiring 31 via an LDD 32, and the LDD 32 is formed on the semiconductor substrate 11 on the other side.
A source / drain diffusion layer 35 is formed via 33. The LDDs 32 and 33 are formed by implanting, for example, arsenic into the semiconductor substrate 11 at a dose of 3 × 10 ¹⁴ / cm ² . The source / drain diffusion layers 34 and 35 are formed, for example, by adding arsenic to the semiconductor substrate 11 at 3 × 10 3.
It is formed by ion implantation at a dose of ¹⁵ / cm ² . The arsenic is also doped in the gate wiring 31.

On the source / drain diffusion layer 34,
As a compound film of a semiconductor and a metal, for example, a cobalt silicide film 36 is formed, similarly, a cobalt silicide film 38 is formed also on the source / drain diffusion layers 35, and a cobalt silicide film 37 is formed also on the gate wiring 31. ing. Thus, the first semiconductor device 30 having the salicide structure is formed.

On the other hand, in the region of the semiconductor substrate 11 (gate insulating film 14) where the DRAM is to be formed, a semiconductor film 15 made of the same polysilicon film as the semiconductor film 15 forming the gate wiring 31 is formed. And the gate wiring 41
(Including a gate electrode). This semiconductor film 15 contains, for example, 3 × 1 phosphorus as an N-type impurity.
It is doped at a dose of 0 ¹⁵ / cm ² . A compound film of a semiconductor and a metal or a metal film is formed on the semiconductor film 15. Here, as an example, a tungsten silicide film 18 of a compound film of a semiconductor and a metal is formed to a thickness of, for example, 150 nm.
Further, a silicon nitride film 19 is formed. As described above, the gate wiring 41 is composed of the semiconductor film 15 made of a polysilicon film and the tungsten silicide film 18 formed thereon, and the silicon nitride film 19 is further formed. A side wall insulating film 20 is formed on the side wall of the gate wiring 41.

A source / drain diffusion layer 45 is formed on the semiconductor substrate 11 on one side of the gate wiring 41 (41a) via the LDD 42, and a source / drain diffusion layer 45 is formed on the semiconductor substrate 11 on the other side via the LDD 43. A source / drain diffusion layer 46 is formed on the semiconductor substrate 11 on one side of the gate wiring 41 (41b) by LDD.
It is shared with the source / drain diffusion layer 46 formed through the gate 43. Further, the semiconductor substrate 11 on the other side has L
Source / drain diffusion layers 47 are formed via the DD 44. Thus, the second semiconductor device 40 is formed.

Each of the LDDs 42 to 44 is a semiconductor substrate 1
1 is obtained by doping phosphorus with a dose of 3 × 10 ¹³ / cm ^2.
5 to 47: 3 × 10 ¹³ / cm 3 of phosphorus on the semiconductor substrate 11
It was obtained by doping at a dose of ² .

Further, a silicon oxide film 21 having a thickness of, for example, 30 nm is formed as a film that does not cause a silicide reaction in a state of covering the second semiconductor device 40.
On the semiconductor substrate 11, an interlayer insulating film 22 is formed of a silicon oxide film having a thickness of, for example, 600 nm so as to cover the first and second semiconductor devices 30 and 40.
The surface of the interlayer insulating film 22 is flattened.

Further, a contact hole 23 with an upper wiring layer in a DRAM formation region is formed in the interlayer insulating film 22 in a self-aligned manner. Here, the side wall insulating film 20 made of a silicon nitride film and the gate wiring 4
The contact hole 23 is formed in a self-aligned manner with the silicon nitride film 19 on the substrate 1 serving as an etching stopper.
A plug 24 is formed inside the contact hole 23.

As described above, the first semiconductor device 30 is formed in the formation region of the high-speed logic, and the second semiconductor device 40 serving as a memory cell is formed in the formation region of the DRAM, thereby forming a system LSI.

In the above semiconductor device, the first semiconductor device 3
A compound film of a semiconductor and a metal, that is, a cobalt silicide film 36 to 38 in the above case is self-aligned on the surfaces of the source / drain diffusion layers 34 and 35 and the upper surface of the gate wiring (including the gate electrode) 31. Therefore, the high-speed logic has a salicide structure in which the gate wiring 31 is silicided, and has the same operating characteristics as those formed independently of the high-speed logic element. can get.

On the other hand, the etching rate around the gate wiring (including the gate electrode) 41 of the second semiconductor device 40 is lower than that of the interlayer insulating film 22 where the contact hole 23 leading to the source / drain diffusion layer 46 is formed. As a slow insulating film, a sidewall insulating film 20 made of a silicon nitride film
And the silicon nitride film 19 are formed, the second semiconductor device 40 becomes a memory element having a self-aligned contact (SAC) structure. Therefore, the distance between the contact hole 23 and the gate wiring 41 can be reduced, and the memory cell size can be reduced.

The first semiconductor device 3 of high-speed logic
0 denotes a gate wiring 31 and a source / drain diffusion layer 34;
35 is changed to cobalt silicide, and the memory element of the DRAM is provided with a tungsten silicide film 18
And a semiconductor film 15 made of a polysilicon film using a tungsten polycide structure having two layers, and the source and drain diffusion layers 45 to 47 use silicon layers doped with ordinary impurities. That is, the source and drain diffusion layers 4
No salicide was used for 5-47. The reason why the source / drain diffusion layers 45 to 47 are not salicided is that the data retention characteristics are deteriorated due to an increase in junction leak current due to the salicidation.

Next, a second embodiment according to the semiconductor device of the present invention will be described with reference to the schematic sectional view of FIG. FIG. 2 illustrates, as an example, a semiconductor device in which high-speed logic and an SRAM are mounted together.

As shown in FIG. 2, an N-type semiconductor substrate (for example, silicon substrate 11) has a depth of, for example, 400 nm.
The field insulating film 12 is embedded in the trench. Further, a P-type well 13 and an N-type
A mold well (not shown) is formed, and a gate oxide film 14 is formed on the surface of the semiconductor
It is formed to a thickness of nm.

The semiconductor substrate 11 (gate insulating film 14)
In the high-speed logic formation region, a gate wiring 31 having a semiconductor film 15 formed by depositing a polysilicon film to a thickness of 200 nm, for example, as a component is formed. A side wall insulating film 20 is formed on the side wall of the gate wiring 31.

A source / drain diffusion layer 34 is formed on the semiconductor substrate 11 on one side of the gate wiring 31 via an LDD 32, and the LDD 32 is formed on the semiconductor substrate 11 on the other side.
A source / drain diffusion layer 35 is formed via 33. The LDDs 32 and 33 are formed by implanting, for example, arsenic into the semiconductor substrate 11 at a dose of 3 × 10 ¹⁴ / cm ² . The source / drain diffusion layers 34 and 35 are formed, for example, by adding arsenic to the semiconductor substrate 11 at 3 × 10 3.
It is formed by ion implantation at a dose of ¹⁵ / cm ² . The arsenic is also doped in the gate wiring 31.

On the source / drain diffusion layer 34, a cobalt silicide film 36 made of a compound film of a semiconductor and a metal is formed. On the source / drain diffusion layer 35, a cobalt silicide film 38 is formed. Is formed with a cobalt silicide film 37. As described above, the first semiconductor device 30 having the salicide structure
Are formed.

On the other hand, a semiconductor film 15 made of the same polysilicon film as the semiconductor film 15 constituting the gate wiring 31 is formed in the SRAM formation region of the semiconductor substrate 11 (gate insulating film 14). A part of the gate wiring 41 is formed. The semiconductor film 15 is doped with, for example, phosphorus as an N-type impurity at a dose of 3 × 10 ¹⁵ / cm ² . A compound film of a semiconductor and a metal or a metal film is formed on the semiconductor film 15. Here, as an example, a tungsten silicide film 18 of a compound film of a semiconductor and a metal is formed to a thickness of, for example, 150 nm. Further, a silicon nitride film 19 is formed. As described above, the gate wiring 41 is composed of the semiconductor film 15 made of a polysilicon film and the tungsten silicide film 18 formed thereon, and the silicon nitride film 19 is further formed. A side wall insulating film 20 is formed on the side wall of the gate wiring 41.

A source / drain diffusion layer 45 is formed on the semiconductor substrate 11 on one side of the gate wiring 41 (41a) via the LDD 42, and a source / drain diffusion layer 45 is formed on the semiconductor substrate 11 on the other side via the LDD 43. A source / drain diffusion layer 46 is formed on the semiconductor substrate 11 on one side of the gate wiring 41 (41b) by LDD.
It is shared with the source / drain diffusion layer 46 formed through the gate 43. Further, the semiconductor substrate 11 on the other side has L
Source / drain diffusion layers 47 are formed via the DD 44. On the source and drain diffusion layers 45 to 47, cobalt silicide films 48 to 50 are formed. Thus, the second semiconductor device 40 is formed.

Each of the LDDs 42 to 44 may be ion-implanted under the same conditions as those of the LDDs 32 and 33 of the first semiconductor device 30.
7 may be ion-implanted under the same conditions as those of the source / drain diffusion layers 45 to 47 of the first semiconductor device 30.

On the semiconductor substrate 11, the first,
The interlayer insulating film 2 covers the second semiconductor devices 30 and 40.
2 is formed of, for example, a silicon oxide film having a thickness of 600 nm. The surface of the interlayer insulating film 22 is flattened. Further, in the interlayer insulating film 22, a contact hole 23 with an upper wiring in a formation region of the DRAM is formed in a self-aligned manner. Here, the side wall insulating film 20 made of a silicon nitride film and the gate wiring 41 are formed.
The contact hole 23 is formed in a self-aligned manner with the upper silicon nitride film 19 serving as an etching stopper.
A plug 24 is formed inside the contact hole 23.

As described above, the first semiconductor device 30 constitutes a high-speed logic, and the second semiconductor device 40 constitutes a system LSI constituting a memory cell of an SRAM.

Also in the second embodiment, the same operation and effect as described in the first embodiment can be obtained.
Although the cobalt silicide films 48 to 50 are formed on the source and drain diffusion layers 45 to 47 of the second semiconductor device 40, in the case of the SRAM, the cobalt silicide films 48 to 50 have a sufficient data holding ability. There is no problem even if ~ 50 is formed.

Next, a first embodiment of the method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. 3 to 5, as an example, FIG.
A method for manufacturing a semiconductor device in which the high-speed logic described above and the DRAM are mounted together will be described. 3 to 5, the same components as those described with reference to FIG. 1 are denoted by the same reference numerals.

As shown in FIG. 3A, an N-type semiconductor substrate (for example, silicon substrate 11) having a depth of, for example, 400 using an ordinary trench element isolation technique.
The field insulating film 12 is buried in the trench of nm. Preferably, the surface of the semiconductor substrate 11 is flattened by, for example, chemical mechanical polishing.

Next, by ion implantation, for example, P
A mold well 13 and an N-type well (not shown) are formed. At this time, in the case where the P-type well 13 is formed by resist coating and lithography technology, a resist mask covering an N-type well formation region is formed,
When an N-type well is formed, a resist mask covering a formation region of the P-type well 13 is formed. afterwards,
For example, a gate oxide film 14 having a thickness of, for example, 10 nm is formed on the surface of the semiconductor substrate 11 in a steam atmosphere at 900 ° C.

Next, as shown in FIG. 3B, the semiconductor substrate 11 (the gate insulating film 1) is formed by, for example, a CVD method.
4) A semiconductor film 15 for forming a gate electrode or a part thereof is formed by depositing, for example, a polysilicon film to a thickness of 200 nm. Subsequently, an etching stopper film 16 serving as a mask when etching the gate electrode of the DRAM is formed on the semiconductor film 15 by the CVD method. The etching stopper film 16 may be used as a mask when etching the gate electrode of the DRAM, that is, a film having an etching rate lower than that of the film constituting the gate electrode of the DRAM. Therefore, the etching stopper film 16 is formed of, for example, a silicon oxide film having a thickness of 20 nm.

After forming a resist film 17 covering the high-speed logic formation region by the usual technique of forming a resist mask, the etching stopper film 16 in the DRAM formation region is etched using the resist film 17 as a mask, for example, by etching. Is selectively removed.

Then, for example, by ion implantation, D
The semiconductor film 15 in the formation region of the RAM is doped with, for example, phosphorus as an N-type impurity by an implantation energy of 30 as an example.
The keV and the dose are set to 3 × 10 ¹⁵ / cm ² , and ions are implanted to make it N-type.

Next, as shown in FIG. 3C, for example, a tungsten silicide film 18 is deposited to a thickness of 150 nm on the semiconductor film 15 and the etching stopper film 16 by, for example, a CVD method. C
A silicon nitride film 19 is deposited by the VD method. Then, by the usual resist coating and lithography technology, DR
After forming a mask for patterning the gate wiring layer in the formation region of the AM with a resist film (not shown), the silicon nitride film 19, the tungsten silicide film 18, and the semiconductor film 15 are formed using the resist film as an etching mask. Is etched to form a gate wiring 41. In this etching, since the etching stopper film 16 made of a silicon oxide film is formed on the semiconductor film 15 in a portion other than the formation region of the DRAM, the etching stops on the etching stopper film 16.

After that, for example, by ion implantation, D
N-type LDDs 42, 43, and 44 are formed on the semiconductor substrate 11 (well region) in the RAM formation region. As the ion implantation conditions at this time, as an example, phosphorus is used as the dopant, the implantation energy is 30 keV,
The dose was set to 3 × 10 ¹³ / cm ² .

Next, as shown in FIG. 4D, a mask for patterning a gate wiring layer in a high-speed logic formation region is formed by a resist film (not shown) by a normal resist coating and lithography technique. Using the resist film as an etching mask, the etching stopper film 16 made of silicon oxide and the semiconductor film 15 made of polysilicon are continuously etched to form the gate wiring 31.

After that, for example, by ion implantation, P
A LDD (not shown) and N-type LDDs 32 and 33 in a high-speed logic formation region are formed. At that time, P
In the case of forming an LDD of the type, for example, boron difluoride (BF ₂ ) is used as a dopant, and ions are implanted under the conditions of an implantation energy of 50 keV and a dose of 3 × 10 ¹⁴ / cm ² . When the N-type LDDs 32 and 33 are formed, as an example, arsenic is used as a dopant, the implantation energy is 50 keV, and the dose is 3 ×.
Ion implantation is performed under the condition of 10 ¹⁴ / cm ² .

At the time of each ion implantation, a P-type LD is formed by resist coating and lithography.
When forming D, an N-type LDD formation region, DRA
A resist mask covering the formation region of M and the like is formed in advance,
In the case of forming an N-type LDD, a resist mask which covers a formation region of a P-type LDD, a formation region of a DRAM, and the like is formed in advance. In the case of ion implantation, the gate wiring 31 also serves as a mask.

As shown in FIG. 4 (5), for example, CVD
By a method, a silicon nitride film is deposited to a thickness of, for example, 150 nm so as to cover the gate wirings 31 and 41. Then, the silicon nitride film is etched back by etching the entire surface, and a sidewall insulating film 20 is formed on the side walls of each of the gate wirings 31 and 41. At this time, in the portion other than the DRAM formation region, the etching stopper film 16 made of the silicon oxide film remaining on the gate wiring 31 is formed.
[See (4) in FIG. 4] is also removed at the same time.

Thereafter, for example, by ion implantation, P
P-type source and drain regions (not shown) are formed in the semiconductor substrate on both sides of the gate wiring (not shown) in the region where the transistor of the type is formed. Source and drain diffusion layers 45 to 47 are formed in the semiconductor substrate 11 on both sides of the gate wiring 41 in the DRAM formation region with the LDDs 42 to 44 interposed between the gate electrodes 41. Specifically, the semiconductor substrate 1 on one side of the gate wiring 41 (41a)
1, a source / drain diffusion layer 45 is formed via the LDD 42, a source / drain diffusion layer 46 is formed on the other side via the LDD 43, and the gate wiring 41 (4
1b) A source / drain diffusion layer 46 (same as the source / drain diffusion layer 46) is formed on one side of the semiconductor substrate 11 via the LDD 43, and the LDD is formed on the other side.
A source / drain diffusion layer 47 is formed via 44.
Thus, the second semiconductor device 40 is formed.

Further, a source / drain diffusion layer 34 is formed on the semiconductor substrate 11 on one side of the gate wiring 31 via the LDD 32 in the formation region of the high-speed logic, and a source / drain diffusion layer 34 is formed on the semiconductor substrate 11 on the other side via the LDD 33. The layer 35 is formed. Thus, first, the semiconductor device 30 is formed.

In the case of forming source / drain diffusion layers (not shown) in the P-type region, boron difluoride (BF ₂ ) is used as a dopant and the implantation energy is 50 ke.
V ions are implanted under the conditions of a dose of 3 × 10 ¹⁵ / cm ² .

When forming the source / drain diffusion layers 34 and 35 of the N-type region in the high-speed logic formation region, arsenic is used as a dopant and the implantation energy is 5
Ion implantation is performed under the conditions of 0 keV and a dose of 3 × 10 ¹⁵ / cm ² .

When forming the source / drain diffusion layers 45 to 47 in the N-type region in the formation region of the DRAM,
Using phosphorus as a dopant and increasing the implantation energy to 30k
Ion implantation is performed under the conditions of eV and a dose of 3 × 10 ¹³ / cm ² .

In the above-mentioned ion implantation, impurities are simultaneously doped in the gate wiring 31 in portions other than the DRAM.

Then, the impurities are activated by performing a heat treatment for 20 minutes in a nitrogen atmosphere at 900 ° C., for example, so that the source and drain diffusion layers 45 to 47, 34 and 35 are formed.
To form

Next, as shown in FIG. 4 (6), a silicon oxide film 21 having a thickness of 30 nm is deposited on the entire surface of the semiconductor substrate 11 as a film which does not cause a silicide reaction. Thereafter, a resist pattern (not shown) is formed to cover the formation region of the DRAM by a normal resist coating and lithography technique, and then the silicon oxide film 21 is etched using the resist pattern as a mask to remove the region other than the formation region of the DRAM. The silicon oxide film 21 is removed. That is, the silicon oxide film 21 is left so as to cover the second semiconductor device 40.

Then, after a cobalt film is deposited to a thickness of 30 nm, for example, on the entire surface of the semiconductor substrate 11 by sputtering, and then subjected to a heat treatment, thereby forming a film on the silicon and the polysilicon film directly in contact with the cobalt film. Then, cobalt silicide films 36, 37 and 38 are formed. That is, a cobalt silicide film 36 is formed on the source / drain diffusion layers 34, a cobalt silicide film 38 is formed on the source / drain diffusion layers 35, and a cobalt silicide film 37 is formed on the gate wiring 31. Thereafter, the semiconductor substrate 11 is immersed in an etching solution of sulfuric acid and a hydrogen peroxide solution to remove cobalt in a region that is not silicided.

Next, as shown in FIG. 5 (7), a silicon oxide film serving as an interlayer insulating film 22 is deposited to a thickness of, for example, 600 nm on the semiconductor substrate 11 by, for example, a CVD method. After that, the interlayer insulating film 2 is formed using a CMP method.
2 is flattened. Further, the known interlayer insulating film 22
By a process of forming a contact hole in the substrate (resist coating, formation of a resist mask by lithography technology, and etching using the resist mask)
Contact hole 23 with the upper wiring in the formation region of AM
Open. Here, the silicon oxide film forming the interlayer insulating film 22 is etched under an etching condition in which the etching rate of the side wall insulating film 20 made of the silicon nitride film and the silicon nitride film 19 on the gate wiring 41 is large. Then, the contact hole 23 is formed in a self-aligned manner so that the underlying silicon nitride film serves as a mask.

Thereafter, as shown in FIG. 5 (8), a plug 24 is formed inside the contact hole 23 by using a conventionally known process. Further, after forming the capacitor 51 of the DRAM, an interlayer insulating film 52 is formed so as to cover the capacitor 51. Next, a contact hole 53 communicating with the source / drain diffusion layer 35 in the high-speed logic formation region is formed in the interlayer insulating films 52, 22 and the like.
And a metal wiring 55 is formed on the interlayer insulating film 52 to form a system LSI in which high-speed logic and DRAM are mounted together.

In the first embodiment relating to the method for manufacturing a semiconductor device, the semiconductor film 15 forming the gate wiring (gate electrode) 31 of the first semiconductor device 30 and the gate wiring of the second semiconductor device 40 are formed. (Gate electrode) 41 and the semiconductor film 15 constituting the same film are formed of the same film, and the etching rate of the semiconductor film 15 on the region where the first semiconductor device 30 is formed is lower than that of the film constituting the gate wiring 41. Since the slow etching stopper film 16 is formed,
The gate wiring 41 of the second semiconductor device 40 is
Can be formed in a polycide structure or a polymetal structure. Then, the gate wiring 41 is processed by etching in a state where the semiconductor film 15 in the region where the first semiconductor device 30 is to be formed is covered with the etching stopper film 16, so that the gate wiring 41 is processed into a polycide structure or a polymetal structure. It becomes possible.

Moreover, after processing the semiconductor film 15 in the region where the first semiconductor device 30 is to be formed to form the gate wiring 31, silicon oxide is formed as a film that does not cause a silicide reaction so as to cover the second semiconductor device 40. Forming a film 21;
After that, since the first semiconductor device 30 is formed in a salicide structure, the first semiconductor device 30 has the same characteristics as those formed by high-speed logic alone.

Further, as an insulating film having a lower etching rate than the interlayer insulating film 22 in which the contact hole 23 leading to the source / drain diffusion layer 46 is formed around the gate wiring 41 of the second semiconductor device 40, silicon nitride is used. Since the sidewall insulating film 20 and the silicon nitride film 19 are formed, the second semiconductor device 40 is formed as a memory element having a self-aligned contact (SAC) structure.

As described above, the first semiconductor device 3
0 and the second semiconductor device 40 can be mixedly mounted on the same semiconductor substrate 11, so that the first semiconductor device 30 is a high-speed logic and the second semiconductor device 40 is a memory element. 11 are mixed.

Next, a description will be given of a second embodiment of the semiconductor device manufacturing method according to the present invention. Here, as an example, the high-speed logic and the SRAM described with reference to FIG.
A method for manufacturing a semiconductor device in which the above is mixed will be described. In the following description, the same components as those described with reference to FIG.

The manufacturing method of this structure does not form the silicon oxide film 21 described with reference to FIG. 4 (6) in the manufacturing method described with reference to FIGS. Then, the cobalt silicide film 36 of the first semiconductor device 30
To 38 simultaneously with the source and drain regions 4 of the SRAM section.
The cobalt silicide films 48 to 50 may be formed on the layers 5 to 47 as shown in FIG. The source and drain of the SRAM are different from the source and drain of the DRAM, and impurities may be ion-implanted under the same conditions as in the high-speed logic section.

In the first semiconductor device 30 serving as the high-speed logic, the surface of the gate wiring 31 and the surfaces of the source / drain diffusion layers 34 and 35 are converted to cobalt silicide to form an SRAM.
The part is that the tungsten silicide film 18 is
And a tungsten silicide structure consisting of two layers of a polysilicon film and a semiconductor film 15 made of a polysilicon film. The source and drain diffusion layers 45 to 47 are made of cobalt silicide films 48 to 5.
A salicide structure in which 0 is formed is used. In the SRAM having such a configuration, especially when a 6-transistor type memory cell is used, the source / drain diffusion layers 45 to 45 are used.
Even if there is an increase in junction leak current due to the salicidation of 47, deterioration of the data retention characteristics does not pose a problem.

Further, the gate wiring 4 having the polycide structure is used.
In No. 1, since the periphery is covered with the silicon nitride film 19 and the side wall insulating film 20 which is a silicon nitride film, the above-mentioned silicon nitride film Serves as an etching stopper to stop etching. Therefore, the contact hole 23 is formed in a self-aligned manner with respect to the gate wiring 41, and the distance between the contact hole 23 and the gate wiring 41 is reduced, so that the memory cell size can be reduced.

Although the tungsten silicide film 18 is used for the gate wiring 41, at least one of a titanium silicide film, a cobalt silicide film, and a molybdenum silicide, or a plurality of kinds including a tungsten silicide film is used instead. The used polycide structure can be used. Alternatively, a polymetal structure using at least one or more of a titanium film, a tungsten film, a tantalum film, a cobalt film, an aluminum film, and a copper film can be used. In the case of a polymetal structure, it is preferable to form a barrier metal such as tungsten nitride, titanium nitride, or tantalum nitride between the polysilicon film and the metal film.

[0074]

As described above, according to the semiconductor device of the present invention, the compound film of the semiconductor and the metal is self-aligned with the surface of the source / drain diffusion layer and the upper surface of the gate electrode of the first semiconductor device. The high-speed logic has a salicide structure in which the gate electrode is silicided, and has the same operating characteristics as those formed independently of the high-speed logic element, so that high-speed operation can be obtained. . On the other hand, around the gate electrode of the second semiconductor device, an insulating film having a lower etching rate than the insulating film in which the contact holes leading to the source and drain diffusion layers of the second semiconductor device are formed. Therefore, the second semiconductor device is a memory element having a self-aligned contact structure. Therefore, the high-speed logic element and the memory element can be mixedly mounted on the same semiconductor substrate.

According to the method of manufacturing a semiconductor device of the present invention,
A semiconductor film forming a gate electrode of the first semiconductor device;
A semiconductor film forming a gate electrode of the second semiconductor device is formed of the same semiconductor film, and a gate electrode of the second semiconductor device is formed over a region of the same semiconductor film where the first semiconductor device is formed. Since the etching stopper film having an etching rate lower than that of the constituent film is formed, a film forming the polycide structure or the polymetal structure forming the gate electrode is formed on the semiconductor film in the region where the second semiconductor device is formed. be able to. Then, the gate electrode of the second semiconductor device is processed by etching in a state where the semiconductor film in the region where the first semiconductor device is formed is covered with the etching stopper film, so that the gate electrode of the second semiconductor device has a polycide structure. Alternatively, it can be processed into a polymetal structure.

Further, the semiconductor film in the region where the first semiconductor device is to be formed is processed to form a gate electrode of the first semiconductor device, and a film that does not cause a silicide reaction is formed so as to cover the second semiconductor device. After that, the first semiconductor device is formed in a salicide structure, so that the first semiconductor device can be formed to have the same characteristics as those formed by high-speed logic alone.

Further, an insulating film having a lower etching rate than the insulating film in which the contact holes leading to the source and drain diffusion layers of the second semiconductor device are formed around the gate electrode of the second semiconductor device. The second semiconductor device can be formed in a memory element having a self-aligned contact structure.

Therefore, it is possible to mix the first semiconductor device serving as a high-speed logic and the second semiconductor device serving as a memory element on the same semiconductor substrate.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a first embodiment according to a semiconductor device of the present invention.

FIG. 2 is a schematic configuration sectional view showing a second embodiment according to the semiconductor device of the present invention.

FIG. 3 is a manufacturing process diagram showing a first embodiment according to a method for manufacturing a semiconductor device of the present invention.

FIG. 4 is a manufacturing step diagram (continued) showing the first embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 5 is a manufacturing step diagram (continued) showing the first embodiment of the method for manufacturing a semiconductor device of the present invention.

[Explanation of symbols]

11: semiconductor substrate, 18: tungsten silicide film,
31, 41 ... gate wiring (gate electrode), 34, 35 ...
Source, drain diffusion layers, 36, 37, 38... Cobalt silicide film, 30... First semiconductor device, 40.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/11 H01L 27/10 381 27/10 481 681F 27/108 21/8242 F term (Reference) 4M104 AA01 BB01 BB19 CC01 CC05 DD02 DD43 DD72 DD84 FF14 GG14 GG16 5F048 AA09 AB01 AB03 AC01 BA01 BB05 BB08 BB09 BB10 BC06 BF06 BF07 BG14 DA27 5F083 AD01 AD10 AD49 BS05 BS17 BS19 BS23 BS26 BS40 JA32 PR35PR03 PR05

Claims (15)

[Claims] 1. A first semiconductor device formed on a semiconductor substrate, wherein a compound film of a semiconductor and a metal is formed in a self-aligned manner on surfaces of source and drain diffusion layers and an upper surface of a gate electrode. And a second semiconductor device formed on the semiconductor substrate and having a compound film of a semiconductor and a metal or a metal film formed on at least an upper surface of a gate electrode. . 2. An insulating film having a lower etching rate than an insulating film in which a contact hole leading to a source / drain diffusion layer of the second semiconductor device is formed around a gate electrode of the second semiconductor device. The semiconductor device according to claim 1, wherein: 3. The gate electrode of the second semiconductor device,
2. The semiconductor device according to claim 1, wherein the semiconductor device is composed of two or more layers including at least a compound film of a semiconductor and a metal or a metal film. 4. A semiconductor film forming a gate electrode of the first semiconductor device and a semiconductor film forming a gate electrode of the second semiconductor device are formed of the same film. The semiconductor device according to claim 1. 5. The semiconductor device according to claim 1, wherein the second semiconductor device has a dynamic R value.
2. The semiconductor device according to claim 1, wherein the semiconductor device comprises an AM memory cell. 6. The semiconductor device according to claim 5, wherein a film that does not cause a silicide reaction is formed so as to cover the second semiconductor device, and the first semiconductor device is formed in a salicide structure. Semiconductor device. 7. The semiconductor device according to claim 1, wherein said second semiconductor device is a static semiconductor device.
2. The semiconductor device according to claim 1, wherein the semiconductor device comprises an AM memory cell. 8. A compound of a semiconductor and a metal formed on the surfaces of the source and drain diffusion layers of the second semiconductor device, on the first semiconductor device and on the gate electrode of the second semiconductor device. 8. The semiconductor device according to claim 7, wherein a compound film of a semiconductor and a metal other than the film or the metal film is formed. 9. A semiconductor device in which a first semiconductor device having a gate electrode, a source and a drain diffusion layer, and a second semiconductor device having a gate electrode, a source and a drain diffusion layer are formed on a semiconductor substrate. In the manufacturing method, a step of forming a semiconductor film forming a gate electrode of the first semiconductor device and a semiconductor film forming a gate electrode of the second semiconductor device with the same semiconductor film; Forming an etching stopper film having a lower etching rate than a film forming a gate electrode of the second semiconductor device on a region of the film where the first semiconductor device is to be formed; After processing the gate electrode of the second semiconductor device by etching in a state where the same semiconductor film in the region to be formed is covered with the etching stopper film Forming the gate electrode of the first semiconductor device by processing the same semiconductor film in a region where the first semiconductor device is formed. 10. An insulating film having a lower etching rate than an insulating film in which a contact hole leading to a source / drain diffusion layer of the second semiconductor device is formed around a gate electrode of the second semiconductor device. The method for manufacturing a semiconductor device according to claim 9, wherein: 11. The semiconductor device according to claim 9, wherein the gate electrode of the second semiconductor device is formed of two or more layers including at least a compound film of a semiconductor and a metal or a metal film. Production method. 12. The method according to claim 9, wherein a memory cell of a dynamic RAM is formed by the second semiconductor device. 13. After processing a semiconductor film in a region where the first semiconductor device is formed to form a gate electrode of the first semiconductor device, a silicide reaction does not occur so as to cover the second semiconductor device. The method of manufacturing a semiconductor device according to claim 12, further comprising: forming a film; and forming the first semiconductor device in a salicide structure. 14. The method according to claim 9, wherein a memory cell of a static RAM is formed by the second semiconductor device. 15. A compound film of a semiconductor and a metal formed on a gate electrode of each of the first semiconductor device and the second semiconductor device on a surface of a source / drain diffusion layer of the second semiconductor device. The method according to claim 14, wherein a compound film of a semiconductor and a metal is formed separately from the metal film.