GB1418969A - Method of making integrated circuits - Google Patents

Method of making integrated circuits

Info

Publication number
GB1418969A
GB1418969A GB4821873A GB4821873A GB1418969A GB 1418969 A GB1418969 A GB 1418969A GB 4821873 A GB4821873 A GB 4821873A GB 4821873 A GB4821873 A GB 4821873A GB 1418969 A GB1418969 A GB 1418969A
Authority
GB
United Kingdom
Prior art keywords
metal
holes
strips
insulating layer
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB4821873A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Publication of GB1418969A publication Critical patent/GB1418969A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0272—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

1418969 Integrated circuits MATSUSHITA ELECTRIC INDUSTRIAL CO Ltd 16 Oct 1973 [16 Oct 1972] 48218/73 Heading H1K In making an integrated circuit, after diffusing impurity into regions at one face of a semiconductor wafer, the wafer is coated with an insulating layer and then with a photoresist layer having holes at specified positions. After etching the insulating layer to expose the wafer at the holes a metal layer is deposited overall to a thickness equal to that of the insulating layer, and the photoresist layer and overlying metal removed leaving the metal only in the holes. Finally metal strips are formed extending over and contacting this metal. As described the wafer is of N-type silicon with parallel diffused P + strips in its surface, the insulating layer of silicon dioxide 1 Á thick and the metal vapour deposited aluminium. The holes are located over the diffused strips and the metal strips, formed from an overall deposit by photoresist etching, are orthogonal to the diffused strips and of the same width as the holes.
GB4821873A 1972-10-16 1973-10-16 Method of making integrated circuits Expired GB1418969A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP47104283A JPS4960870A (en) 1972-10-16 1972-10-16

Publications (1)

Publication Number Publication Date
GB1418969A true GB1418969A (en) 1975-12-24

Family

ID=14376586

Family Applications (1)

Application Number Title Priority Date Filing Date
GB4821873A Expired GB1418969A (en) 1972-10-16 1973-10-16 Method of making integrated circuits

Country Status (7)

Country Link
US (1) US3945347A (en)
JP (1) JPS4960870A (en)
CA (1) CA989076A (en)
DE (1) DE2351943B2 (en)
FR (1) FR2203175B1 (en)
GB (1) GB1418969A (en)
NL (1) NL158026B (en)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4096623A (en) * 1974-07-01 1978-06-27 Siemens Aktiengesellschaft Thyristor and method of producing the same
FR2284981A1 (en) * 1974-09-10 1976-04-09 Radiotechnique Compelec PROCESS FOR OBTAINING AN INTEGRATED SEMICONDUCTOR CIRCUIT
US3985597A (en) * 1975-05-01 1976-10-12 International Business Machines Corporation Process for forming passivated metal interconnection system with a planar surface
US4045594A (en) * 1975-12-31 1977-08-30 Ibm Corporation Planar insulation of conductive patterns by chemical vapor deposition and sputtering
FR2340620A1 (en) * 1976-02-06 1977-09-02 Ibm MANUFACTURING PROCESS OF A LARGE-SCALE INTEGRATED DEVICE HAVING A FLAT SURFACE
US4035276A (en) * 1976-04-29 1977-07-12 Ibm Corporation Making coplanar layers of thin films
US4564997A (en) * 1981-04-21 1986-01-21 Nippon-Telegraph And Telephone Public Corporation Semiconductor device and manufacturing process thereof
JPS57176746A (en) * 1981-04-21 1982-10-30 Nippon Telegr & Teleph Corp <Ntt> Semiconductor integrated circuit and manufacture thereof
US4392298A (en) * 1981-07-27 1983-07-12 Bell Telephone Laboratories, Incorporated Integrated circuit device connection process
US4440804A (en) * 1982-08-02 1984-04-03 Fairchild Camera & Instrument Corporation Lift-off process for fabricating self-aligned contacts
JPS5982746A (en) * 1982-11-04 1984-05-12 Toshiba Corp Electrode wiring method of semiconductor device
US4631806A (en) * 1985-05-22 1986-12-30 Gte Laboratories Incorporated Method of producing integrated circuit structures
JPH02125422A (en) * 1988-11-02 1990-05-14 Nec Corp Manufacture of semiconductor device
KR0121106B1 (en) * 1994-02-15 1997-11-10 김주용 Method of metal wiring of semiconductor element
US5854128A (en) 1996-04-29 1998-12-29 Micron Technology, Inc. Method for reducing capacitive coupling between conductive lines
TW350099B (en) * 1998-01-26 1999-01-11 United Microelectronics Corp IC microfilm process
DE10208728B4 (en) * 2002-02-28 2009-05-07 Advanced Micro Devices, Inc., Sunnyvale A method for producing a semiconductor element having different metal silicide regions

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE590576A (en) * 1959-05-06
US3160534A (en) * 1960-10-03 1964-12-08 Gen Telephone & Elect Method of making tunnel diodes
US3266127A (en) * 1964-01-27 1966-08-16 Ibm Method of forming contacts on semiconductors
NL132313C (en) * 1964-12-17 1900-01-01
US3498833A (en) * 1966-07-08 1970-03-03 Fairchild Camera Instr Co Double masking technique for integrated circuit
US3840982A (en) * 1966-12-28 1974-10-15 Westinghouse Electric Corp Contacts for semiconductor devices, particularly integrated circuits, and methods of making the same
GB1286737A (en) * 1969-10-15 1972-08-23 Itt Multilevel conductive systems
GB1363815A (en) * 1971-12-06 1974-08-21 Tektronix Inc Semiconductor device and method of producing same
US3747200A (en) * 1972-03-31 1973-07-24 Motorola Inc Integrated circuit fabrication method

Also Published As

Publication number Publication date
US3945347A (en) 1976-03-23
NL158026B (en) 1978-09-15
FR2203175A1 (en) 1974-05-10
FR2203175B1 (en) 1977-09-23
DE2351943A1 (en) 1974-05-02
DE2351943B2 (en) 1980-08-07
NL7314156A (en) 1974-04-18
JPS4960870A (en) 1974-06-13
CA989076A (en) 1976-05-11

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
746 Register noted 'licences of right' (sect. 46/1977)
PCNP Patent ceased through non-payment of renewal fee

Effective date: 19921016