JPS54158878A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS54158878A
JPS54158878A JP6795778A JP6795778A JPS54158878A JP S54158878 A JPS54158878 A JP S54158878A JP 6795778 A JP6795778 A JP 6795778A JP 6795778 A JP6795778 A JP 6795778A JP S54158878 A JPS54158878 A JP S54158878A
Authority
JP
Japan
Prior art keywords
film
source
diffusion
sio
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6795778A
Other languages
Japanese (ja)
Inventor
Nobuhiro Endo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6795778A priority Critical patent/JPS54158878A/en
Publication of JPS54158878A publication Critical patent/JPS54158878A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To obtain an IGFET without depending upon matching precision by fixing the relation between source and drain regions and a channel stopper region and that between source and drain regions and an insulating gate region by self-matching.
CONSTITUTION: On P-type Si substrate 1, SiO2 film 2 is bonded and removed over source, drain and gate formation regions and the window circumference of remaining film 2 is covered with Si3N4 film 3, which is used as a mask to form N-type source and drain regions 4 by diffusion. Through intruding diffusion, region 4 is made deeper and film 2 is partially removed by etching with film 3 used as a mask. Then, P-type channel stopper region 5 is formed here by diffusion and heat-treated to produce SiO2 film 6 only on regions 4 and 5. Next, the surface is sufficiently cleaned and heat-treated again to produce gate SiO2 2 film 7, and window is made to fit Al gate electrode 8.
COPYRIGHT: (C)1979,JPO&Japio
JP6795778A 1978-06-05 1978-06-05 Manufacture of semiconductor device Pending JPS54158878A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6795778A JPS54158878A (en) 1978-06-05 1978-06-05 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6795778A JPS54158878A (en) 1978-06-05 1978-06-05 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS54158878A true JPS54158878A (en) 1979-12-15

Family

ID=13359939

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6795778A Pending JPS54158878A (en) 1978-06-05 1978-06-05 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS54158878A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4973983A (en) * 1972-09-29 1974-07-17
JPS51151081A (en) * 1975-06-20 1976-12-25 Matsushita Electric Ind Co Ltd Mos type semiconductor apparatus and that manufacturing method
JPS52131483A (en) * 1976-04-28 1977-11-04 Hitachi Ltd Mis-type semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4973983A (en) * 1972-09-29 1974-07-17
JPS51151081A (en) * 1975-06-20 1976-12-25 Matsushita Electric Ind Co Ltd Mos type semiconductor apparatus and that manufacturing method
JPS52131483A (en) * 1976-04-28 1977-11-04 Hitachi Ltd Mis-type semiconductor device

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