KR100548536B1 - Semiconductor device formed SOI substrate and method for manufacturing the same - Google Patents

Abstract

The present invention discloses a semiconductor device formed on an SOI substrate that can easily dissipate heat generated by an ESD current, and a method of manufacturing the same. The disclosed device comprises: an SOI substrate comprised of a handling wafer, an buried insulation layer, and a silicon layer; An isolation layer formed on a predetermined portion of the silicon layer, defining an ESD region and a cell region, and having a thickness smaller than that of the silicon layer; And a MOSFET formed in each of the ESD region and the cell region, and a polysilicon spacer including impurities formed on sidewalls of the ESD region and sidewalls of the cell region, respectively, on a bottom surface of the device isolation layer defining the ESD region and the cell region. And a conductor filled between the polysilicon spacer and a conductive path connecting the silicon wafer and the handling wafer of the ESD region and the cell region.

Description

Semiconductor device formed SOI substrate and method for manufacturing the same

1 is a cross-sectional view of a semiconductor device formed on a conventional SOI substrate.

2A-2H are cross-sectional views of a semiconductor device formed on an SOI substrate in accordance with the present invention.

(Explanation of symbols for the main parts of the drawing)

11-handling wafer 12-investment insulation layer

13-silicon layer 14-silicon oxide film

15-Silicon Nitride 16a-Residual Spacer

17-PSG film 18-Linear oxide film

19-oxide film for gap filling 20-gate insulating film

21-gate electrode 22-source, drain region

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device formed on a silicon on insulator (SOI) substrate capable of increasing a heat dissipation area and a method of manufacturing the same.

Semiconductor integrated circuits, in particular CMOS-LSI, are constantly required to increase in speed and density.

So far, performance gains have been achieved primarily by scaling. Up to submicrons could be scaled to a constant power supply voltage, which significantly improved the operating speed. However, below the submicron, the power supply voltage is also lowered, so that the improvement in speed cannot be achieved by simple scaling alone.

Accordingly, in order to solve such a problem, development of a new technology continues, and one of them has been proposed a SOI structure in which a semiconductor layer for forming a semiconductor device is formed on an insulator layer.

1 is a view for explaining a semiconductor device formed on a conventional SOI substrate.

In the related art, as shown in FIG. 1, a buried insulating layer 2 and a silicon layer 3 are sequentially stacked on the handling wafer 1. A field oxide film 4 is formed in a predetermined portion of the silicon layer 3 to define an active region. A gate insulating film 5 and a gate electrode 6 are disposed in a predetermined portion of the active region, and highly-concentrated impurities are ion-implanted in the active regions on both sides of the gate electrode 6 to form source and drain regions 7a and 7b. . Thereafter, an interlayer insulating film is formed on the resultant, and then contact holes are formed to expose the source and drain regions 7a and 7b. Subsequently, source and drain electrodes 9a and 9b are formed in the contact hole.

Since the silicon layer is a thin film, the SOI structure MOSFET has an extremely small diffusion capacitance, which can be used as a low voltage device, and when the thickness of the silicon layer is 100 nm or less, the on-current can be increased. In addition, the active region may be completely insulated and separated by an isolation layer (not shown) and the buried insulating layer 2.

However, the semiconductor device of the SOI structure has various advantages as described above, but has a problem that the electrostatic discharge (ESD) characteristics are very weak.

More specifically, in the conventional SOI semiconductor device, in order to prevent static electricity from the outside, an ESD protection circuit made of an NMOS transistor or a CMOS transistor is formed.

At this time, due to the inflow of static electricity, an ESD current is generated in the silicon layer of the SOI substrate, and heat is generated in the silicon layer by the ESD current. In a bulk silicon substrate, such heat is easily released to silicon due to its excellent heat transfer characteristics, but in an SOI structure having a buried insulation layer of several microns in thickness, the heat transfer path is blocked by the investment insulation layer to easily release heat. It doesn't work. Furthermore, since the bottoms of the source and drain regions 7a and 7b contact the buried insulating layer 2, the introduced ESD current does not escape to the edge regions of the source and drain regions 7a and 7b, so that the temperature of the silicon layer Will be raised.

This adversely affects the operation of the device.

Accordingly, an object of the present invention is to solve the above-mentioned conventional problems, and to provide a semiconductor device formed on an SOI substrate that can easily dissipate heat generated by an ESD current.

Moreover, another object of this invention is to provide the manufacturing method of the said semiconductor device.

In order to achieve the above object of the present invention, according to one aspect of the present invention, an SOI substrate consisting of a handling wafer, a buried insulating layer and a silicon layer; An isolation layer formed on a predetermined portion of the silicon layer, defining an ESD region and a cell region, and having a thickness smaller than that of the silicon layer; And a MOSFET formed in each of the ESD region and the cell region, and a polysilicon spacer including impurities formed on sidewalls of the ESD region and sidewalls of the cell region, respectively, on a bottom surface of the device isolation layer defining the ESD region and the cell region. And a conductor filled between the polysilicon spacer and a conductive path connecting the silicon layer and the handling wafer in the ESD region and the cell region to form a semiconductor device.

At this time, the conductor is formed of a PSG film.

In addition, the present invention is a SOI substrate consisting of a handling wafer, a buried insulating layer and a silicon layer; A first trench formed in a predetermined portion of the silicon layer, dividing an ESD region and a cell region, the first trench having a bottom surface in contact with a surface of the handling wafer; A second trench that separates devices in the cell region and has a depth shallower than that of the silicon layer; A conductive spacer formed on the sidewall portion of the first trench and having a height shallower than that of the first trench; A conductor filled in the first trench between the conductive spacers; A gap-filling oxide layer filled in a space surrounded by the exposed sidewalls and the conductor surface of the first trench and inside the second trench; And a MOSFET formed in the ESD region and the cell region, respectively.

In this case, the conductive spacer is formed of a doped polysilicon film, and the conductor is formed of a PSG film.

According to another aspect of the present invention, there is provided a method comprising: providing an SOI substrate composed of a handling wafer, a buried insulating layer, and a silicon layer, wherein an ESD region and a cell region are predetermined; Depositing a silicon oxide film and a silicon nitride film on the silicon layer; Forming first and second trenches in the first device isolation region separating the ESD region and the cell region and the second device isolation region separating the elements in the cell region, respectively, wherein the first trench is formed by the first trench. Forming first and second trenches deeper than two trenches, such that a handling wafer is exposed on the bottom of the first trench; Forming a spacer having a height shallower than a height of the first trench only on both sidewalls of the first trench; Filling a conductor between the spacers; Filling an oxide upper region of the first trench and an oxide layer in the second trench; And forming a MOSFET in the ESD region and the cell region, and when the conductor is filled, conductivity is provided to the spacer.

The forming of the first and second trenches may include: patterning a silicon nitride film of the first device isolation region; Removing the silicon oxide film and the silicon layer by a predetermined depth using the silicon nitride film as a mask; Patterning a silicon nitride film of the second device isolation region; Etching the silicon nitride film as a mask until the buried insulating layer of the first isolation region is exposed to form first and second trenches; And etching the exposed investment insulating layer in the first trench.

The forming of the spacer only on the inner side of the first trench may include depositing a spacer film on the resultant layer; Anisotropically etching the spacer film to form spacers on inner walls of the first and second trenches; Isotropically etching the spacer such that the spacer of the inner side of the second trench is removed. In this case, the spacer film is a polysilicon film.

In addition, filling the conductor between the spacers in the first trench may include forming a PSG film in the first trench; Heat-treating the PSG film to fill the PSG film in the first trench; And etching back the PSG film until the spacer in the first trench is exposed. During the heat treatment, impurities in the PSG film are doped into the spacer.

Finally, linearly filling the inner wall of the first trench and the upper region of the conductor and the inner wall of the second trench between filling the conductor between the spacers and filling the oxide film in the first and second trenches. The method further includes coating the oxide film.

According to the present invention, a polysilicon spacer for a pass for connecting the handling wafer and the silicon layer is formed on the bottom surface of the device isolation film defining the ESD region. As a result, the silicon layer is partially connected to the handling wafer, thereby substantially increasing the area of the silicon layer. Therefore, upon ingress of ESD, current and heat are effectively distributed towards the handling wafer so that current and heat are not concentrated in the silicon layer.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2G are manufacturing process diagrams of a semiconductor device formed on an SOI substrate according to the present invention.

In this embodiment, in order to prevent heat from concentrating on the silicon layer of the SOI substrate due to generation of ESD current, the area of the silicon layer where the device is formed is partially increased.

That is, as shown in FIG. 2A, an SOI substrate made of a handling wafer 11, a buried insulating layer 12, and a silicon layer 13 is provided. At this time, the SOI substrate is a bonding method formed by attaching a semiconductor wafer with a buried insulating layer and a handling wafer, as known, or a SIMOX (seperation) to inject oxygen ions deeply into a silicon wafer to form a buried insulating layer. by implanted oxygen). Subsequently, a buffer silicon oxide film 14 and a silicon nitride film 15 are sequentially formed on the silicon layer 13.

Then, as shown in FIG. 2B, a resist pattern (not shown) is formed so that the device isolation region separating the ESD circuit region E and the cell region C is exposed, and the form of the resist pattern The silicon nitride film 15 is patterned. Subsequently, after patterning the silicon oxide film 14 using the patterned silicon nitride film 15 as a mask, the silicon layer 13 is recessed by a predetermined depth to define the first device isolation region FO1. .

Next, as shown in FIG. 2C, the silicon nitride film 15 and the silicon oxide film of the second device isolation region FO2 are defined to define the device isolation region (hereinafter, the second device isolation region FO2) of the cell region. Remove (14).

Then, the silicon layers 13 of the exposed first and second device isolation regions FO1 and FO2 are etched to form first and second trenches t1 and t2 as shown in FIG. 2D. In this case, the etching endpoint is until the buried insulating layer 12 of the first device isolation region FO1 is exposed. Then, the buried insulating layer 12 is exposed on the bottom of the first trench t1, and the silicon layer 13 is exposed on the bottom of the second trench t2. At this time, the first and second trenches t1 and t2 have different depths because the silicon layer 13 is etched once in the first device isolation region FO1.

Thereafter, as shown in FIG. 2E, the buried insulating layer 12 of the exposed first device isolation region FO1 is removed by a known method. Then, a polysilicon film is deposited on the resultant, and the polysilicon film is anisotropically etched to form polysilicon spacers 16 on the inner walls of the first and second trenches t1 and t2.

Then, with reference to FIG. 2F, isotropic etching is performed such that the polysilicon spacer 16 of the second trench t2 is removed. At this time, since the polysilicon spacer in the first trench t1 is formed thicker than the polysilicon spacer in the second trench t2, even if all of the polysilicon spacers in the second trench t2 are removed, the first trench t1 is removed. Some polysilicon spacers 16 remain in the interior. At this time, the polysilicon spacer 16 remaining in the first trench t1 is referred to as the residual spacer 16a. Then, the PSG film 17 is deposited on the resultant, and then annealing is performed at a temperature of 600 ° C. or more to embed the PSG film 17 in the first trench t1. At this time, when heat is applied, the PSG film 17 has excellent interlayer planarization characteristics and includes phosphorus (P) impurities, thereby doping the polysilicon spacers 16a under the thermal process. Accordingly, the polysilicon spacer 16a becomes conductive.

Then, as shown in Fig. 2G, the PSG film 17 is etched back until the surface of the residual spacer 16a is exposed to fill the PSG film 17a between the remaining spacers 16a. At this time, due to the step between the trenches t1 and t2, the PSG film 17 in the second trench t2 is removed during the etch back process. Subsequently, linear oxide films 18 are formed on the inner surfaces of the first and second trenches t1 and t2. At this time, in the first trench t1, the linear oxide film 18 is formed on the surface of the PSG film 17a which is etched back.

Referring to FIG. 2H, an oxide film having excellent gap filling characteristics is embedded in the first and second trenches t1 and t2 surrounded by the linear oxide film 18 to form a element separator 20. Next, a gate insulating film 20 and a gate electrode 21 are formed in a predetermined portion of the exposed silicon layer 13. Subsequently, impurities are implanted into both sides of the gate electrode 21 to form the source and drain regions 22, thereby forming MOSFETs in the ESD region and the cell region.

In this manner, the buried insulating layer 12 is removed from the bottom of the device isolation film 19 defining the ESD region E, and the silicon layer 13 and the handling wafer (eg, through the doped polysilicon spacer 16a) are removed. Since 11 is connected, the area of the silicon layer 13 substantially extends to the handling wafer 11. As a result, the area of the silicon layer 13 is expanded, thereby dispersing the concentration of the ESD current and the heat generated by the source in the source and drain regions during the ESD generation.

As described in detail above, according to the present invention, a polysilicon spacer for a pass for connecting the handling wafer and the silicon layer is formed on the bottom surface of the device isolation layer that defines the ESD region. As a result, the silicon layer is partially connected to the handling wafer, thereby substantially increasing the area of the silicon layer. Therefore, upon ingress of ESD, current and heat are effectively distributed towards the handling wafer so that current and heat are not concentrated in the silicon layer.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (14)

An SOI substrate composed of a handling wafer, an embedding insulating layer and a silicon layer; An isolation layer formed on a predetermined portion of the silicon layer, defining an ESD region and a cell region, and having a thickness smaller than that of the silicon layer; A MOSFET formed in each of the ESD region and the cell region, A bottom surface of the device isolation layer defining the ESD region and the cell region includes a polysilicon spacer including impurities formed on sidewalls of the ESD region and a sidewall of the cell region, and a conductor filled between the polysilicon spacer. A semiconductor device formed on an SOI substrate, wherein a conductive path is formed to connect the silicon layer and the handling wafer in the region and the cell region. delete The semiconductor device according to claim 1, wherein the conductor is a PSG film. The semiconductor device according to claim 1, wherein said device isolation film has a trench structure. The semiconductor device according to claim 4, wherein the device isolation film is formed on an SOI substrate including a linear oxide film covering an outer circumferential surface of the device isolation film and a gap filling oxide film filled in a space surrounded by the linear oxide film. An SOI substrate composed of a handling wafer, an embedding insulating layer and a silicon layer; A first trench formed in a predetermined portion of the silicon layer, dividing an ESD region and a cell region, the first trench having a bottom surface in contact with a surface of the handling wafer; A second trench that separates devices in the cell region and has a depth shallower than that of the silicon layer; A conductive spacer formed on the sidewall portion of the first trench and having a height shallower than that of the first trench; A conductor filled in the first trench between the conductive spacers; A gap-filling oxide layer filled in a space surrounded by the exposed sidewalls and the conductor surface of the first trench and inside the second trench; And And a MOSFET formed in the ESD region and the cell region, respectively. 7. The semiconductor device of claim 6, wherein the conductive spacer is formed of a doped polysilicon film. 8. The semiconductor device of claim 6 or 7, wherein the conductor is a PSG film. Providing a SOI substrate comprising a handling wafer, a buried insulating layer, and a silicon layer, wherein the ESD region and the cell region are predetermined; Depositing a silicon oxide film and a silicon nitride film on the silicon layer; Forming first and second trenches in the first device isolation region separating the ESD region and the cell region and the second device isolation region separating the elements in the cell region, respectively, wherein the first trench is formed by the first trench. Forming first and second trenches deeper than two trenches, such that a handling wafer is exposed on the bottom of the first trench; Forming a spacer having a height shallower than a height of the first trench only on both sidewalls of the first trench; Filling a conductor between the spacers; Filling an oxide upper region of the first trench and an oxide layer in the second trench; And Forming a MOSFET in the ESD region and the cell region, A method of manufacturing a semiconductor device formed on an SOI substrate, wherein conductivity is imparted to the spacer when the conductor is filled. 10. The method of claim 9, wherein the forming of the first and second trenches comprises: patterning a silicon nitride film of the first device isolation region; Removing the silicon oxide film and the silicon layer by a predetermined depth using the silicon nitride film as a mask; Patterning a silicon nitride film of the second device isolation region; Etching the silicon nitride film as a mask until the buried insulating layer of the first isolation region is exposed to form first and second trenches; And etching the exposed buried insulator layer in the first trenches. The method of claim 10, wherein forming the spacer only on the inner side of the first trench comprises: depositing a spacer film on the resultant layer; Anisotropically etching the spacer film to form spacers on inner walls of the first and second trenches; Isotropically etching the spacers such that the spacers in the second trench inner side walls are removed. 12. The method of manufacturing a semiconductor device according to claim 11, wherein the spacer film is a polysilicon film. 10. The method of claim 9, wherein filling a conductor between spacers in the first trench comprises: forming a PSG film in the first trench; Heat-treating the PSG film to fill the PSG film in the first trench; And etching back the PSG film until the spacer in the first trench is exposed, wherein, during the heat treatment, impurities in the PSG film are doped into the spacer. 10. The method of claim 9, wherein an inner wall of the first trench and an upper region of the conductor and the second trench are filled between filling a conductor between the spacers and filling an oxide film in the first and second trenches. A method of manufacturing a semiconductor device formed on an SOI substrate, further comprising coating a linear oxide film on the inner wall.

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