KR19990052558A - Power device manufacturing method and structure - Google Patents
Power device manufacturing method and structure Download PDFInfo
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- KR19990052558A KR19990052558A KR1019970072051A KR19970072051A KR19990052558A KR 19990052558 A KR19990052558 A KR 19990052558A KR 1019970072051 A KR1019970072051 A KR 1019970072051A KR 19970072051 A KR19970072051 A KR 19970072051A KR 19990052558 A KR19990052558 A KR 19990052558A
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- silicon substrate
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- insulating film
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- 238000004519 manufacturing process Methods 0.000 title abstract description 9
- 239000010408 film Substances 0.000 claims abstract description 37
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 29
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 29
- 239000010703 silicon Substances 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 239000010409 thin film Substances 0.000 claims abstract description 15
- 229910003460 diamond Inorganic materials 0.000 claims abstract description 14
- 239000010432 diamond Substances 0.000 claims abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 5
- 239000011229 interlayer Substances 0.000 abstract description 4
- 239000010410 layer Substances 0.000 abstract description 4
- 239000004065 semiconductor Substances 0.000 description 5
- 238000002955 isolation Methods 0.000 description 4
- 238000010292 electrical insulation Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3732—Diamonds
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Thin Film Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Element Separation (AREA)
Abstract
본 발명은 전력 소자 제조방법 및 그 구조에 관한 것으로, 특히 집적회로(IC; integrated circuits)에서 전력 소자가 동작할 때 발생되는 열을 적절하게 방열시킬 수 있는 전력 소자 제조방법 및 그 구조에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power device manufacturing method and a structure thereof, and more particularly to a power device manufacturing method and a structure that can properly dissipate heat generated when a power device operates in integrated circuits (IC). .
본 발명은 에스오아이 실리콘 기판에서 기판 실리콘과 활성 실리콘 층사이에 있는 층간 산화막에 구멍을 뚫어 산화막 보다 열전도도가 우수한 다이아몬드 박막을 끼워 넣음으로써 전력 소자에서 발생된 열을 효과적으로 빼 낼 수 있게 하여 소자의 동작 특성과 신뢰성을 더욱 개선시킬 수 있다.In the present invention, a diamond thin film having a higher thermal conductivity than an oxide film is inserted in an SII silicon substrate by inserting a hole in an interlayer oxide film between a substrate silicon and an active silicon layer, thereby effectively extracting heat generated from a power device. The operation characteristics and reliability can be further improved.
Description
본 발명은 전력 소자 제조방법 및 그 구조에 관한 것으로, 특히 집적회로(IC; integrated circuits)에서 전력 소자가 동작할 때 발생되는 열을 적절하게 방열시킬 수 있는 전력 소자 제조방법 및 그 구조에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power device manufacturing method and a structure thereof, and more particularly to a power device manufacturing method and a structure that can properly dissipate heat generated when a power device operates in integrated circuits (IC). .
일반적으로, SOI(Silicon-On Insulator) 절연막을 이용한 종래의 전력 집적회로는 트랜치 기술을 이용하여 소자를 격리시킨다. 이때 실리콘 기판을 식각하여 트랜치를 형성한 다음 절연막(산화막)을 성장(또는 증착)하고 그후에 다결정실리콘 등을 저압화학증착법 등으로 트랜치를 메우게 된다. 이 구조에서는 실리콘 보다 열전도가 아주 나쁜 산화막이 전력소자를 완전히 격리 시킨다. 그 결과 종래의 전력 집적회로에서는 전력소자가 동작할 때 발생되는 열이 적절하게 방열되지 못하는 단점이 있다. 따라서, 전력소자가 동작할 때 발생되는 열을 쉽게 방출시킬 수 있는 전력 집적회로 구조가 필요하다.In general, a conventional power integrated circuit using a silicon-on insulator (SOI) insulating film uses a trench technology to isolate the device. At this time, the silicon substrate is etched to form a trench, followed by growing (or depositing) an insulating film (oxide film), and then filling the trench by low pressure chemical vapor deposition or the like. In this structure, the oxide film, which has much lower thermal conductivity than silicon, completely isolates the power device. As a result, in the conventional power integrated circuit, heat generated when the power device is operated may not be properly radiated. Therefore, there is a need for a power integrated circuit structure capable of easily dissipating heat generated when the power device operates.
종래 전력소자의 구조를 도 1을 참조하여 설명하면 다음과 같다.The structure of the conventional power device will be described with reference to FIG. 1.
여기서 전력소자는 대표적으로 LDMOS를 나타내었으나 VDMOS, Bipolar 전력소자가 모두 포함될 수 있다. 에스오아이 실리콘 기판을 이용하여 전력 집적회로를 제작할 때 활성 실리콘(3)을 식각하여 트랜치를 만든 후에 트랜치 격리 절연막(4)를 형성하고 나머지 공간을 저압화학증착법 등으로 다결정실리콘(5)으로 채운다. 따라서, 전력소자는 SOI절연막(2)과 트랜치 격리 절연막(4)으로 둘러 쌓여져 전기적으로 완전히 격리된다.Here, the power device typically represents an LDMOS, but may include both VDMOS and Bipolar power devices. When fabricating a power integrated circuit using an SIO silicon substrate, the trench is formed by etching the active silicon 3, and then the trench isolation insulating film 4 is formed, and the remaining space is filled with polycrystalline silicon 5 by low pressure chemical vapor deposition. Therefore, the power device is surrounded by the SOI insulating film 2 and the trench isolation insulating film 4 to be completely electrically isolated.
반도체 전력 집적회로 소자에서 종래에는 소자의 전기적 특성을 최적화시키는 연구에 치중하여 전력소자가 동작할 때 발생된 열을 효과적으로 방열하는 구조에 대하여는 많은 연구가 이루어지지 못하였다.In the semiconductor power integrated circuit device, a lot of research has not been conducted on the structure of effectively dissipating heat generated when the power device operates in the prior art, focusing on the optimization of the electrical characteristics of the device.
따라서, 본 발명은 반도체 전력 집적회로 소자가 동작시 발생되는 열을 효과적으로 방출시킬 수 있는 구조와 공정을 제안함으로써 더욱더 안정된 상태에서 소자가 동작하게 하여 전력 집적회로의 신뢰성을 향상시키는 전력 소자 제조방법 및 그 구조를 제공하는데 그 목적이 있다.Accordingly, the present invention proposes a structure and a process for effectively dissipating heat generated during operation of a semiconductor power integrated circuit device, thereby making the device operate in a more stable state, thereby improving the reliability of the power integrated circuit, and The purpose is to provide that structure.
상기한 목적을 달성하기 위한 본 발명에 따른 전력 소자 제조방법은 제 1 실리콘 기판상에 절연막을 형성한 후 식각 공정을 이용하여 상기 절연막에 실린더 형태의 홀을 형성하는 단계와, 홀이 형성된 전체 상부면에 다이아몬드 박막 및 다결정실리콘막을 순차적으로 형성하는 단계와, 상기 다결정실리콘막의 표면을 평탄화 시킨 후 전체 상부면에 제 2 실리콘 기판을 붙이는 단계와, 상기 제 1 실리콘 기판 하부면을 식각한 후 전력 소자를 이루기 위한 여러 요소를 형성하는 단계를 포함하는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a power device manufacturing method including: forming an insulating film on a first silicon substrate, and then forming a cylindrical hole in the insulating film using an etching process, and forming an entire upper portion of the hole. Sequentially forming a diamond thin film and a polysilicon film on the surface, planarizing the surface of the polysilicon film, attaching a second silicon substrate to the entire upper surface, and etching the lower surface of the first silicon substrate, Characterized in that it comprises the steps of forming a number of elements to achieve.
본 발명에 따른 전력 소자 구조는 제 1 실리콘 기판상에 형성된 다결정 실리콘막과, 상기 다결정실리콘막상에 형성된 다이아몬드 박막층과, 상기 다이아몬드 박막층 상에 형성되며 실린더 형태의 홀이 형성된 절연막과, 상기 절연막 상에 형성된 제 2 실리콘 기판과, 상기 제 2 실리콘 기판상에 형성되며 전력 소자를 이루기 위한 여러 요소를 포함하여 구성된 것을 특징으로 한다.The power device structure according to the present invention includes a polycrystalline silicon film formed on a first silicon substrate, a diamond thin film layer formed on the polycrystalline silicon film, an insulating film formed on the diamond thin film layer and having a cylindrical hole formed thereon, and on the insulating film. And a second element formed on the second silicon substrate, and a plurality of elements formed on the second silicon substrate to form a power device.
본 발명은 반도체 전력 집적회로에서 소자가 동작할 때 많이 열이 발생한다. 발생된 열이 외부로 방열이 쉽게 일어나야 하며, 특히 SOI 기판을 이용하고 트랜치 소자격리 기술을 이용하면 전력소자가 전기 절연성을 탁월하지만 열전도 특성이 나쁜 산화막으로 완전히 격리된다. 그 결과 소자가 동작하면서 발생된 열은 외부로 방열되는데 어려움이 있어 소자의 동작 특성이 나빠지며, 전력 소자의 신뢰성에도 문제점이 발생하게 된다. 이것을 극복하기 위하여 열전도 특성이 우수한 다이아몬드 박막과 같은 열전도 특성이 우수한 절연막을 층간 절연막에 구멍을 뚫은 후에 끼워 넣어 전력소자에서 발생된 열을 다이아몬드 기둥을 통하여 기판으로 빠져 나갈 수 있도록 한다.The present invention generates a lot of heat when the device operates in a semiconductor power integrated circuit. Heat generated should be easily dissipated to the outside. In particular, using SOI substrates and trench isolation technology, power devices are completely isolated by oxide films with excellent electrical insulation but poor thermal conductivity. As a result, the heat generated during operation of the device is difficult to dissipate to the outside, resulting in deterioration of operating characteristics of the device and problems in reliability of power devices. In order to overcome this problem, an insulating film having excellent thermal conductivity such as a diamond thin film having excellent thermal conductivity is punched through the interlayer insulating film, and then inserted, so that the heat generated from the power device can escape to the substrate through the diamond pillar.
도 1은 종래의 전력소자의 구조1 is a structure of a conventional power device
도 2는 새로 제안된 전력 소자의 제조 공정 단면도Figure 2 is a cross-sectional view of the manufacturing process of the newly proposed power device
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
1 및 11: 제 1 실리콘 기판 2 및 12 : SOI 절연막1 and 11: first silicon substrate 2 and 12: SOI insulating film
3 및 15: 제 2 실리콘 기판 13 : 다이아몬드 박막3 and 15: second silicon substrate 13: diamond thin film
14 : 다결정실리콘막 4 및 16 :트랜치 격리 절연막14 polycrystalline silicon film 4 and 16: trench isolation insulating film
5 및 17 : 다결정실리콘 6 및 18 : 필드산화막5 and 17 polysilicon 6 and 18 field oxide film
7 및 19 : 층간절연막7 and 19: interlayer insulating film
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2h는 새로 제안한 전력소자의 구조와 제조 공정 단면도이다. 도 2a는 제 1 실리콘 기판(11)상에 SOI절연막(12)을 형성하는 공정을 도시한다. 이때 제 1 실리콘 기판은 활성 실리콘으로 형성한다.2A to 2H are cross-sectional views of a structure and a manufacturing process of a newly proposed power device. FIG. 2A shows a process of forming the SOI insulating film 12 on the first silicon substrate 11. At this time, the first silicon substrate is formed of active silicon.
도 2b는 일반적인 사진전사 방법과 습식 또는 건식 식각 공정을 이용하여 상기 SOI절연막(12)을 실린더 형태의 홀을 형성한 상태를 도시한다.FIG. 2B illustrates a state in which the SOI insulating layer 12 is formed with a cylindrical hole by using a general photolithography method and a wet or dry etching process.
도 2c는 전체 상부면에 다이아몬드 박막(13)을 형성한 상태의 도면으로, 다이아몬드 박막(13)은 산화막 뿐만아니라 실리콘 보다 열전도도가 10 배 이상인 5.45 eV의 넓은 에너지 갭을 가진 반도체 물질로서 비저항이 1016cm 이상으로 전기적으로 절연성이 우수하다.FIG. 2C is a view showing the diamond thin film 13 formed on the entire upper surface. The diamond thin film 13 is not only an oxide film but also a semiconductor material having a wide energy gap of 5.45 eV having a thermal conductivity of 10 times or more than that of silicon. 10 16 cm or more, excellent electrical insulation.
도 2d는 실리콘 기판을 두장을 붙일 때 다이아몬드 박막(13)은 경도가 크기 때문에 박막의 표면을 가공하기 어려우므로 전체 상부면에 다결정실리콘 박막(13)을 증착한 상태를 도시한다.2D shows a state in which the diamond thin film 13 has a high hardness when attaching two silicon substrates, so that it is difficult to process the surface of the thin film so that the polysilicon thin film 13 is deposited on the entire upper surface.
도 2e는 다른 실리콘 기판을 붙이기 위하여 CMP(chemical mechanical polishing)를 이용하여 다결정실리콘(13)의 표면을 평평하게 가공한 상태를 도시한다.FIG. 2E shows a state in which the surface of the polysilicon 13 is flattened using chemical mechanical polishing (CMP) to attach another silicon substrate.
도 2f는 전체 상부면에 다른 새로운 제 2 실리콘 기판(15)을 붙여 뒤집어 놓은 상태의 도면이다.FIG. 2F is a view in which another new second silicon substrate 15 is placed upside down on the entire upper surface.
도 2g는 전력소자를 제작하는 데 필요한 두께까지 제 1 실리콘 기판(11)을 식각하여 가공한 상태를 도시한다.FIG. 2G illustrates a state in which the first silicon substrate 11 is etched and processed to a thickness required for manufacturing a power device.
도 2h는 전체 상부면에 대표적으로 트랜치 기술과 LDMOS 전력소자를 이용하여 제작한 전력소자 단면을 도시한다.FIG. 2H shows a cross section of a power device fabricated using trench technology and LDMOS power devices representatively over the entire top surface.
본 발명은 SOI 절연막을 이용한 종래의 반도체 전력 집적회로 구조에서 층간 절연막에 구멍을 뚫은 후에 열전도 특성이 우수한 다이아몬드 박막을 끼워넣어 기존의 방열 문제를 해결함으로써 전력 소자의 동작 특성을 개선시키고 신뢰성을 향상시킬 수 있을 것으로 기대된다.The present invention solves the heat dissipation problem by inserting a diamond thin film having excellent thermal conductivity after punching the interlayer insulating film in the conventional semiconductor power integrated circuit structure using the SOI insulating film to improve the operating characteristics of the power device and improve the reliability It is expected to be able.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970072051A KR100258177B1 (en) | 1997-12-22 | 1997-12-22 | A power device and method of manufacturing the same |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019970072051A KR100258177B1 (en) | 1997-12-22 | 1997-12-22 | A power device and method of manufacturing the same |
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| KR100258177B1 KR100258177B1 (en) | 2000-06-01 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100505400B1 (en) * | 1999-06-21 | 2005-08-04 | 주식회사 하이닉스반도체 | Semiconductor device formed SOI substrate and method for manufacturing the same |
| KR100548536B1 (en) * | 1999-06-21 | 2006-02-02 | 주식회사 하이닉스반도체 | Semiconductor device formed SOI substrate and method for manufacturing the same |
-
1997
- 1997-12-22 KR KR1019970072051A patent/KR100258177B1/en not_active IP Right Cessation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100505400B1 (en) * | 1999-06-21 | 2005-08-04 | 주식회사 하이닉스반도체 | Semiconductor device formed SOI substrate and method for manufacturing the same |
| KR100548536B1 (en) * | 1999-06-21 | 2006-02-02 | 주식회사 하이닉스반도체 | Semiconductor device formed SOI substrate and method for manufacturing the same |
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| KR100258177B1 (en) | 2000-06-01 |
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