JP3400528B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having various kinds of wells on a substrate and a method for manufacturing the semiconductor device.

[0002]

2. Description of the Related Art A plurality of first conductive layers are formed on a semiconductor substrate of a first conductivity type.
A well structure having conductive type wells in which the first conductive type wells are electrically isolated from each other is called a triple well structure. Here, in the semiconductor device having this triple well structure, a conventionally used isolation method between elements and wells will be described below.

FIG. 27 is a partial cross-sectional view showing the structure of a conventional semiconductor device. In FIG. 27, reference numeral 1 denotes a P-type semiconductor substrate, which extends to the back surface of the substrate 1 below. Two
Is a shield layer made of an N-type semiconductor formed on the semiconductor substrate 1, 3 is a P-type isolated well formed on the shield layer 2, and 4 is an N-type well formed adjacent to the P-type isolated well 3. Thus, the shield layer 2 is in a conductive state. Reference numeral 5 denotes a P-type substrate well formed adjacent to the N-type well 4, which is in conduction with the P-type semiconductor substrate 1.

Reference numeral 6 denotes a P-type high-concentration diffusion region formed in the surface layer of the P-type isolated well 3, to which a wide area wiring 17, which will be described later, for fixing the P-type isolated well 3 to the first potential is connected. . Reference numeral 7 denotes an N-type high-concentration diffusion region formed in the surface layer of the N-type well 4, to which a wide area wiring 17, which will be described later, for fixing the N-type well 4 to the second potential is connected. Reference numeral 8 is a second P-type high-concentration diffusion region formed in the surface layer of the P-type substrate well 5, to which a wide area wiring 17 described later for fixing the P-type substrate well 5 to the third potential is connected. . Reference numeral 9 denotes a source / drain diffusion region which is to be a source / drain formed in the surface layer of the semiconductor substrate 1, and 10 has an insulator such as SiO ₂ embedded in a trench having a width of about 0.2 μm and a depth of about 0.4 μm. In the trench type isolation region, the high concentration diffusion region 6,
It is formed between 7, 8 and the source / drain diffusion region 9.

Reference numeral 11 denotes a gate insulating film having a thickness of about 10 nm formed on the source / drain diffusion region 9, 12 denotes a gate electrode formed on the gate insulating film 11, and 13
Internal wiring, the source / drain diffusion region through the internal wiring hole 15b of the SiO ₂ insulating film 14 16 is electrically connected via internal wiring hole 15a of the source / drain diffusion region 9 and the SiO ₂ insulating film 14 is 9 is a memory capacitor electrically connected to the lower electrode 16a and the dielectric 16
b and the upper electrode 16c. Reference numeral 17 is the source / drain diffusion region 9 or the high concentration diffusion regions 6, 7, 8
Is a wide area wiring electrically connected through the wide area wiring connection hole 18 of the SiO ₂ insulating film 14.

In the semiconductor device configured as described above, a large number of elements (not shown) are formed in the same well. Between these elements, that is, between the adjacent source / drain diffusion regions 9, By forming a trench type isolation region 10 having a width of 0.2 μm and a depth of 0.4 μm in which an insulator is embedded in the trench, the distance between the adjacent source / drain diffusion regions 9 in the semiconductor substrate 1 is increased. You can get the same function as taking a big one. That is, the isolation breakdown voltage between the source / drain diffusion regions 9 is improved.

Further, by forming the trench type isolation region 10 between the high concentration diffusion regions 6, 7, 8 for fixing the well potential and the source / drain diffusion region 9,
A function similar to that of increasing the distance between the high concentration diffusion regions 6, 7, 8 and the source / drain diffusion regions 9 can be obtained.
That is, the junction breakdown voltage, which is the maximum applied voltage for maintaining the insulation characteristic of the PN junction in the opposite direction, increases.

Further, in the semiconductor device configured as described above, in order to optimize the characteristics of the N-type semiconductor element formed in the P-type isolated well 3 and the P-type substrate well 5,
Since the potential of the P-type isolated well 3 and the potential of the P-type substrate well 5 are set to different values, it is necessary to electrically separate the P-type isolated well 3 and the P-type substrate well 5. Therefore,
By forming the N-type semiconductor shield layer 2 on the bottom surface of the P-type isolated well 3, the P-type isolated well 3 is electrically separated from the P-type semiconductor substrate 1 which is in conduction with the P-type substrate well 5. Further, an N-type well 4 electrically connected to the N-type semiconductor shield layer 2 is formed on the side surface of the P-type isolated well 3 to electrically separate the P-type isolated well 3 and the P-type substrate well 5. I am letting you.

[0009]

In the conventional semiconductor device as described above, in order to electrically isolate wells of the same conductivity type, it is necessary to surround the periphery with wells of different conductivity types. .

However, in the current industrial technology, the boundary position between the P-type well and the N-type well is set to 0.1 μm.
Is difficult to control, and in this conventional example, the width of the N-type well 4 surrounding the P-type isolated well 3 cannot be reduced to 1 μm or less. Therefore, this has been a major obstacle in promoting high integration of semiconductor devices.

The present invention has been made to solve the above-mentioned problems, and an object thereof is to obtain a structure of a semiconductor device in which high integration is not hindered by separation of wells, and a method of manufacturing the semiconductor device. The purpose is to provide.

[0012]

In a semiconductor device according to the present invention, a semiconductor device formed on the main surface of a semiconductor substrate of the first conductivity type.
The first conductive layer separated by the trench type well isolation region.
Including an electric well and the trench well isolation region
The first well formed on the entire bottom surface of the separated well.
And a buried region of two conductivity type.
The other side of the trench contacts the semiconductor substrate and is connected to the trench type wafer.
The isolation region is formed deeper than the well and
It is characterized in that it is terminated inside the area .

In the method of manufacturing a semiconductor device according to the second invention , the first insulating film is formed on the first conductivity type semiconductor substrate.
And a second insulating film are sequentially formed to form a laminated film,
The laminated film is patterned and the semiconductor is used as a mask.
Anisotropically etch the substrate to form the first trench
And the above-mentioned half so as to cover the inner wall of the first trench.
The first insulating film made of the same material as the first insulating film is formed on the entire surface of the conductor substrate.
Protective film and second protective film made of the same material as the second insulating film
The film is sequentially formed, and the insulating film is formed on the entire surface of the film.
After filling the first trench, etch back the entire surface
Form a plug made of the insulating film in the first trench.
And a resist mask is used to perform the first tray.
The plug in the desired trench selected from the
After removing, the second and first protections in the trench
The film is removed, and the semiconductor substrate below the trench is anisotropically
Etching to form deep trenches, and
Using the resist mask covering the deep trench, the first
Remove the above plug remaining in the trench of
A step of removing the second insulating film and the second protective film,
Then, the first insulating film is formed on the entire surface of the semiconductor substrate.
Form an insulating film of material to form the deep trench and other
Embedded in the first trench of the
Process for forming isolated region and trench type element isolation region
And selectively ion-implanting into a predetermined region of the semiconductor substrate.
The buried region of the second conductivity type inside the buried region.
Predetermined to terminate the trench type well isolation region at
Of the above semiconductor by ion implantation
Separated by the trench type well isolation region on the substrate
And a step of forming a first conductivity type well .

In the method of manufacturing a semiconductor device according to the third invention, a first insulating film is formed on a semiconductor substrate of the first conductivity type.
And a second insulating film are sequentially formed to form a laminated film,
The laminated film is patterned and the semiconductor is used as a mask.
Anisotropically etch the substrate to form the first trench
And the above-mentioned half so as to cover the inner wall of the first trench.
The first insulating film made of the same material as the first insulating film is formed on the entire surface of the conductor substrate.
Protective film and second protective film made of the same material as the second insulating film
The film is sequentially formed, and the insulating film is formed on the entire surface of the film.
After filling the first trench, etch back the entire surface
Form a plug made of the insulating film in the first trench.
And a resist mask is used to perform the first tray.
The plug in the desired trench selected from the
After removing, the second and first protections in the trench
The film is removed, and the semiconductor substrate below the trench is anisotropically
Etching to form deep trenches, and
After forming an insulating film on the entire surface of the semiconductor substrate, anisotropically
Of the insulating film to the side surface in the deep trench.
And leave the conductor film embedded in the deep trench.
Formed in the deep trench, and the surrounding film is covered with the insulating film in the deep trench.
The trench type well isolation region made of the above-mentioned conductor film
Forming step and then remaining in the first trench
The plug is removed, and the second insulating film and
A step of removing the second protective film, and then the semiconductor substrate
An insulating film made of the same material as the first insulating film is formed on the entire surface of the plate.
Fills the first trench and separates the trench type device.
The process of forming a region and selecting a predetermined region of the semiconductor substrate
Alternatively, by implanting ions, a second conductivity type buried region is formed.
Inside the buried region, the trench type well isolation region is
It is formed to a predetermined depth so as to terminate, and the conductor film is
For the process of electrically connecting with the buried region and for ion implantation
From the semiconductor substrate to the trench well isolation region
Therefore, the method is provided with a step of forming a first conductivity type well that is separated .

[0015]

In the semiconductor device of the first aspect of the present invention, the second conductivity type buried region is formed over the entire bottom surface of at least one of the first conductivity type wells in the two first conductivity type wells. Of the conductive type wells and the buried region of the second conductive type are electrically separated from each other by a PN junction, and between the adjacent wells of the first conductive type, the wells of the first conductive type penetrate through the wells of the second conductive type. The trench-type well isolation region reaching the type-embedded region is electrically isolated, and therefore the adjacent first conductivity type wells are electrically isolated from each other.

In the method of manufacturing a semiconductor device according to the second aspect of the invention, a trench type element isolation region having an insulator embedded in a shallow trench and a trench type well isolation region having an insulator embedded in a deep trench. Can be formed.

Further, in the semiconductor device of the third invention, the trench type element isolation region in which the insulator is embedded in the shallow trench and the conductor which is surrounded by the insulator are embedded in the deep trench. Well isolation regions can be formed.

[0018]

EXAMPLES Example 1. Hereinafter, the present invention will be described by taking a semiconductor device having a triple well structure, which is an embodiment, as an example. In the embodiment, the first conductivity type is P type and the second conductivity type is N type.
Described as a type. FIG. 1 is a partial sectional view showing a semiconductor device according to an embodiment of the present invention. In this figure, reference numeral 1 is a P-type semiconductor substrate, which extends to the back surface of the substrate 1 below in the figure. Reference numeral 2 denotes a shield layer which is an N-type semiconductor formed on the semiconductor substrate 1 and has a thickness of approximately 0.2 μm, and 3 is P, which is formed on the shield layer 2 and has a thickness of approximately 1.0 μm.
D type isolated wells 5 are P type substrate wells formed adjacent to the P type isolated well 3 with an isolation region therebetween, and are in a conductive state with the P type semiconductor substrate 1.

Reference numeral 6 denotes a P-type high-concentration diffusion region formed in the surface layer of the P-type isolated well 3, to which a wide area wiring 17, which will be described later, for fixing the P-type isolated well 3 to the first potential is connected. . Reference numeral 8 is a second P-type high-concentration diffusion region formed in the surface layer of the P-type substrate well 5, to which a wide area wiring 17 described later for fixing the P-type substrate well 5 to the third potential is connected. . Reference numeral 9 is a source / drain diffusion region which is formed in the surface layer of the semiconductor substrate 1 and serves as a source / drain.

10a has a width of about 0.2 μm and a depth of about 0.4 μm.
In the shallow trench of m, the SiO ₂ insulator which is the _first insulator is embedded, and the shallow trench type isolation region which is the trench type element isolation region for performing element isolation is used. The well 5 has a depth less than the thickness of the well 5, and is formed between the high-concentration diffusion regions 6 and 8 and the source / drain diffusion regions 9. 10b is a first deep trench having a width of about 0.2 μm and a depth of about 0.4 μm.
In the deep trench type isolation region which is the trench type well isolation region in which the SiO ₂ insulator which is the insulator of the above is buried, the shield layer 2 is reached at a depth equal to or more than the thickness of the P type isolated well 3 and the P type It is formed in the isolation region between the isolated well 3 and the P-type substrate well 5.

Reference numeral 11 is a gate insulating film having a thickness of about 10 nm formed on the source / drain diffusion region 9, 12 is a gate electrode formed on the gate insulating film 11, and 13 is the source / drain diffusion region 9 and SiO 2. ₂ internal wiring electrically connected through the internal wiring hole 15a of the insulating film 14;
Is a memory electrically connected to the source / drain diffusion region 9 through the internal wiring hole 15b of the SiO ₂ insulating film 14.
The capacitor is composed of a lower electrode 16a, a dielectric 16b and an upper electrode 16c. Reference numeral 17 denotes the source / drain diffusion region 9 or the high-concentration diffusion regions 6, 7, 8 and Si.
The wide area wiring is electrically connected through the wide area wiring connection hole 18 of the O ₂ insulating film 14.

In the N-type semiconductor shield layer 2 configured as described above, the bottom surface of the P-type isolated well 3 is formed on the P-type substrate well 5.
Is electrically separated from the P-type substrate 1 electrically connected to, and has a depth equal to or larger than the thickness of the P-type isolated well 3,
The deep trench type isolation region 10b reaching the shield layer 2 of the N type semiconductor has a function of electrically isolating the side surface of the P type isolated well 3 from the P type substrate well 5. Therefore, the P-type isolated well 3 is electrically separated from the P-type substrate well 5, and the P-type isolated well 3 and the P-type substrate well 5,
The potentials of the P-type isolated well 3 and the P-type substrate well 5 can be set to different values in order to optimize the characteristics of the N-type semiconductor element formed in each.

Further, in the well separating method as described above, the shield layer 2 of the N-type semiconductor is the semiconductor substrate 1.
Since it is formed below the element formed on the surface, it does not occupy the area of the surface of the semiconductor substrate 1 and thus does not hinder the progress of high integration. Further, by separating the side surface in the deep trench type isolation region 10b reaching the N-type semiconductor shield layer 2, the conventional width of 1 μm is obtained.
Since the width of only 0.2 μm is required for the N-type well 4, the occupation of the area of the surface of the semiconductor substrate 1 is significantly reduced, which is advantageous in promoting high integration.

Further, in the semiconductor device configured as described above, a large number of elements (not shown) are formed in the same well, and these elements are formed between these elements, that is, between the adjacent source / drain diffusion regions 9. With a width of 0.2μ
By forming the shallow trench type isolation region 10a having a depth of m and a depth of 0.4 μm, the same function as increasing the distance between the adjacent source / drain diffusion regions 9 in the semiconductor substrate 1 can be obtained. That is, the isolation breakdown voltage between the source / drain diffusion regions 9 is improved.

Further, by forming the trench between the high concentration diffusion regions 6, 7, 8 for fixing the well potential and the source / drain diffusion region 9, the high concentration region 6,
A function similar to that of increasing the distance between 7, 8 and the source / drain diffusion region 9 can be obtained. That is, the junction breakdown voltage, which is the maximum applied voltage for maintaining the insulation characteristic of the PN junction in the opposite direction, increases.

Therefore, by forming the shallow trench type isolation region 10a between the elements, the elements can be formed in close proximity to each other, and higher integration can be promoted.

In this embodiment, it is needless to say that the above-described effects can be obtained even if the first conductivity type P type is N type and the second conductivity type N type is P type.

Next, a method of manufacturing the semiconductor device described above will be described with reference to FIGS. 2 to 21 sequentially show steps of the semiconductor device of this embodiment. First, as shown in FIG. 2A, a first insulating film 20 made of SiO ₂ which is a first insulator having a film thickness of about 200 nm and a film thickness of about 200 n are formed on the P-type semiconductor substrate 1.
The second insulating film 21 made of Si ₃ N ₄ which is the second insulating material of m is sequentially formed. Next, as shown in FIG. 2B, a resist pattern 22 is formed on the P-type semiconductor substrate 1 by photolithography so that the portion where the trench is formed becomes an opening, and then the resist 22 is masked. As the first insulating film 20, the first insulating film 20 and the second insulating film 21 are anisotropically etched. Next, when the resist 22 is removed, it becomes as shown in FIG.

Next, the semiconductor substrate 1 is anisotropically etched using the second insulating film 21 etched as shown in FIG.
First trench 10 corresponding to a depth of about 0.4 μm of 0a
form c. Next, as shown in FIG. 3B, a first protective film made of SiO ₂ which is a first insulator and has a film thickness of about 10 nm is formed on the surface of the P-type semiconductor substrate 1 in the first trench 10c. 23 is formed by thermal oxidation, and a second film having a thickness of about 20 nm is formed on the first protective film 23 and the entire surface of the semiconductor substrate 1.
The second protective film 24 made of Si ₃ N ₄ which is an insulating material is formed by the CVD method. Here, since the second insulating film 21 and the second protective film 24 formed thereon have the same components as Si ₃ N ₄ , they will be described below by including them in the second insulating film 21. The first protective film 23 is for protecting the surface of the semiconductor substrate 1 in the trench 10c from the second protective film 24 that exerts stress on the surface of the semiconductor substrate 1.

Next, a SiO ₂ insulator, which is a first insulator, is applied to the entire surface of the semiconductor substrate 1 by a glass coating method or the like to fill the inside of the first trench 10c, and then is etched back by an etch back method. SiO ₂ formed on the second insulating film 21
By completely removing the insulating film, the plug 25 made of a SiO ₂ insulator is formed in the first trench 10c as shown in FIG. 4A. Next, FIG.
As shown in (b), the deep trench isolation region 10
By forming a resist pattern 26 having an opening in the first trench 10c where b will be formed by photolithography and performing HF chemical treatment for selectively etching the SiO ₂ insulating film, The plug 25 in the trench 10c not covered with the resist is removed. Next, after removing the resist 26, the second protective film 24 formed on the bottom side surface of the first trench 10c from which the plug 25 has been removed is anisotropically removed by etching, and then the second insulating film 24 is formed. Using the film 21 as a mask, the first protective film 23 made of a SiO ₂ insulating film is anisotropically etched, and then the semiconductor substrate 1 below the trench 10c is anisotropically etched.
A deep trench 10d as shown in FIG. 5A is formed. (Hereinafter, the first trench 10c that has not been etched is referred to as a shallow trench 10e).

Next, as shown in FIG. 5B, a resist pattern 27 is formed by photolithography so as to cover the deep trench 10b formed above, and a plug in the shallow trench 10e is formed by HF chemical treatment. Remove 25. Next, as shown in FIG. 6A, after removing the resist 27, the Si ₃ N ₄ insulating film forming the second insulating film 21 and the second protective film 24 is selectively etched. H ₃ PO ₄ chemical treatment is performed to remove the second insulating film 21.
The second protective film 24 in the trench is completely removed. Next, on the entire surface of the semiconductor substrate 1, Si, which is a first insulator, is formed.
An insulating film 28 made of O ₂ is deposited by the CVD method,
As shown in FIG. 6B, the insulating film 28 made of SiO ₂ is buried in the shallow trench 10e and the deep trench 10d to complete the shallow trench isolation region 10a and the deep trench isolation region 10b. Here, since the first protective film 23, the first insulating film 20, and the insulating film 28 have the same components, they will be described below by including them in the insulating film 28.

Next, as shown in FIG. 7, a resist pattern 29 for forming the N-type semiconductor shield layer 2 is formed on the semiconductor substrate 1, and this resist pattern 29 is formed.
As a mask, by high-energy ion implantation method,
Phosphorus ions are implanted at an energy of about 1 MeV to form the N-type shield layer 2 in the deep trench 10d.
Next, as shown in FIG. 8, the resist pattern 29 is formed.
Is removed, a resist pattern 30 for forming an active region is formed by a photoengraving method, and the insulating film 28 is etched using the resist pattern 30 as a mask.
An active region 31 for forming a semiconductor device is obtained.
Next, as shown in FIG. 9, after removing the resist pattern 30, a third protective film 32 made of a SiO ₂ insulating film having a thickness of about 20 nm is formed on the active region 31. Next, a resist pattern (not shown) for forming a P-type well is formed by photolithography. At this time, the third protective film 32
Protects the active region 31 from a resist that adversely affects the semiconductor. By using this resist pattern as a mask and by implanting boron ions of about 10 ¹³ / cm ² at an energy of about 400 KeV by a high-energy implantation method, the P-type isolated well 3 and the P-type substrate well as shown in FIG. 5 is formed. Next, by a high energy implantation method, for example, boron ions of about 10 ¹² / cm ² are implanted with an energy of about 50 KeV, and channel doping is performed on the active regions 31 of the isolated well 3 and the substrate well 5.

Next, the resist is removed from the semiconductor substrate 1 and, as shown in FIG. 11, a resist pattern 34 is again formed by photolithography so that the substrate well 5 becomes an opening, and then this resist pattern is formed. 34 as a mask, with an energy of about 50 KeV, 10 ¹² / cm ²
Further, boron ions are additionally implanted to perform channel doping on the active region 31 of the substrate well 5. Next, as shown in FIG. 12, after removing the resist 34 from the semiconductor substrate 1, S
iO ₂ the third protective film 32 made of an insulating film is removed to form a gate insulating film 11 made of SiO ₂ insulating film of approximately 10nm on the active region 31, on the SiO ₂ insulating film 28 and the gate insulating film 11 About 100 nm conductor film 35, this conductor film 3
A SiO ₂ insulating film 36 of about 100 nm is sequentially deposited on the film 5.

Next, as shown in FIG. 13, a resist pattern to be a gate electrode is formed on the above substrate by photolithography, and this resist pattern is used as a mask for SiO ₂
After anisotropically etching the insulating film 36, the resist pattern is removed and the anisotropically etched SiO 2 is removed.
_{2 The} conductive film 35 is anisotropically etched using the insulating film 36 as a mask to form the gate electrode 12.

Next, as shown in FIG. 14, a resist pattern 37 for forming an N type diffusion region is formed on the substrate 1, and the resist pattern 37 is used as a mask.
About 30KeV of energy of about ¹⁰ 15 / cm ² phosphorus ions or energy of about ^{10 15} to about 50 KeV,
/ Cm ² arsenic ions are implanted to form source / drain diffusion regions 9 which are N type diffusion regions. Next, FIG.
As shown in FIG.
After removing the above, a resist pattern 38 for forming a P-type diffusion region is formed by a photolithography method, and using this resist pattern 38 as a mask, BF ₂ ions of 10 ¹⁵ / cm ² or 10 K at an energy of about 20 KeV are formed.
High-concentration regions 6 and 8 which are P-type diffusion regions of about 10 ¹⁵ / cm ² are formed with an energy of eV or less. After that, the resist pattern 38 is removed, and an insulating film 39 of SiO ₂ of about 100 nm is deposited on the entire surface of the substrate as shown in FIG.

Next, the internal wiring connection hole 1 is formed by photolithography.
A resist pattern for forming 5a is formed, and using this resist pattern as a mask, the SiO ₂ insulating film 39 is formed.
Is anisotropically etched to form the internal wiring connection hole 15a, and then the resist pattern is removed. After that, FIG.
As shown in, conductive film 4 of about 100 nm is formed on the entire surface of substrate 1.
After depositing 0, a resist pattern for forming the internal wiring 13 is formed by a photolithography method, and the conductive film 40 is anisotropically etched using the resist pattern as a mask to form the internal wiring 13. , Remove the resist,
As shown in FIG. 18, the SiO ₂ insulating film 4 is formed on the entire surface of the substrate 1.
1 is deposited and flattened by a resist etch back method or the like.

Next, as shown in FIG. 19, a resist pattern for forming the internal wiring connection hole 15b is formed, and this SiO _{2 is used} as a mask.
The insulating film 41 is anisotropically etched to form the internal wiring hole 15b.
And then removing the resist, about 100
A conductive film 42 having a thickness of nm is deposited. After that, a resist pattern for forming the lower electrode 16a of the memory capacitor 16 is formed by photolithography, and the conductive film 42 is anisotropically etched using the resist pattern as a mask.
After forming the lower electrode 16a, the resist is removed,
As shown in 0, a dielectric film 16b is formed on the upper surface and the side surface of the lower electrode 16a, and a conductor film 43 to be the upper electrode 16c is deposited on the entire surface of the substrate.

Next, a resist pattern for forming the upper electrode 16c is formed on the substrate by photolithography, and the conductor film 43 is used as a mask.
Is etched to form the upper electrode 16c of the memory capacitor, the resist is removed, and the SiO ₂ insulating film 44 is formed on the entire surface of the substrate to be planarized. After that, a resist pattern for forming the wide-area wiring connection hole 18 is formed by photolithography, and the resist pattern is used as a mask to form an S
The iO ₂ insulating film 44 is anisotropically etched to form wide-area wiring connection holes 18, the resist is removed, a metal film is deposited on the entire surface of the substrate, and a resist pattern for forming the wide-area wiring 17 is formed by photoengraving. Thereafter, the metal film is anisotropically etched using the resist as a mask to form the wide area wiring 17, and the resist is removed, whereby the semiconductor device according to the embodiment of FIG. 1 is formed.

In the method of manufacturing a semiconductor device described above, the shallow trench 10e is used to make use of the deep trench 1
Since 0d is formed, the deep trench 10d can be easily etched.

Example 2. A semiconductor device according to another embodiment of the present invention will be described below. This semiconductor device has a twin well structure in which a plurality of P-type wells are provided on an N-type semiconductor substrate and the P-type wells are electrically isolated from each other. FIG. 22 is a partial cross-sectional view of the semiconductor device according to the second embodiment. In this figure, 3, 6, 9, 10a, 1
0b to 18 are exactly the same as those in the first embodiment. 5
Reference numeral 0 denotes an N-type semiconductor substrate, which extends to the lower surface of the substrate in the lower part of the figure.

In the semiconductor device configured as described above, the bottom surface of the P-type isolated well 3 has an N-type semiconductor substrate 50.
And electrically separated. Furthermore, the deep trench type isolation region 10b having a depth equal to or larger than the thickness of the P type isolated well 3 and having an insulator embedded in the trench reaching the N type semiconductor substrate 50 is adjacent to the adjacent P type isolated well 3. The deep trench type isolation region 10b, which is formed between them and reaches the N type semiconductor substrate 50, electrically separates the side surfaces of these P type isolated wells 3 from each other. Therefore, the adjacent P-type isolated wells 3 are electrically separated from each other, and
As described above, different potentials can be set in the P-type isolated wells 3, and the semiconductor element characteristics can be optimized.

Further, similar to the first embodiment, by forming the shallow trench type isolation region 10a in which the SiO ₂ insulator is embedded in the trench, the same effect as the first embodiment can be obtained.

Example 3. Hereinafter, a semiconductor device according to still another embodiment of the present invention will be described. FIG. 23 is a partial cross-sectional view of the semiconductor device of the third embodiment. The difference from the semiconductor device of the first embodiment described above is that the deep trench isolation region 10b is formed by filling the trench with an insulator. Instead, the conductor 52 is embedded in the trench and is surrounded by the insulating film 51. The conductor 52 serves as the internal wiring 13, and one end of the internal wiring 13 is N The mold shield layer 2 and the other end are electrically connected to the wide area wiring 17.

Also in the semiconductor device having such a structure, the P-type isolated well 3 and the P-type substrate well 5 are electrically isolated by the insulator 51 formed in the deep trench isolation region 10b. Therefore, the first embodiment
It has the same effect as the effect described above.

Further, in the semiconductor device of this embodiment, the N-type shield layer 2 and the deep trench type isolation region 10b are formed.
Since the internal wiring 13 therein is connected, the N-type shield layer can be set to an arbitrary potential.

Next, a method of manufacturing a semiconductor device according to this embodiment will be described below with reference to FIGS. 2 to 5A, 7 to 21 and 24 to 26. 2 to 5
The steps until forming the shallow trench type isolation region 10a and the deep trench type isolation region 10b shown in (a) are exactly the same as those described in the first embodiment. Next, FIG.
As shown in (a), the third process is performed by the LP-CVD method.
The insulating film 51 made of SiO ₂ which is the insulator of
m is deposited and this insulating film 51 is anisotropically etched by the reactive ion etching method to form the second insulating film 21.
When the insulating film 51 on the top and the bottom of the deep trench 10d is removed and the first protective film 23 on the bottom of the deep trench 10d is removed, as shown in FIG. _{The two} insulating films 51 are left.

Next, as shown in FIG. 25A, a Si semiconductor film 52 having a high concentration of N-type impurities added thereto is deposited to a thickness of about 150 to 200 nm on the entire surface of the substrate by a CVD method to fill the deep trench 10d. . Next, as shown in FIG. 25B, after forming a resist pattern 53 for forming the internal wiring 13 by a photoengraving method, the resist pattern 53 is used as a mask to remove the Si semiconductor film 52 from the reactive ion beam. The internal wiring 13 is formed by anisotropic etching by the etching method. Then, the resist is removed, as shown in FIG. 26 (a), the HF chemical treatment for selectively etching the SiO ₂ insulating film to remove the SiO ₂ insulating film plug 25 in the shallow trench 10e,
Further, H ₃ for selectively etching the Si ₃ N ₄ insulating film
The second insulating film 21 and the second protective film 24 are completely removed by PO ₄ chemical treatment.

Next, as shown in FIG. 26B, C
SiO ₂ composed of the first insulator is formed on the entire surface of the substrate by the VD method.
Insulating film 28 is deposited to a thickness of about 150 nm to form shallow trench 10e.
The SiO ₂ insulating film 28 is embedded in the inside to form the shallow trench type isolation region 10a. After that, the semiconductor device shown in FIG. 23 is obtained by the same manufacturing method as that shown in FIGS. 7 to 21 in the first embodiment.

[0049]

In the semiconductor device of the first invention, since the well isolation is performed by the trench type well isolation region, the isolation region for isolating the well can be made small, and high integration can be promoted. Have an effect.

In the method of manufacturing a semiconductor device of the second invention, a trench type element isolation region having an insulator filled in a shallow trench and a trench type well isolation region having an insulator filled in a deep trench are provided. Has an effect that can be efficiently formed.

In the method of manufacturing a semiconductor device according to the third aspect of the invention, a trench type element isolation region in which an insulator is embedded in a shallow trench and a conductor which is surrounded by the insulator in a deep trench are provided. This has the effect that the buried trench type well isolation region can be efficiently formed.

[Brief description of drawings]

FIG. 1 is a partial cross-sectional view showing a configuration of a semiconductor device that is Embodiment 1 of the present invention.

FIG. 2 is a cross-sectional view showing a part of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a part of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a part of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a part of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a part of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a part of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 8 is a cross-sectional view showing a part of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 9 is a cross-sectional view showing a part of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 10 is a cross-sectional view showing a part of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 11 is a cross-sectional view showing a part of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 12 is a cross-sectional view showing a part of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 13 is a cross-sectional view showing a part of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 14 is a cross-sectional view showing a part of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 15 is a cross-sectional view showing a part of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 16 is a cross-sectional view showing a part of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 17 is a cross-sectional view showing a part of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 18 is a cross-sectional view showing a part of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 19 is a cross-sectional view showing a part of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 20 is a cross-sectional view showing a part of the process for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 21 is a cross-sectional view showing a part of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 22 is a partial cross-sectional view showing the configuration of a semiconductor device that is Embodiment 2 of the present invention.

FIG. 23 is a partial cross-sectional view showing the configuration of a semiconductor device that is Embodiment 3 of the present invention.

FIG. 24 is a cross-sectional view showing a step in the semiconductor device manufacturing method of the third embodiment of the present invention.

FIG. 25 is a cross-sectional view showing a step in the semiconductor device manufacturing method of the third embodiment of the present invention.

FIG. 26 is a cross-sectional view showing a step in the semiconductor device manufacturing method of the third embodiment of the present invention.

FIG. 27 is a partial cross-sectional view showing the structure of a conventional semiconductor device.

[Explanation of symbols]

1 P-type semiconductor substrate, 2 N-type shield layer, 3 P-type isolated well, 5 P-type substrate well, 10a Shallow trench type isolation region, 10b Deep trench type isolation region, 10c
1st trench, 10d deep trench, 10e shallow trench, 20 1st insulating film, 21 2nd insulating film, 23 1st protective film, 24 2nd protective film, 25
Plug, 28 insulating film, 50 N-type semiconductor substrate, 51
Insulator, 52 conductor.

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-4-241451 (JP, A) JP-A 5-299591 (JP, A) JP-A 63-60553 (JP, A) JP-A 62- 277745 (JP, A) JP-A-63-116445 (JP, A) Fukukaihei 4-93152 (JP, U) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/76 H01L 21 / 74 H01S 21/761 H01L 27/08 331

Claims (3)

(57) [Claims] 1. A first conductive type semiconductor substrate, which is formed on a main surface of a semiconductor substrate and is separated by a trench type well separation region.
A well of a conductive type and a buried region of a second conductive type formed on the entire bottom surface of one of the isolated wells including the trench type well isolation region, and the other of the isolated wells is the semiconductor substrate. Touching,
The trench type well isolation region is formed deeper than the well and terminates inside the buried region. 2. A first insulating layer on a semiconductor substrate of the first conductivity type.
Edge film and second insulating film are sequentially formed to form a laminated film
And patterning the laminated film and using this as a mask
Anisotropically etch the semiconductor substrate to form the first trench
Forming step and covering the inner wall of the first trench
The same material as the first insulating film is formed on the entire surface of the semiconductor substrate.
The first protective film and the second insulating film made of the same material as the second insulating film.
Protective film is sequentially formed, and an insulating film is formed on the entire surface.
After filling the inside of the first trench with
The insulating film is formed in the first trench.
And the first step using a resist mask.
Of the desired trench selected from among the trenches
The second and the first in the trench after removing the groove.
The protective film of the semiconductor substrate is removed, and the semiconductor substrate under the trench is further removed.
Of forming a deep trench by anisotropically etching
And using a resist mask that covers the deep trench
Note that the plug remaining in the first trench is removed,
And a process for removing the second insulating film and the second protective film.
Then, the first insulating layer is formed on the entire surface of the semiconductor substrate.
An insulating film of the same material as the film is formed to form the deep trench and
The other first trenches are buried to form a trench type trench.
Forming a cell isolation region and a trench type element isolation region
Process and selectively ion-implant a predetermined area of the semiconductor substrate.
The second conductivity type buried region,
So that the trench type well isolation region is internally terminated.
The step of forming with a predetermined depth and the above half by ion implantation
Separated on the conductive substrate by the trench type well isolation region
And a step of forming a well of the first conductivity type
And a method for manufacturing a semiconductor device. 3. A first insulating layer on a semiconductor substrate of the first conductivity type.
Forming a laminated film Enmaku and second insulation Enmaku are sequentially formed
And patterning the laminated film and using this as a mask
Anisotropically etch the semiconductor substrate to form the first trench
Forming step and covering the inner wall of the first trench
The same material as the first insulating film is formed on the entire surface of the semiconductor substrate.
The first protective film and the second insulating film made of the same material as the second insulating film.
Protective film is sequentially formed, and an insulating film is formed on the entire surface.
After filling the inside of the first trench with
The insulating film is formed in the first trench.
And the first step using a resist mask.
Of the desired trench selected from among the trenches
The second and the first in the trench after removing the groove.
The protective film of the semiconductor substrate is removed, and the semiconductor substrate under the trench is further removed.
Of forming a deep trench by anisotropically etching
And anisotropy after forming an insulating film on the entire surface of the semiconductor substrate
Etching the insulating film to the deep trench side
Surface, and leave a conductor film in the deep trench.
By embedding and forming the insulating film in the deep trench.
Trench-type well isolation consisting of the above conductor film surrounded by
Forming a region and then in the first trench
The remaining plug is removed, and the second insulating film is further removed.
And a step of removing the second protective film, and
An insulating film made of the same material as the first insulating film is formed on the entire surface of the conductor substrate.
A trench-type element formed by filling the first trench
A step of forming a child isolation region and a predetermined area of the semiconductor substrate.
Region of the second conductivity type by selectively implanting ions into the region
The trench-type well isolation inside the buried region.
The conductor film is formed with a predetermined depth so that the region ends.
Electrically connecting the buried region to the buried region, and
Injecting the trench well into the semiconductor substrate by implantation
Forming wells of the first conductivity type separated by regions
A method of manufacturing a semiconductor device, which comprises:
Law.