JPS55154770A - Manufacture of complementary mos semiconductor device - Google Patents

Manufacture of complementary mos semiconductor device

Info

Publication number
JPS55154770A
JPS55154770A JP6345179A JP6345179A JPS55154770A JP S55154770 A JPS55154770 A JP S55154770A JP 6345179 A JP6345179 A JP 6345179A JP 6345179 A JP6345179 A JP 6345179A JP S55154770 A JPS55154770 A JP S55154770A
Authority
JP
Japan
Prior art keywords
substrate
layer
groove
semiconductor device
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6345179A
Other languages
Japanese (ja)
Inventor
Yoshihide Nagakubo
Susumu Kayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP6345179A priority Critical patent/JPS55154770A/en
Publication of JPS55154770A publication Critical patent/JPS55154770A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To enhance the integrating degree of a complementary MOS semiconductor device by forming a narrow and deep groove by utilizing anisotropic Si etching in the boundary between a semiconductor substrate and a well layer and burying insulating layer in the groove to shorten the distance between diffused layers. CONSTITUTION:A resist pattern 12 having a hole corresponding to the boundary between an n-type Si substrate 11 and a p-type well layer 18 to be formed on the surface of the substrate 11 is formed thereon, ion milling is executed with Ar gas at the substrate 11 to etch the substrate 11 in narrow and deep manner to form an etched groove 13 having deeper depth than the layer 18, n-type impurity ion is implanted to the bottom surface of the groove 13 to form a field inversion preventive layer 14 thereon. Then, the pattern 12 is removed, heat treated, an SiO2 layer 16 is filled in the groove 13, and the SiO2 film 15 on the surface of the substrate 11 is simultaneously removed. Thereafter, it is etched to slightly reduce the height of the surface 17 of the layer 16, a p-type well layer 18 is diffused and formed on one substrate 11 isolated via the layer 16, and element regions are formed in the confronting substrate to form a C-MOS device.
JP6345179A 1979-05-23 1979-05-23 Manufacture of complementary mos semiconductor device Pending JPS55154770A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6345179A JPS55154770A (en) 1979-05-23 1979-05-23 Manufacture of complementary mos semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6345179A JPS55154770A (en) 1979-05-23 1979-05-23 Manufacture of complementary mos semiconductor device

Publications (1)

Publication Number Publication Date
JPS55154770A true JPS55154770A (en) 1980-12-02

Family

ID=13229607

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6345179A Pending JPS55154770A (en) 1979-05-23 1979-05-23 Manufacture of complementary mos semiconductor device

Country Status (1)

Country Link
JP (1) JPS55154770A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5940563A (en) * 1982-08-31 1984-03-06 Toshiba Corp Manufacture of semiconductor device
JPS5955055A (en) * 1982-09-24 1984-03-29 Fujitsu Ltd Manufacture of semiconductor device
JPS59121865A (en) * 1982-12-28 1984-07-14 Toshiba Corp Manufacture of complementary semiconductor device
JPS6038861A (en) * 1983-08-12 1985-02-28 Hitachi Ltd Complementary type semiconductor integrated circuit device and manufacture thereof
JPS61500140A (en) * 1983-10-11 1986-01-23 アメリカン テレフオン アンド テレグラフ カムパニ− Semiconductor circuits including complementary metal-oxide-semiconductor devices
JPS61181155A (en) * 1984-11-29 1986-08-13 テキサス　インスツルメンツ　インコーポレイテッド Making high integration cmos ic
JPS6252957A (en) * 1985-09-02 1987-03-07 Toshiba Corp Cmos semiconductor device
US6461946B2 (en) 2000-05-01 2002-10-08 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor device

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5940563A (en) * 1982-08-31 1984-03-06 Toshiba Corp Manufacture of semiconductor device
JPH0481339B2 (en) * 1982-08-31 1992-12-22 Tokyo Shibaura Electric Co
JPS5955055A (en) * 1982-09-24 1984-03-29 Fujitsu Ltd Manufacture of semiconductor device
JPS59121865A (en) * 1982-12-28 1984-07-14 Toshiba Corp Manufacture of complementary semiconductor device
JPH0481340B2 (en) * 1982-12-28 1992-12-22 Tokyo Shibaura Electric Co
JPS6038861A (en) * 1983-08-12 1985-02-28 Hitachi Ltd Complementary type semiconductor integrated circuit device and manufacture thereof
JPH0469433B2 (en) * 1983-08-12 1992-11-06 Hitachi Ltd
JPS61500140A (en) * 1983-10-11 1986-01-23 アメリカン テレフオン アンド テレグラフ カムパニ− Semiconductor circuits including complementary metal-oxide-semiconductor devices
JPS61181155A (en) * 1984-11-29 1986-08-13 テキサス　インスツルメンツ　インコーポレイテッド Making high integration cmos ic
JPS6252957A (en) * 1985-09-02 1987-03-07 Toshiba Corp Cmos semiconductor device
US6461946B2 (en) 2000-05-01 2002-10-08 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor device

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