JPS57157540A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS57157540A JPS57157540A JP4231581A JP4231581A JPS57157540A JP S57157540 A JPS57157540 A JP S57157540A JP 4231581 A JP4231581 A JP 4231581A JP 4231581 A JP4231581 A JP 4231581A JP S57157540 A JPS57157540 A JP S57157540A
- Authority
- JP
- Japan
- Prior art keywords
- face
- width
- substrate
- groove
- diffusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title 1
- 238000009792 diffusion process Methods 0.000 abstract 3
- 238000005530 etching Methods 0.000 abstract 3
- 239000000758 substrate Substances 0.000 abstract 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 238000002955 isolation Methods 0.000 abstract 2
- QNRATNLHPGXHMA-XZHTYLCXSA-N (r)-(6-ethoxyquinolin-4-yl)-[(2s,4s,5r)-5-ethyl-1-azabicyclo[2.2.2]octan-2-yl]methanol;hydrochloride Chemical compound Cl.C([C@H]([C@H](C1)CC)C2)CN1[C@@H]2[C@H](O)C1=CC=NC2=CC=C(OCC)C=C21 QNRATNLHPGXHMA-XZHTYLCXSA-N 0.000 abstract 1
- 239000007864 aqueous solution Substances 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 230000010354 integration Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- 239000011347 resin Substances 0.000 abstract 1
- 229920005989 resin Polymers 0.000 abstract 1
- 238000007493 shaping process Methods 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
- H01L21/30608—Anisotropic liquid etching
Landscapes
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- General Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Bipolar Transistors (AREA)
- Element Separation (AREA)
- Weting (AREA)
Abstract
PURPOSE:To obtain an element isolating region having a small occupying area by forming a deep narrow groove through the anisotropic etching of the substrate of a (110) face and shaping a deep diffusion layer. CONSTITUTION:A mask 11 is executed to the (110) face of the Si substrate 10, and a pattern 12 is formed in a rhombus having the <1-12> direction and the direction inclined to said direction at 70.5 deg.. A (111) face is hardly etched more than the (110) face through anisotropic etching by a KOH aqueous solution, and the deep groove of a vertical wall surface is formed without the etching of a side surface. when rhombic etched grooves 21, 22 are formed to an N epitaxial layer 3 on a P type Si substrate 1 according to this method, width can be shaped in approximately 1-3mum because the side surface is not etched, the grooves with approximately 1mum width are buried with SiO2 through the oxidation of the surface, and insulating resin is filled when the width is said value or higher. Or diffusion and isolation are conducted at the same time as the diffusion of a P base, 10mum or lower is also sufficient as groove width at that time. According to such constitution, the occupying area of the isolation layer can be reduced more than a V-shaped groove, and the degree of integration of the device is increased.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4231581A JPS57157540A (en) | 1981-03-25 | 1981-03-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4231581A JPS57157540A (en) | 1981-03-25 | 1981-03-25 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS57157540A true JPS57157540A (en) | 1982-09-29 |
Family
ID=12632577
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4231581A Pending JPS57157540A (en) | 1981-03-25 | 1981-03-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57157540A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60257539A (en) * | 1984-06-04 | 1985-12-19 | Hitachi Micro Comput Eng Ltd | Semiconductor device and production thereof |
| JPH02260442A (en) * | 1989-03-30 | 1990-10-23 | Toshiba Corp | Dielectric isolation type semiconductor substrate |
| JPH03253025A (en) * | 1990-03-02 | 1991-11-12 | Nippon Telegr & Teleph Corp <Ntt> | Substrate to be worked and anisotropic etching of silicon |
| JP2007201015A (en) * | 2006-01-24 | 2007-08-09 | Seiko Epson Corp | Silicon wafer, method for processing the same, and process for manufacturing liquid injection head |
-
1981
- 1981-03-25 JP JP4231581A patent/JPS57157540A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60257539A (en) * | 1984-06-04 | 1985-12-19 | Hitachi Micro Comput Eng Ltd | Semiconductor device and production thereof |
| JPH02260442A (en) * | 1989-03-30 | 1990-10-23 | Toshiba Corp | Dielectric isolation type semiconductor substrate |
| JPH03253025A (en) * | 1990-03-02 | 1991-11-12 | Nippon Telegr & Teleph Corp <Ntt> | Substrate to be worked and anisotropic etching of silicon |
| JP2007201015A (en) * | 2006-01-24 | 2007-08-09 | Seiko Epson Corp | Silicon wafer, method for processing the same, and process for manufacturing liquid injection head |
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