JPS556891A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device

Info

Publication number
JPS556891A
JPS556891A JP7917979A JP7917979A JPS556891A JP S556891 A JPS556891 A JP S556891A JP 7917979 A JP7917979 A JP 7917979A JP 7917979 A JP7917979 A JP 7917979A JP S556891 A JPS556891 A JP S556891A
Authority
JP
Japan
Prior art keywords
conductive type
semiconductor
range
semiconductor device
indentation portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7917979A
Other languages
Japanese (ja)
Inventor
Naonobu Sato
Kaoru Niino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP7917979A priority Critical patent/JPS556891A/en
Publication of JPS556891A publication Critical patent/JPS556891A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To obtain this semiconductor device that has high resisting pressure and the great degree of integration, by embedding one portion of an EP layer onto a substrate by utilizing anisotropic etching technique.
CONSTITUTION: This semiconductor device is produced by forming the second conductive type semiconductor layer 15 with an indentation portion 13' on the second conductive type first high impurities concentration range 14 made up to an indentation portion 13 of the first conductive type semiconductor substrate 11 by epitaxial growth, by etching its surface and by building up an isolation range 19 reaching the substrate 11. In this case, the first conductive type semiconductor range 16 is formed by introducing the first conductive type impurities to the semiconductor region 15 prior to etching, and the second conductive type semiconductor region 15 is etched in such a manner that the semiconductor range 16 of the outside of the indentation portion 13' is removed leaving a semiconductor range 16a of a bottom of the indentation portion 13'. Thus, this semiconductor device that has high resisting pressure and the great degree of integration can be made up.
COPYRIGHT: (C)1980,JPO&Japio
JP7917979A 1979-06-25 1979-06-25 Manufacturing method of semiconductor device Pending JPS556891A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7917979A JPS556891A (en) 1979-06-25 1979-06-25 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7917979A JPS556891A (en) 1979-06-25 1979-06-25 Manufacturing method of semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP50145041A Division JPS5269587A (en) 1975-12-08 1975-12-08 Device and manufacture for high voltage resisting semiconductor

Publications (1)

Publication Number Publication Date
JPS556891A true JPS556891A (en) 1980-01-18

Family

ID=13682743

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7917979A Pending JPS556891A (en) 1979-06-25 1979-06-25 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JPS556891A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57115258U (en) * 1981-01-10 1982-07-16

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57115258U (en) * 1981-01-10 1982-07-16

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