JPH05335569A - Mis field-effect transistor - Google Patents

Abstract

PURPOSE:To suppress the occurrence of hot carriers by forming a low- concentration impurity area in a drain area, to which high voltage is applied, in a self alignment manner. CONSTITUTION:At one end of a gate electrode 12A is provided a drain region consisting of the n<+>-type drain region 4 provided on the surface of a p<->-type silicon substrate 1 and the n<->-type drain region 5 provided on the surface of the p<->-type silicon substrate 1 at the side of a first trench 8. At the other end of the gate electrode 12 is provided a second trench 9 in self alignment with the first trench 8. A source region is provided, which consists of a metallic layer 10 which has filled up the n<+>-type source region 3 and the second trench 9 provided on the p<->-type substrate 1 at the bottom. A short channel MIS field- effect transistor is formed by providing a gate electrode 12 at the sidewall and the bottom of the first trench 8. Accordingly, the occurrence of hot carriers can be suppressed by a low-concentration impurity area in a self-alignment manner in the drain region.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MIS type semiconductor device, and more particularly to a high speed short channel MIS field effect transistor having improved hot carrier effect and improved transfer conductance. Conventionally, in a MIS field-effect transistor having a relatively short channel length, in order to improve deterioration of transfer conductance due to hot carriers caused by a strong electric field near the drain region, the so-called LDD (Lightly Doped D) is used.
A MIS field effect transistor having a (rain) structure was formed. In the conventional method, the transfer conductance in terms of life can be improved, but since the low-concentration impurity region of the LDD structure is formed in self-alignment and symmetrically, it is not necessary to consider the hot carrier effect, and high voltage is not applied. Since it is also formed in the source region, a high resistance is attached to the source region, and the transfer conductance during operation cannot be increased. Therefore, there is a problem that speeding up is not achieved even if the transistor size is miniaturized. Further, although it is self-aligned, there is a problem that further miniaturization cannot be performed because the low concentration impurity region is formed on the surface of the semiconductor substrate. Therefore, there is a demand for a means capable of improving the hot carrier effect and forming a high speed and highly integrated short channel MIS field effect transistor.

[0002]

2. Description of the Related Art FIG. 5 is a schematic side sectional view of a conventional MIS field effect transistor, in which 51 is a p ^- type silicon substrate and 52 is a p-type silicon substrate.
Type channel stopper region, 53 is n ⁺ type source region, 54
Is an n ⁺ type drain region, 55 is an n ⁻ type source region, and 56 is n ^−.
-Type drain region, the full _Lee Rudo oxide film 57, 58 is a gate oxide film, 59 gate electrode, 60 is the side wall oxide film, 61 is an impurity blocking oxide film, 62 is phosphosilicate glass (PSG) film, 63
Indicates Al wiring. In the figure, a gate electrode is formed on the p ⁻ type silicon substrate 51 with a thin gate oxide film 58 interposed therebetween.
59 is provided on the side wall of the gate electrode 59 side wall oxide film 60 which is self-aligned formation is provided immediately below side wall oxide films 60, n to the drain side ^- -type drain region 56, n the source side ^- -type The source region 55 is provided and the sidewall oxide film 60 is provided.
N ⁻ type drain region 56 and n ⁻ type source region on both ends of
N ⁺ type drain region 54 and n ⁺ type source region in contact with 55
A so-called LDD structure short channel MIS field effect transistor provided with 53 is formed. n
^A high voltage is applied due to the existence of the -type drain region 56.
^Although the electric field near the ⁺ type drain region 54 is relaxed and the deterioration of the transfer conductance due to the hot carrier effect over the life is improved, the same reference voltage as that of the p ⁻ type silicon substrate 51 is applied and the hot carrier effect does not occur. ^Since the n ⁻ type source region 55 having an unnecessarily high resistance is formed in the ⁺ type source region 53, the transfer conductance during operation cannot be high, so that a short channel MIS field effect transistor is formed. On the contrary, there is a drawback that a higher speed cannot be achieved.

[0003]

The problem to be solved by the present invention is, as shown in the conventional example, in the conventional short channel MIS field effect transistor of the LDD structure, the transmission of the lifetime due to the hot carrier effect. In order to improve the deterioration of conductance, the low concentration impurity region formed by self-alignment is formed not only in the required drain region but also in the unnecessary source region, so that the source region has a large resistance. Therefore, the transmission conductance during operation was reduced, and although it was miniaturized, high speed could not be achieved.

[0004]

Means for Solving the Problems The above problems include a one-conductivity type semiconductor substrate, a first trench provided in the semiconductor substrate, and a gate oxide film provided on a sidewall and a bottom of the first trench. A gate electrode in which the first trench is buried via the gate oxide film, a first high-concentration impurity region of opposite conductivity type provided on the surface of the semiconductor substrate outside one end of the gate electrode, A drain region formed of a low-concentration impurity region of opposite conductivity type provided on the side surface of the first trench in the semiconductor substrate in contact with the first high-concentration impurity region; and a sidewall at the other end of the gate electrode. A second trench provided in the semiconductor substrate in contact with the gate oxide film, a second high-concentration impurity region of the opposite conductivity type provided in the semiconductor substrate at the bottom of the second trench, and It is solved by MIS field effect transistor of the invention comprising a source region formed of a conductive film embedded second trench.

[0005]

[Operation] That is, in the MIS field-effect transistor of the present invention, a first drain provided with a voltage higher than that applied to the semiconductor substrate is provided on the surface of the semiconductor substrate.
A high-concentration impurity region and a first high-concentration impurity region in contact with the first high-concentration impurity region, the low-concentration impurity region provided on the semiconductor substrate on the side surface of the first trench, The second high-concentration impurity region provided in the semiconductor substrate on the bottom surface of the second trench self-aligned in the first trench and the conductive film filling the second trench, and the gate is formed on the sidewall of the first trench. And the MIS field effect transistor formed by the gate electrode filling the first trench via the gate oxide film provided on the bottom. Therefore, since the low-concentration impurity region can be formed in the drain region to which a high voltage is applied in a self-aligned manner, the generation of hot carriers can be suppressed, so that the deterioration of the transfer conductance over the life can be improved and the high reliability can be obtained. In the source region where the hot carrier effect is irrelevant, the operating resistance can be reduced by forming the source region composed of the high-concentration impurity region and the low-resistance conductive film from the gate electrode end without forming the low-concentration impurity region. Speeding up by improving the transfer conductance during operation,
Further, since the low-concentration impurity region formed in the drain region can be formed on the side surface of the first trench which does not require a layout area on the surface, high integration can be realized. That is, it is possible to obtain a MIS field effect transistor which enables formation of a highly reliable, high speed and highly integrated semiconductor integrated circuit.

[0006]

EXAMPLES The present invention will be described in detail below with reference to illustrated examples. FIG. 1 is a schematic side sectional view of a first embodiment of a MIS field effect transistor of the present invention, and FIG.
Schematic side sectional view of the second embodiment of the IS field effect transistor, FIG. 3 is a schematic side sectional view of the third embodiment of the MIS field effect transistor of the present invention, FIGS. 4 (a) to 4 (e).
FIG. 6 is a process cross-sectional view of an example of the method for manufacturing the MIS field effect transistor of the present invention. The same object is denoted by the same symbol throughout the drawings. FIG. 1 shows a first MIS field effect transistor of the present invention when a p-type silicon substrate is used.
1 is a p ^- type silicon substrate of about 10 ¹⁶ cm ⁻³ , 2 is a p-type channel stopper region of about 10 ¹⁷ cm ⁻³ , and 3 is n of about 10 ²⁰ cm ^{−3. +} Type source region, 4
An n ⁺ -type drain region of about 10 ²⁰ cm ^-3 , 5 is an n ^- type drain region of about 10 ¹⁸ cm ^-3 , 6 is a third trench (for element isolation) having a depth of about 3 μm, and 7 is a third Trench filling insulating film, 8 is a first trench with a depth of about 0.5 μm (for forming a buried gate), 9 is a second trench with a depth of about 0.5 μm (for forming a buried metal source region), 10 is a buried metal source Region (tungsten silicide), 11 is 15
Gate oxide film of about nm, 12 is a gate electrode with a gate length of about 0.6 μm, 13 is an oxide film for impurity blocking of about 35 nm, 14
Is about 0.6 μm phosphosilicate glass (PSG) film, 15 is 1 μm
The degree of Al wiring is shown. In the figure, a third trench 6 is provided in the p ⁻ type silicon substrate 1, a p type channel stopper region is provided on the bottom surface of the third trench 6, and an element isolation region filled with an insulating film 7 is formed. The first trench 8 is provided in the element formation region between the element isolation regions, the gate oxide film 11 is provided on the side wall and the bottom of the first trench 8, and the first trench 8 is provided through the gate oxide film 11. A gate electrode 12 in which the first trench 8 is buried flat is provided. In addition, p ⁻ at one end of the gate electrode 12
The drain region composed of the n ⁺ type drain region 4 provided on the surface of the type silicon substrate 1 and the n ⁻ type drain region 5 provided on the p ⁻ type silicon substrate 1 on the side surface of the first trench 8 is a gate electrode 12 At the other end of the first trench 8
The second trench 9 is provided in self-alignment with
Of the bottom surface of the trench 9 in which the n ⁺ type source region 3 provided in the p ⁻ type silicon substrate 1 and the source region made of a conductive film (metal layer) 10 in which the second trench 9 is evenly provided are provided. And a short channel MIS field effect transistor having is formed. Therefore, since the low-concentration impurity region can be formed in the drain region to which a high voltage is applied in a self-aligned manner, the generation of hot carriers can be suppressed, so that the deterioration of the transfer conductance over the life can be improved and the high reliability can be obtained. ,
In the source region where the hot carrier effect is irrelevant,
By forming the high-concentration impurity region and the source region made of the low-resistance conductive film from the gate electrode end without forming the low-concentration impurity region, the operating resistance can be reduced, and thus the transfer conductance at the time of operation can be improved. In addition, the low-concentration impurity region formed in the drain region can be formed on the side surface of the first trench, which does not require a layout area on the surface, thereby enabling high integration. FIG. 2 is a schematic side sectional view of a second embodiment of the MIS field effect transistor of the present invention, in which there is no distinction between a drain region to which a high voltage is applied and a source region to which a reference voltage is applied, and a bidirectional MIS field effect. In the case of transistors, 1, 2, 6 to 8 and 11 to 15 are the same as those in FIG.
Indicates an n ⁺ type source / drain region, and 17 indicates an n ⁻ type source / drain region. In the figure, there is no distinction between the drain region and the source region, and the n ⁺ type source / drain region 16
And the n ⁻ -type source / drain region 17 are formed in the same structure as in FIG. 1 except that a symmetrical source / drain region is formed. In this embodiment, bidirectional MI
Since it is used as an S field effect transistor, even if one of them is used as a source region, a high resistance always exists in the source region, so that the transfer conductance cannot be improved during operation. The effect of the embodiment can be achieved, and the manufacturing process is facilitated. FIG. 3 is a schematic side sectional view of a third embodiment of the MIS field-effect transistor of the present invention.
15 is the same as FIG. 1, 18 is an n ⁻ -type impurity well region,
Reference numeral 19 indicates a p ⁺ type source / drain region. In the figure, an N channel MIS having the structure of the first embodiment is shown.
It has a field effect transistor and a structure similar to that of the second embodiment, the conductivity type of the source / drain region is p-type, and the p ⁺ -type source / drain region extends to the side surface of the first trench 8.
C-MOS comprising a P-channel MIS field effect transistor provided with 19 and further provided with an n ⁻ type impurity well region 18 so as to include all p ⁺ type source / drain regions 19.
Is composed of. In the present embodiment, in addition to the effect of the first embodiment of the N-channel MIS field effect transistor considering the hot carrier effect, high integration and high speed P-channel MIS which does not need to consider the hot carrier effect.
It is possible to obtain an optimum C-MOS that realizes high reliability, high speed, and high integration in which field effect transistors coexist. Next, an embodiment of a method of manufacturing a MIS field effect transistor according to the present invention will be described with reference to FIGS. 4 (a) to 4 (e) and FIG. However, here, only the manufacturing method relating to the formation of the MIS field effect transistor of the present invention will be described, and the manufacturing method relating to the formation of various elements (other transistors, resistors, capacitors, etc.) mounted in a general semiconductor integrated circuit will be described. Is omitted. 4A, an oxide film 20 of about 30 nm and a nitride film 21 of about 50 nm are grown on the p ⁻ type silicon substrate 1. Then, using a normal photolithography technique, the nitride film 21 and the oxide film 20 are selectively and sequentially etched using a resist (not shown) as a mask layer. Then, expose the exposed p ⁻ -type silicon substrate 1 to 3 μm
Etching to some extent to form a third trench 6 for element isolation. Then, the resist (not shown) is removed. Then, an oxide film (not shown) for ion implantation having a thickness of about 20 nm is grown. Next, boron is ion-implanted using the nitride film 21 as a mask layer. Then, heat treatment is performed to form the p-type channel stopper region 2. Next, the oxide film (not shown) for ion implantation is removed by etching. Next, a chemical vapor deposition oxide film 7 is grown and anisotropically dry-etched to fill the third trench 6 to form an element isolation region. 4B, using a normal photolithography technique, the nitride film 21 and the oxide film 20 are selectively and sequentially etched using the resist (not shown) and the oxide film 7 as a mask layer. Next, the exposed p ⁻ type silicon substrate 1 is etched by about 0.3 μm to form a first trench 8. Then, the resist (not shown) is removed. Then, an oxide film (not shown) for ion implantation having a thickness of about 20 nm is grown. Next, phosphorus is obliquely ion-implanted using the nitride film 21 and the oxide film 7 as a mask layer. Next, the oxide film (not shown) for ion implantation is removed by etching. Then, using the nitride film 21 and the oxide film 7 as a mask layer, the p ⁻ type silicon substrate 1 is etched by about 0.2 μm to remove the phosphorus injected into the bottom surface of the first trench 8 by etching. Next, a chemical vapor deposition oxide film 22 is grown,
Anisotropic dry etching is performed to fill the first trench 8. Then, heat treatment is performed to form the n ⁻ type drain region 5 on the side surface of the first trench 8. 4C, using a normal photolithography technique, the nitride film 21 and the oxide film 20 are selectively and sequentially etched using a resist (not shown), the oxide film 22 and the oxide film 7 as mask layers. (At this time, the oxide film 22 and the oxide film 7 are slightly etched, but there is no problem.) Next, the exposed p ⁻ type silicon substrate 1 is etched by about 0.5 μm, and the second trench 9 is formed.
To form. Then, the resist (not shown) is removed.
Then, an oxide film (not shown) for ion implantation having a thickness of about 20 nm is grown. Then, using the nitride film 21, the oxide film 22, and the oxide film 7 as a mask layer, arsenic is ion-implanted to define the n ⁺ type source region 3. Next, the oxide film (not shown) for ion implantation is removed by etching. Then, a selective chemical vapor deposition tungsten silicide film is grown to form the second trench 9
To form a metal source region 10. 4D, using a normal photolithography technique, the oxide film 22 is removed by etching using the resist (not shown), the nitride film 21 and the metal source region 10 as a mask layer. Then, the resist (not shown) is removed. Then, a gate oxide film 11 of about 15 nm is grown. Then, a polycrystalline silicon film containing impurities is grown. Next, the polycrystalline silicon film is anisotropically dry-etched to form the gate electrode 12 embedded in the first trench 8. 4E, using a normal photolithography technique, a resist (not shown), a gate electrode 12, a metal source region 10 are formed.
Using the oxide film 7 as a mask layer, arsenic is ion-implanted to define the n ⁺ type drain region 4. Then, the resist (not shown) is removed. Then, the unnecessary nitride film 21 and oxide film 20 are removed by etching. Then, by applying a conventional technique, the growth of the impurity blocking oxide film 13 and the phosphosilicate glass (PSG) film 14 is performed.
The MIS field effect transistor is completed by activating the impurity diffusion region and controlling the depth by high temperature heat treatment, forming an electrode contact window, forming an Al wiring, and the like. As described in the above embodiments, according to the MIS field effect transistor of the present invention, the low-concentration impurity region can be formed in a self-aligned manner in the drain region to which a high voltage is applied.
Since the generation of hot carriers can be suppressed, the high reliability due to the improvement of the deterioration of the transfer conductance over the lifetime can be achieved by the gate region without forming the low concentration impurity region in the source region where the hot carrier effect is not related. Since the operating region can be reduced by forming the source region composed of the high-concentration impurity region and the low-resistance conductive film from an extremely high level, it is possible to improve the transfer conductance at the time of operation, thereby increasing the speed of the low-concentration impurity region formed in the drain region. The region can be formed on the side surface of the first trench that does not require a layout area on the surface, and thus high integration can be enabled. Further, when the present invention is applied to a C-MOS, high-speed and high-integration P-channel MIS field-effect transistors can coexist independently without impairing the characteristics of the high-reliability, high-speed and high-integration N-channel MIS field-effect transistor. It is also possible to construct a highly reliable, high-speed and highly integrated C-MOS. Although not shown in the embodiment, if it is used for a so-called offset type high breakdown voltage MIS field effect transistor having the same structure as that of the first embodiment and having a large size and a large film thickness, it is extremely small. It is also possible to form a high breakdown voltage MIS field effect transistor that can obtain a large breakdown voltage in the layout area.

[0007]

As described above, according to the present invention, MI
In the S field effect transistor, a low-concentration impurity region effective in suppressing hot carriers can be formed only in a necessary drain region and on the side surface of the trench below the high-concentration impurity region by self-alignment, and a source region is formed. Since it can be formed with low resistance, high reliability can be obtained by improving the deterioration of transfer conductance over life, high speed can be achieved by improving transfer conductance during operation, and high integration can be achieved without requiring a special layout area. Can be enabled. That is, it is possible to obtain a MIS field effect transistor which enables formation of a highly reliable, high speed and highly integrated semiconductor integrated circuit.

[Brief description of drawings]

FIG. 1 is a schematic side sectional view of a first embodiment of a MIS field effect transistor of the present invention.

FIG. 2 is a schematic side sectional view of a second embodiment of the MIS field effect transistor of the present invention.

FIG. 3 is a schematic side sectional view of a third embodiment of the MIS field effect transistor of the present invention.

4 (a) to 4 (e) are process cross-sectional views of an example of a method of manufacturing the MIS field effect transistor of the present invention.

[Explanation of symbols]

1 p ⁻ type silicon substrate 2 p type channel stopper region 3 n ⁺ type source region 4 n ⁺ type drain region 5 n ⁻ type drain region 6 third trench (for element isolation) 7 third trench buried insulating film 8 1 trench (for forming a buried gate) 9 second trench (for forming a buried metal source region) 10 buried metal source region (tungsten silicide) 11 gate oxide film 12 gate electrode 13 oxide film for impurity block 14 phosphosilicate glass (PSG) ) Film 15 Al wiring 16 n ⁺ type source / drain region 17 n ⁻ type source / drain region 18 n ⁻ type impurity well region 19 p ⁺ type source / drain region

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[Procedure amendment]

[Submission date] June 10, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Brief explanation of the drawing

[Correction method] Added

[Correction content]

[Brief description of drawings]

FIG. 1 is a schematic side sectional view of a first embodiment of a MIS field effect transistor of the present invention.

FIG. 2 is a schematic side sectional view of a second embodiment of the MIS field effect transistor of the present invention.

FIG. 3 is a schematic side sectional view of a third embodiment of the MIS field effect transistor of the present invention.

4 (a) to 4 (e) are process cross-sectional views of an example of a method of manufacturing the MIS field effect transistor of the present invention.

FIG. 5 is a schematic side sectional view of a conventional MIS field effect transistor.

[Explanation of Codes] 1 p ⁻ type silicon substrate 2 p type channel stopper region 3 n ⁺ type source region 4 n ⁺ type drain region 5 n ⁻ type drain region 6 third trench (for element isolation) 7 third trench Buried insulating film 8 First trench (for buried gate formation) 9 Second trench (for buried metal source region formation) 10 Buried metal source region (tungsten silicide) 11 Gate oxide film 12 Gate electrode 13 Impurity block oxide film 14 Phosphosilicate glass (PSG) film 15 Al wiring 16 n ⁺ type source / drain region 17 n ⁻ type source / drain region 18 n ⁻ type impurity well region 19 p ⁺ type source / drain region

Claims (2)

[Claims] 1. A semiconductor substrate of one conductivity type, a first trench provided in the semiconductor substrate, a gate oxide film provided on a sidewall and a bottom of the first trench, and the gate oxide film interposed therebetween. A gate electrode filling the first trench, a first high-concentration impurity region of opposite conductivity type and a first high-concentration impurity region provided on the surface of the semiconductor substrate outside one end of the gate electrode. In contact with the first
Provided on the semiconductor substrate in contact with the drain region formed of a low-concentration impurity region of opposite conductivity type provided on the semiconductor substrate on the side surface of the trench and the gate oxide film on the side wall at the other end of the gate electrode. A second trench, a second high-concentration impurity region of the opposite conductivity type provided on the semiconductor substrate on the bottom surface of the second trench, and a source region made of a conductive film filling the second trench. A MIS field effect transistor characterized by: 2. The MIS field effect transistor according to claim 1, wherein the structure of the source region is the same as the structure of the drain region.