JP2006041308A - Semiconductor apparatus - Google Patents

Semiconductor apparatus Download PDF

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JP2006041308A
JP2006041308A JP2004221160A JP2004221160A JP2006041308A JP 2006041308 A JP2006041308 A JP 2006041308A JP 2004221160 A JP2004221160 A JP 2004221160A JP 2004221160 A JP2004221160 A JP 2004221160A JP 2006041308 A JP2006041308 A JP 2006041308A
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trench
layer
semiconductor
region
semiconductor substrate
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Shinichi Jinbo
信一 神保
Naoto Fujishima
直人 藤島
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Fuji Electric Co Ltd
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Fuji Electric Device Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor apparatus capable of increasing a breakdown strength and lowering an on-resistance. <P>SOLUTION: The semiconductor apparatus is composed of P-wells 35 as p-well regions formed on a semiconductor substrate 1, a P-off 5 as a p-offset region formed on the surface layers of the P-wells 35, a trench 19 formed so as to reach the P-wells 35 from the surface of the P-off 5, and a gate electrode 21 formed on the side wall of the trench 19 through a gate oxide film 20. The semiconductor apparatus is further composed of an N-body 6 as an extended drain region formed on the bottom of the trench, an n-epitaxial layer 30 as a drain region formed towards an upper section in the trench 19 so as to be brought into contact with the N-body 6, and an n<SP>+</SP>region 8 in an upper section as a source region formed on the surface layer of the P wells 35. In the constitution, since the n-epitaxial layer 30 as the drain region is formed at a place where a tungsten layer 23 is formed, a space between the gate electrode 21 and the epitaxial layer 30 as the drain region can be widened without broadening the trench 19. Consequently, the breakdown strength can be increased and the on-resistance lowered. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

この発明は、トレンチ横型パワーＭＩＳＦＥＴなどの半導体装置に関する。   The present invention relates to a semiconductor device such as a trench lateral power MISFET.

近年、横型パワーＭＩＳＦＥＴは、低抵抗化を狙いとして様々な構造のものが開発されてきている。
図１９は、従来のトレンチ横型パワーＭＩＳＦＥＴの要部断面図である。このトレンチ横型ＭＩＳＦＥＴは特許文献１に開示されている。以下の説明ではトレンチ横型パワーＭＩＳＦＥＴをＮ−ＭＩＳＦＥＴ（Ｎはｎチャネル型のこと）と称す。
Ｎ−ＭＩＳＦＥＴ１１５は、半導体基板１０１上形成されたｐウエル領域であるＰ−ｗｅｌｌ１３５と、このＰ−ｗｅｌｌ１３５の表面層に形成したｐオフセット領域であるＰ−ｏｆｆ１０５と、Ｐ−ｏｆｆ１０５の表面からＰ−ｗｅｌｌ１３５に達するように形成したトレンチ１１９と、このトレンチ１１９の側壁にゲート酸化膜１２０を介して形成したゲート電極１２１と、トレンチ底に形成した拡張ドレイン領域であるＮ−ｂｏｄｙ１０６およびドレイン領域となる下部のｎ+ 領域１０８と、Ｐ−ｗｅｌｌ１３５の表面層に形成したソース領域となる上部のｎ+ 領域１０８と、で構成される。 In recent years, various lateral power MISFETs have been developed with the aim of reducing resistance.
FIG. 19 is a cross-sectional view of a main part of a conventional trench lateral power MISFET. This trench lateral MISFET is disclosed in Patent Document 1. In the following description, the trench lateral power MISFET is referred to as an N-MISFET (N is an n-channel type).
The N-MISFET 115 includes a P-well 135 that is a p-well region formed on the semiconductor substrate 101, a P-off 105 that is a p-off region formed on the surface layer of the P-well 135, and a P-off 105 from the surface of the P-off 105. A trench 119 formed so as to reach the well 135, a gate electrode 121 formed on the side wall of the trench 119 via a gate oxide film 120, an N-body 106 that is an extended drain region formed at the bottom of the trench, and a lower portion that becomes a drain region N + region 108 and an upper n + region 108 serving as a source region formed in the surface layer of P-well 135.

尚、図中の１１３は選択酸化膜、１２２はＣＶＤ（Ｃｈｅｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ）で形成する酸化膜、１２３はタングステン膜（プラグ）、１２４はアルミ−シリコン−銅の合金からなる金属電極である。
このＮ−ＭＩＳＦＥＴ１１５は、チャネル領域（上部のｎ+ 層とＮ−ｂｏｄｙ１０６に挟まれたＰ−ｏｆｆ１０５とＰ−ｗｅｌｌ１３５）とドリフト領域となるＮ−ｂｏｄｙ１０６が垂直方向に形成され、セル数を増やせるために、図２０で示す従来のプレーナ横型パワーＭＩＳＦＥＴ１１４よりもオン抵抗を低減できる特長がある。
尚、図２０の中で、１０４はＮ−ｗｅｌｌ、１０９はｐ+ 領域、１１１は裏面電極である。
図１９のＮ−ＭＩＳＦＥＴ１１５では、ゲート酸化膜１２０の膜厚が２０ｎｍ程度の場合、ドレイン−ソース間に電圧を印加していくと、図中の○印で示したゲート電極近傍の拡張ドレイン領域（Ｎ−ｂｏｄｙ１０６）内に電界が最も高くなる箇所が発生し、その箇所でアバランシェ電流が流れ始める。また、ドレイン−ソース間にサージ電圧が印加されたときに、ゲート近傍が高電界になり、低いサージ電圧（ＥＳＤ電圧など）で破壊する。例えば、Ｎ−ＭＩＳＦＥＴの面積が２００μｍ2 程度の場合には、５ｋＶ程度と低いサージ耐量（ＥＳＤ耐量）となる。 In the figure, 113 is a selective oxide film, 122 is an oxide film formed by CVD (Chemical Vapor Deposition), 123 is a tungsten film (plug), and 124 is a metal electrode made of an aluminum-silicon-copper alloy.
In this N-MISFET 115, the channel region (P-off 105 and P-well 135 sandwiched between the upper n + layer and N-body 106) and the N-body 106 serving as a drift region are formed in the vertical direction to increase the number of cells. In addition, the on-resistance can be reduced as compared with the conventional planar lateral power MISFET 114 shown in FIG.
In FIG. 20, 104 is an N-well, 109 is a p + region, and 111 is a back electrode.
In the N-MISFET 115 of FIG. 19, when the gate oxide film 120 has a thickness of about 20 nm, when a voltage is applied between the drain and source, an extended drain region (in the vicinity of the gate electrode indicated by a circle in the figure) ( A portion where the electric field is highest is generated in the N-body 106), and an avalanche current begins to flow there. In addition, when a surge voltage is applied between the drain and source, the vicinity of the gate becomes a high electric field, and the device is destroyed by a low surge voltage (ESD voltage or the like). For example, when the area of the N-MISFET is about 200 μm 2 , the surge resistance (ESD resistance) is as low as about 5 kV.

また、このＮ−ＭＩＳＦＥＴ１１５の電気的特性は、トレンチ深さ２μｍ、トレンチ幅３μｍ程度の構造では、耐圧が２０Ｖ程度、ＲｏｎＡが２０ｍΩｍｍ2 程度である。このように図１９の従来のトレンチ横型ＭＩＳＦＥＴでは高耐圧化は困難である。
さらに高耐圧化を必要とする場合は、ドレイン領域となる下部のｎ+ 領域１０８をゲート電極１２１から離して電界を緩和する方法がある。
図２１は下部のｎ+ 領域１０８の寸法を小さくする方法であり、図２２はトレンチ幅を広げる方法である。
また、電界を緩和するために、特許文献２に開示されている図２３は、トレンチ底に選択酸化膜１４０を形成する方法である。
特開平８−１８１３１３号公報 特開２００３−２４９６５０号公報 The electrical characteristics of the N-MISFET 115 are a breakdown voltage of about 20 V and a RonA of about 20 mΩmm 2 in a structure having a trench depth of about 2 μm and a trench width of about 3 μm. Thus, it is difficult to increase the breakdown voltage in the conventional trench lateral MISFET of FIG.
When a higher breakdown voltage is required, there is a method of relaxing the electric field by separating the lower n + region 108 serving as the drain region from the gate electrode 121.
21 shows a method of reducing the size of the lower n + region 108, and FIG. 22 shows a method of increasing the trench width.
In order to alleviate the electric field, FIG. 23 disclosed in Patent Document 2 is a method of forming a selective oxide film 140 at the bottom of the trench.
JP-A-8-181313 JP 2003-249650 A

しかし、図２１の方法では下部のｎ+ 領域１０８の寸法は、もともと低オン抵抗を狙いとして小さく設計されており、そのため高耐圧化には限界がある。
図２２の方法ではトレンチ幅を広げて高耐圧化を図ることは容易であるが、低オン抵抗化が困難になる。
図２３の方法ではトレンチ底に選択酸化膜１４０を形成するが、トレンチ底で選択酸化のマスクになる例えば窒化膜のパターンを形成することがプロセス上困難という問題がある。
この発明の目的は、前記の課題を解決して、高耐圧化と低オン抵抗化を図ることができる半導体装置を提供することにある。 However, in the method of FIG. 21, the size of the lower n + region 108 is originally designed to be small with the aim of low on-resistance, and therefore there is a limit to increasing the breakdown voltage.
In the method of FIG. 22, it is easy to increase the breakdown voltage by widening the trench width, but it is difficult to reduce the on-resistance.
In the method of FIG. 23, the selective oxide film 140 is formed at the bottom of the trench. However, there is a problem in that it is difficult to form a nitride film pattern, for example, which serves as a selective oxidation mask at the bottom of the trench.
An object of the present invention is to provide a semiconductor device capable of solving the above-described problems and achieving high breakdown voltage and low on-resistance.

前記の目的を達成するために、第１導電型の半導体基板と、前記半導体基板の表面から内部に向けて形成されたトレンチと、前記半導体基板表面に形成された第２導電型のソース領域と、前記トレンチ内にゲート絶縁膜を介して形成されたゲート電極と、前記トレンチ内に形成された第２導電型の半導体層からなるドレイン領域とを有する構成とする。
また、前記半導体層に接して、前記トレンチの底から側壁に渡って前記半導体基板に形成された第２導電型の半導体領域を有するとよい。
また、第１導電型の半導体基板と、前記半導体基板上に形成された第１導電型の第１のエピタキシャル層と、該第１のエピタキシャル層の表面から内部に向けて形成されたトレンチと、前記第１のエピタキシャル層表面に形成された第２導電型のソース領域と、前記トレンチ内にゲート絶縁膜を介して形成されたゲート電極と、前記トレンチ内に形成された第２導電型の半導体層からなるドレイン領域と、前記トレンチの底から側壁に渡って前記第１のエピタキシャル層に形成され、前記半導体基板と接する第２導電型の半導体領域とを有する構成とする。 To achieve the above object, a first conductivity type semiconductor substrate, a trench formed inward from the surface of the semiconductor substrate, a second conductivity type source region formed on the surface of the semiconductor substrate, And a gate electrode formed in the trench through a gate insulating film, and a drain region made of a second conductivity type semiconductor layer formed in the trench.
In addition, the semiconductor layer may have a second conductivity type semiconductor region formed on the semiconductor substrate from the bottom to the side wall of the trench in contact with the semiconductor layer.
A first conductivity type semiconductor substrate; a first conductivity type first epitaxial layer formed on the semiconductor substrate; a trench formed from the surface of the first epitaxial layer toward the inside; A second conductivity type source region formed on the surface of the first epitaxial layer, a gate electrode formed in the trench through a gate insulating film, and a second conductivity type semiconductor formed in the trench A drain region composed of a layer and a semiconductor region of a second conductivity type formed in the first epitaxial layer from the bottom to the side wall of the trench and in contact with the semiconductor substrate.

また、前記半導体層が第２のエピタキシャル層もしくはポリシリコン層であるとよい。 また、前記半導体層が、前記トレンチ内に形成されたドレイン電極と電気的に接触するとよい。
また、前記ドレイン領域と前記ソース領域の間の耐圧が、前記半導体領域と前記半導体基板との間に形成された前記トレンチ直下のｐｎ接合のアバランシェ降伏によって決定されるとよい。
また、前記第１のエピタキシャル層と前記半導体基板の間に、第２導電型の埋め込み層が形成されているとよい。
また、前記ドレイン領域と前記ソース領域の間の耐圧が、前記埋め込み層と前記半導体基板との間に形成されたｐｎ接合のアバランシェ降伏によって決定されるとよい。 The semiconductor layer may be a second epitaxial layer or a polysilicon layer. The semiconductor layer may be in electrical contact with a drain electrode formed in the trench.
The breakdown voltage between the drain region and the source region may be determined by an avalanche breakdown of a pn junction formed immediately below the trench formed between the semiconductor region and the semiconductor substrate.
Further, a second conductivity type buried layer may be formed between the first epitaxial layer and the semiconductor substrate.
The breakdown voltage between the drain region and the source region may be determined by an avalanche breakdown of a pn junction formed between the buried layer and the semiconductor substrate.

また、前記トレンチの平面形状が、ループ状であるとよい。   The planar shape of the trench may be a loop shape.

この発明によれば、トレンチ横型パワーＭＩＳＦＥＴの高濃度のドレイン領域をトレンチ内のエピタキシャル層に形成することによって、トレンチ幅を広げることなく、従来よりもゲート電極と高濃度のドレイン領域との距離を大きくできるため、ドレイン−ソース間に電圧をかけたときのゲート電極下の電界を緩和することができて、高耐圧化することができる。
また、トレンチ幅を広げないので、低オン抵抗を維持できる。つまり、高耐圧化と低オン抵抗化を実現できる。
さらに、ＭＩＳＦＥＴの拡張ドレイン領域であるトレンチ底の拡散領域（Ｎ−ｂｏｄｙ６）が半導体基板と接して形成されるｐｎ接合でアバランシェ降伏するように設計する（ｐｎ接合の耐圧が、ＭＩＳＦＥＴの耐圧を決定するように各領域の濃度を調整する）ことによって、アバランシェ電流を半導体基板に向けて流すことができるため、サージ破壊耐量を向上させることができる。 According to the present invention, by forming the high concentration drain region of the trench lateral power MISFET in the epitaxial layer in the trench, the distance between the gate electrode and the high concentration drain region can be made larger than before without increasing the trench width. Since it can be increased, the electric field under the gate electrode when a voltage is applied between the drain and the source can be relaxed, and a high breakdown voltage can be achieved.
Further, since the trench width is not increased, a low on-resistance can be maintained. That is, high breakdown voltage and low on-resistance can be realized.
Furthermore, the diffusion region (N-body 6) at the bottom of the trench, which is the extended drain region of the MISFET, is designed to avalanche breakdown at the pn junction formed in contact with the semiconductor substrate (the breakdown voltage of the pn junction determines the breakdown voltage of the MISFET). By adjusting the concentration of each region so that the avalanche current can flow toward the semiconductor substrate, surge breakdown resistance can be improved.

また、トレンチの平面形状を切れ目なくループ状に繋がった形状にすることによって、電界が集中しやすいトレンチ端部がなくなり、高耐圧化、高サージ耐量化を実現することができる。   Further, by making the planar shape of the trench connected in a loop shape without a break, there is no end of the trench where the electric field tends to concentrate, and high breakdown voltage and high surge resistance can be realized.

実施するための最良の形態は、トレンチ横型パワーＭＩＳＦＥＴのゲート電極とドレイン領域の間隔を広くして、ゲート電極近傍のＮ−ｂｏｄｙ内に発生する高電界を緩和することである。本来プラグが形成される箇所にドレイン領域を形成することで、トレンチの幅を広げることをせずに、ゲート電極とドレイン領域の間隔を広げた点である。こうすることで、高耐圧化と低オン抵抗化を実現する。以下に本発明の実施例を図を用いて説明する。   The best mode for carrying out is to widen the distance between the gate electrode and the drain region of the trench lateral power MISFET to alleviate the high electric field generated in the N-body near the gate electrode. By forming the drain region where the plug is originally formed, the gap between the gate electrode and the drain region is increased without increasing the width of the trench. In this way, high breakdown voltage and low on-resistance are realized. Embodiments of the present invention will be described below with reference to the drawings.

図１は、この発明の第１実施例の半導体装置の要部断面図である。本実施例は前記の特許文献１において開示される、トレンチ横型パワーＭＩＳＦＥＴの構造を高耐圧化のために改良したものである。
Ｎ−ＭＩＳＦＥＴ１５は、半導体基板１上に形成されたｐウエル領域であるＰ−ｗｅｌｌ３５と、このＰ−ｗｅｌｌ３５の表面層に形成されるｐオフセット領域であるＰ−ｏｆｆ５と、Ｐ−ｏｆｆ５の表面からＰ−ｗｅｌｌ３５に達するように形成したトレンチ１９と、このトレンチ１９の側壁にゲート酸化膜２０を介して形成したゲート電極２１と、トレンチ底に形成した拡張ドレイン領域である拡張ドレイン領域であるＮ−ｂｏｄｙ６と、このＮ−ｂｏｄｙ６と接するようにトレンチ１９内部上方に向かって形成されたドレイン領域となるｎエピタキシャル層３０と、Ｐ−ｗｅｌｌ３５の表面層に形成したソース領域となる上部のｎ+ 領域８と、で構成される。 FIG. 1 is a cross-sectional view of a main part of a semiconductor device according to a first embodiment of the present invention. In the present embodiment, the structure of the trench lateral power MISFET disclosed in the above-mentioned Patent Document 1 is improved in order to increase the breakdown voltage.
The N-MISFET 15 includes a P-well 35 that is a p-well region formed on the semiconductor substrate 1, a P-off 5 that is a p-offset region formed on the surface layer of the P-well 35, and a surface of the P-off 5. A trench 19 formed to reach the P-well 35, a gate electrode 21 formed on the side wall of the trench 19 via a gate oxide film 20, and an N− which is an extended drain region which is an extended drain region formed at the bottom of the trench body 6, an n epitaxial layer 30 serving as a drain region formed in contact with the N-body 6 toward the inside of the trench 19, and an upper n + region 8 serving as a source region formed in the surface layer of the P-well 35. And.

尚、図中の１３は選択酸化膜、２２はＣＶＤで形成する酸化膜、２３はタングステン層（プラグ）、２４はアルミ−シリコン−銅の合金からなる金属電極である。
本実施例において、図１９との違いは、ドレイン領域となる下部のｎ+ 領域１０８の代わりに、トレンチ１９の底からトレンチ内部上方に向かって厚さ０．３μｍ程度のｎエピタキシャル層３０をドレイン領域として形成した点である。ｎエピタキシャル層３０は、金属配線との境界近くでは不純物濃度を高めてオーミック接触が取れるようにする。図示したタングステン層２３は電極の埋め込み層であるプラグであり、エピタキシャル層３０との界面には図示していないＴｉ／ＴｉＮのバリアメタル層が存在する。前記したゲート電極は、高濃度のｎ型不純物をドープしたポリシリコンで形成される。
この構造では、従来例の図１９で示したように、ゲート電極とドレイン領域の間隔が狭いために、ゲート電極近傍のＮ−ｂｏｄｙ１０６内に発生する高電界を、ゲート電極とドレイン領域の間隔を広くすることで、緩和させることができて、高電圧化を図ることが容易になる。また、本来、タングステン層２３を形成する箇所にドレイン領域となるｎエピタキシャル層３０を形成するために、トレンチ１９を広げることなく、ゲート電極とドレイン領域の間隔を広げることができるために、トレンチを広げる場合に比べて低オン抵抗化を図ることができる。 In the figure, 13 is a selective oxide film, 22 is an oxide film formed by CVD, 23 is a tungsten layer (plug), and 24 is a metal electrode made of an aluminum-silicon-copper alloy.
In this embodiment, the difference from FIG. 19 is that the n epitaxial layer 30 having a thickness of about 0.3 μm is drained from the bottom of the trench 19 toward the upper part inside the trench instead of the lower n + region 108 serving as the drain region. This is a point formed as a region. The n epitaxial layer 30 increases the impurity concentration near the boundary with the metal wiring so that ohmic contact can be obtained. The illustrated tungsten layer 23 is a plug which is a buried layer of an electrode, and a Ti / TiN barrier metal layer (not shown) exists at the interface with the epitaxial layer 30. The gate electrode is formed of polysilicon doped with a high concentration of n-type impurities.
In this structure, as shown in FIG. 19 of the conventional example, since the distance between the gate electrode and the drain region is narrow, a high electric field generated in the N-body 106 near the gate electrode is generated. By making it wide, it can be relaxed and it becomes easy to achieve a high voltage. In addition, in order to form the n epitaxial layer 30 serving as the drain region at the place where the tungsten layer 23 is originally formed, the gap between the gate electrode and the drain region can be increased without increasing the trench 19, so that the trench is formed. The on-resistance can be reduced as compared with the case of widening.

例えば、トレンチ深さ１．５μｍ、トレンチ幅３μｍの構造で、耐圧３０Ｖ程度、ＲｏｎＡが２０ｍΩｍｍ2 程度のＮ−ＭＩＳＦＥＴを実現することができる。また、図２３のようにトレンチ底に選択酸化膜を形成する従来の方法に比べ、エピタキシャル成長技術を利用することで比較的容易に形成できる。
図２は、図１の半導体装置のトレンチ形状の要部平面図である。トレンチが、切れ目なく連続的に形成されていることが特徴で、電界集中が起き易いトレンチ終端部がないため、電流集中が起きにくい。
図３から図１４は、図１の半導体装置の製造方法を示す図であり、工程順に示した要部製造工程断面図である。
半導体基板１としては、例えばｐ型不純物（例えばボロン）濃度が２×１０15ｃｍ-3程度の基板を用いる（図３）。 For example, an N-MISFET having a trench depth of 1.5 μm and a trench width of 3 μm, a breakdown voltage of about 30 V, and RonA of about 20 mΩmm 2 can be realized. Further, as compared with the conventional method of forming a selective oxide film on the trench bottom as shown in FIG. 23, it can be formed relatively easily by using an epitaxial growth technique.
2 is a plan view of the main part of the trench shape of the semiconductor device of FIG. A feature of the trench is that it is continuously formed without a break, and since there is no trench termination portion where electric field concentration tends to occur, current concentration hardly occurs.
3 to 14 are views showing a method of manufacturing the semiconductor device of FIG. 1, and are cross-sectional views of main part manufacturing steps shown in the order of steps.
As the semiconductor substrate 1, for example, a substrate having a p-type impurity (for example, boron) concentration of about 2 × 10 15 cm −3 is used (FIG. 3).

ドーズ量５×１０12ｃｍ-2程度のボロンのイオン注入をＮ−ＭＩＳＦＥＴ１５形成部に行い、１１５０℃４時間程度のドライブによりＰ−ｗｅｌｌ３５を形成し、続いて、ドーズ量１×１０13ｃｍ-2程度のボロンのイオン注入をＮ−ＭＩＳＦＥＴ１５形成部に行い、１１５０℃１時間程度のドライブを行なってＰ−ｏｆｆ５を形成する（図４）。
つぎに、深さ１．５μｍ程度のトレンチ１９を形成する（図５）。
つぎに、トレンチ１９底部にドーズ量２×１０13ｃｍ-2程度のリン（Ｐ）のイオン注入を行い、１１５０℃１時間程度のドライブを行なって、Ｎ−ｂｏｄｙ６を形成する（図６）。ここで、Ｐ−ｏｆｆ５とＮ−ｂｏｄｙ６を形成するドライブは同時に行っても構わない。
つぎに、ウエハ表面に選択酸化膜１３を成長させる（図７）。 Boron ion implantation with a dose of about 5 × 10 12 cm −2 is performed on the N-MISFET 15 forming portion to form P-well 35 by driving at 1150 ° C. for about 4 hours, followed by a dose of 1 × 10 13 cm −. Boron ion implantation of about 2 is performed in the N-MISFET 15 forming portion, and driving is performed at 1150 ° C. for about 1 hour to form P-off 5 (FIG. 4).
Next, a trench 19 having a depth of about 1.5 μm is formed (FIG. 5).
Next, phosphorus (P) is implanted into the bottom of the trench 19 with a dose of about 2 × 10 13 cm −2 and driven at 1150 ° C. for about 1 hour to form N-body 6 (FIG. 6). Here, the drive forming P-off 5 and N-body 6 may be performed simultaneously.
Next, a selective oxide film 13 is grown on the wafer surface (FIG. 7).

つぎに、ゲート酸化膜２０を形成し、その上に高濃度のｎ型不純物をドープしたポリシリコン２１を０．３μｍ成長する（図８）。
つぎに、ポリシリコンを異方性エッチングによりトレンチの側壁だけに残し、これをＮ−ＭＩＳＦＥＴ１５のゲート電極２１とする（図９）。
つぎに、Ｐ−ｏｆｆ５の表面層にｎ型不純物（例えば砒素）をドーズ量３×１０15ｃｍ-2の条件でイオン注入し、９００℃３０分程度のアニール処理を行い、ソース領域となる上部のｎ+ 領域８を形成する（図１０）。
つぎに、層間絶縁膜としてＢＰＳＧなどのＣＶＤ成長による酸化膜２２を形成した後、ウエハ表面をＣＭＰで平坦化する（図１１）。
つぎに、酸化膜２２をエッチングしてまずトレンチ底のコンタクト部を開口する（図１２）。 Next, a gate oxide film 20 is formed, and a polysilicon 21 doped with high-concentration n-type impurities is grown thereon by 0.3 μm (FIG. 8).
Next, the polysilicon is left only on the sidewall of the trench by anisotropic etching, and this is used as the gate electrode 21 of the N-MISFET 15 (FIG. 9).
Next, an n-type impurity (for example, arsenic) is ion-implanted into the surface layer of P-off 5 under the condition of a dose amount of 3 × 10 15 cm −2 , and an annealing process is performed at 900 ° C. for about 30 minutes to form an upper portion that becomes a source region N + region 8 is formed (FIG. 10).
Next, after forming an oxide film 22 by CVD growth such as BPSG as an interlayer insulating film, the wafer surface is planarized by CMP (FIG. 11).
Next, the oxide film 22 is etched to first open the contact portion at the bottom of the trench (FIG. 12).

つぎに、ｎエピタキシャル層３０を開口したコンタクト部に成長させてドレイン領域を形成する。このとき、ドレイン領域がドレイン電極となるタングステン層２３とオーミック接触するようにｎエピタキシャル層３０の表面層の濃度を高濃度とする（図１３）。
つぎに、ウエハ表面の上部のｎ+ 領域８上の酸化膜２２をエッチングで開口したのち、ｎエピタキシャル層３０上と上部のｎ+ 領域８上に図示しないＴｉ／ＴｉＮをスパッタで成膜したのち、タングステン層２３を埋め込み、その上にアルミ−シリコン−銅の合金でソース電極、ドレイン電極となる金属電極２４を形成してＮ−ＭＩＳＦＥＴ１５が完成する。このようにすることで、製造方法が比較的容易で高耐圧、低オン抵抗の半導体装置を製造することができる。
尚、前記のエピタキシャル層３０の代わりにポリシリコン層を形成しても構わない。また、このポリシリコン層をアニール処理して単結晶層としてもよい。 Next, the n epitaxial layer 30 is grown in the opened contact portion to form a drain region. At this time, the concentration of the surface layer of the n epitaxial layer 30 is set high so that the drain region is in ohmic contact with the tungsten layer 23 serving as the drain electrode (FIG. 13).
Next, the oxide film 22 on the n + region 8 on the upper surface of the wafer is opened by etching, and Ti / TiN (not shown) is formed on the n epitaxial layer 30 and the upper n + region 8 by sputtering. Then, the tungsten layer 23 is buried, and a metal electrode 24 serving as a source electrode and a drain electrode is formed thereon with an aluminum-silicon-copper alloy, thereby completing the N-MISFET 15. In this way, a semiconductor device with a relatively easy manufacturing method and high breakdown voltage and low on-resistance can be manufactured.
A polysilicon layer may be formed instead of the epitaxial layer 30. The polysilicon layer may be annealed to form a single crystal layer.

図１５は、この発明の第２実施例の半導体装置の要部断面図である。実施例２は、実施例１の構造をＰ−ＭＩＳＦＥＴ１６（ｐチャネル型のトレンチ横型パワーＭＩＳＦＥＴ）に適用したものである。
実施例１のＰ−ｗｅｌｌ３５、Ｎ−ｂｏｄｙ６、Ｐ−ｏｆｆ５、ソースｎ+ 領域８、ｎエピタキシャル層３０をそれぞれ、Ｎ−ｗｅｌｌ４、Ｐ−ｂｏｄｙ１１、Ｎ−ｏｆｆ１０、ｐ+ 領域９、ｐエピタキシャル層３２に置き換えるとＰ−ＭＩＳＦＥＴ１６になる。 FIG. 15 is a fragmentary cross-sectional view of the semiconductor device according to the second embodiment of the present invention. In Example 2, the structure of Example 1 is applied to a P-MISFET 16 (p-channel type trench lateral power MISFET).
The P-well 35, N-body 6, P-off 5, source n + region 8, and n epitaxial layer 30 of Example 1 are replaced with N-well 4, P-body 11, N-off 10, p + region 9, and p epitaxial layer 32, respectively. Is replaced with P-MISFET16.

図１６は、この発明の第３実施例の半導体装置の要部断面図である。実施例１の半導体装置とは基板構造が異なる。すなわち実施例３では、半導体基板１上に、ｐエピタキシャル層３を積んだ構造とし、半導体基板１の濃度を例えば１×１０19ｃｍ-3と高濃度にし、ｐエピタキシャル層３の濃度を例えば１×１０16ｃｍ-3とする。
また、図１６に示すようにウエハ裏面電極の電位をＮ−ＭＩＳＦＥＴ１７のソース電極（上部のｎ+ 領域８上の金属電極２４）およびｐエピタキシャル層３と共通の最低電位（ＧＮＤ）にする。トレンチ底のＮ−ｂｏｄｙ６は半導体基板１と接するようにし、Ｎ−ＭＩＳＦＥＴ１７の耐圧が、上記半導体基板１とＮ−ｂｏｄｙ６との間に形成されるｐｎ接合で決定されるようにする。つまり、アバランシェ降伏を半導体基板１とＮ−ｂｏｄｙ６のｐｎ接合で起こるようにする。 FIG. 16 is a fragmentary cross-sectional view of the semiconductor device according to the third embodiment of the present invention. The substrate structure is different from the semiconductor device of the first embodiment. That is, in Example 3, a structure in which the p epitaxial layer 3 is stacked on the semiconductor substrate 1, the concentration of the semiconductor substrate 1 is set to a high concentration of 1 × 10 19 cm −3 , for example, and the concentration of the p epitaxial layer 3 is set to, for example, 1 × 10 16 cm -3
Further, as shown in FIG. 16, the potential of the wafer back electrode is set to the lowest potential (GND) common to the source electrode (the metal electrode 24 on the upper n + region 8) and the p epitaxial layer 3 of the N-MISFET 17. The N-body 6 at the bottom of the trench is in contact with the semiconductor substrate 1 so that the breakdown voltage of the N-MISFET 17 is determined by a pn junction formed between the semiconductor substrate 1 and the N-body 6. That is, the avalanche breakdown is caused to occur at the pn junction between the semiconductor substrate 1 and N-body 6.

これによって、Ｎ−ＭＩＳＦＥＴ１７のドレイン−ソース間にサージ電圧がかかる場合に縦方向のダイオード３８に電流を流すことでＮ−ＭＩＳＦＥＴ１７の破壊耐量を向上させることができる。
例として、従来構造で５ｋＶ程度であったサージ耐量を倍程度に向上させることが可能である。 As a result, when a surge voltage is applied between the drain and source of the N-MISFET 17, the breakdown resistance of the N-MISFET 17 can be improved by passing a current through the vertical diode 38.
As an example, it is possible to improve the surge resistance, which was about 5 kV in the conventional structure, to about twice.

図１７は、この発明の第４実施例の半導体装置の要部断面図である。実施例３とは、ｎ埋め込み層３７が半導体基板１とｐエピタキシャル層３の間に設けられている点が異なる。縦方向のダイオード３９は実施例３のダイオードよりもｐｎ接合面積が大きいため、Ｎ−ＭＩＳＦＥＴ１８のドレイン−ソース間のサージ電圧に対する破壊耐量をＮ−ＭＩＳＦＥＴ１７よりも高くすることができる。   FIG. 17 is a sectional view showing the principal part of a semiconductor device according to the fourth embodiment of the present invention. The third embodiment is different from the third embodiment in that an n buried layer 37 is provided between the semiconductor substrate 1 and the p epitaxial layer 3. Since the vertical diode 39 has a larger pn junction area than the diode of the third embodiment, the breakdown resistance against the surge voltage between the drain and source of the N-MISFET 18 can be made higher than that of the N-MISFET 17.

図１８は、この発明の第５実施例の半導体装置の要部断面図である。この実施例は、Ｎ−ＭＩＳＦＥＴ４０がＳＯＩ基板に形成された場合に、部分ＳＯＩ基板を用いて縦型ダイオード４１を形成したものである。これは、埋め込まれた酸化膜４２が部分的に開口され（部分ＳＯＩ基板）、その開口部にＮ−ｂｏｄｙ６の下部を形成し、半導体基板１と接続することで縦型ダイオード４１を形成することができる。この場合も第１実施例と同様の効果が得られる。   FIG. 18 is a fragmentary cross-sectional view of the semiconductor device according to the fifth embodiment of the present invention. In this embodiment, when the N-MISFET 40 is formed on an SOI substrate, a vertical diode 41 is formed using a partial SOI substrate. This is because the buried oxide film 42 is partially opened (partial SOI substrate), the lower portion of the N-body 6 is formed in the opening, and the vertical diode 41 is formed by connecting to the semiconductor substrate 1. Can do. In this case, the same effect as that of the first embodiment can be obtained.

この発明の第１実施例の半導体装置の要部断面図Sectional drawing of the principal part of the semiconductor device of 1st Example of this invention. 図１の半導体装置のトレンチ形状の要部平面図1 is a plan view of the main part of the trench shape of the semiconductor device of FIG. 図１の半導体装置の要部製造工程断面図FIG. 1 is a cross-sectional view of the main part manufacturing process of the semiconductor device of FIG. 図３に続く、図１の半導体装置の要部製造工程断面図FIG. 3 is a cross-sectional view of the main part manufacturing process of the semiconductor device of FIG. 図４に続く、図１の半導体装置の要部製造工程断面図FIG. 4 is a cross-sectional view of the main part manufacturing process of the semiconductor device of FIG. 図５に続く、図１の半導体装置の要部製造工程断面図FIG. 5 is a cross-sectional view of the main part manufacturing process of the semiconductor device of FIG. 図６に続く、図１の半導体装置の要部製造工程断面図FIG. 6 is a cross-sectional view of the main part manufacturing process of the semiconductor device of FIG. 図７に続く、図１の半導体装置の要部製造工程断面図FIG. 7 is a cross-sectional view of the main part manufacturing process of the semiconductor device of FIG. 図８に続く、図１の半導体装置の要部製造工程断面図FIG. 8 is a cross-sectional view of the main part manufacturing process of the semiconductor device of FIG. 図９に続く、図１の半導体装置の要部製造工程断面図FIG. 9 is a cross-sectional view of the main part manufacturing process of the semiconductor device of FIG. 図１０に続く、図１の半導体装置の要部製造工程断面図FIG. 10 is a cross-sectional view of the main part manufacturing process of the semiconductor device of FIG. 図１１に続く、図１の半導体装置の要部製造工程断面図FIG. 11 is a cross-sectional view of the main part manufacturing process of the semiconductor device of FIG. 図１２に続く、図１の半導体装置の要部製造工程断面図FIG. 12 is a cross-sectional view of the main part manufacturing process of the semiconductor device of FIG. 図１３に続く、図１の半導体装置の要部製造工程断面図FIG. 13 is a cross-sectional view of the essential part manufacturing process of the semiconductor device of FIG. この発明の第２実施例の半導体装置の要部断面図Sectional drawing of the principal part of the semiconductor device of 2nd Example of this invention この発明の第３実施例の半導体装置の要部断面図Sectional drawing of the principal part of the semiconductor device of 3rd Example of this invention. この発明の第４実施例の半導体装置の要部断面図Sectional drawing of the principal part of the semiconductor device of 4th Example of this invention. この発明の第５実施例の半導体装置の要部断面図Sectional drawing of the principal part of the semiconductor device of 5th Example of this invention 従来のトレンチ横型パワーＭＩＳＦＥＴの要部断面図Sectional view of the main part of a conventional trench lateral power MISFET 従来のプレーナ横型パワーＭＩＳＦＥＴの要部断面図Sectional view of the main part of a conventional planar lateral power MISFET 従来の別のトレンチ横型パワーＭＩＳＦＥＴの要部断面図Sectional view of the main part of another conventional trench lateral power MISFET 従来の別のトレンチ横型パワーＭＩＳＦＥＴの要部断面図Sectional view of the main part of another conventional trench lateral power MISFET 従来の別のトレンチ横型パワーＭＩＳＦＥＴの要部断面図Sectional view of the main part of another conventional trench lateral power MISFET

符号の説明Explanation of symbols

１ 半導体基板（ｐ型）
３ ｐエピタキシャル層
４ Ｎ−ｗｅｌｌ（ｎウエル領域）
５ Ｐ−ｏｆｆ（ｐオフセット領域）
６ Ｎ−ｂｏｄｙ（拡張ドレイン領域）
８ ｎ+ 領域（ｎソース領域）
１０ Ｎ−ｏｆｆ（ｎオフセット領域）
１３ 選択酸化膜
１５、１７、１８、４０ Ｎ−ＭＩＳＦＥＴ（ｎチャネル型ＭＩＳＦＥＴ）
１６ Ｐ−ＭＩＳＦＥＴ（ｐチャネル型ＭＩＳＦＥＴ）
１９ トレンチ
２０ ゲート酸化膜
２１ ポリシリコン
２２ 酸化膜
２３ タングステン層（プラグ）
２４ 金属電極
２５ 裏面電極
３０ ｎエピタキシャル層（ｎドレイン領域）
３２ ｐエピタキシャル層
３５ Ｐ−ｗｅｌｌ（ｐウエル領域）
３７ ｎ埋め込み層
３８、３９、４１ 縦型ダイオード
４２ 埋め込み酸化膜 1 Semiconductor substrate (p-type)
3 p epitaxial layer 4 N-well (n-well region)
5 P-off (p offset region)
6 N-body (extended drain region)
8 n + region (n source region)
10 N-off (n offset region)
13 Selective oxide films 15, 17, 18, 40 N-MISFET (n-channel MISFET)
16 P-MISFET (p-channel MISFET)
19 trench 20 gate oxide film 21 polysilicon 22 oxide film 23 tungsten layer (plug)
24 Metal electrode 25 Back electrode 30 n Epitaxial layer (n drain region)
32 p epitaxial layer 35 P-well (p well region)
37 n buried layer 38, 39, 41 Vertical diode 42 buried oxide film

Claims (9)

第１導電型の半導体基板と、前記半導体基板の表面から内部に向けて形成されたトレンチと、前記半導体基板表面に形成された第２導電型のソース領域と、前記トレンチ内にゲート絶縁膜を介して形成されたゲート電極と、前記トレンチ内に形成された第２導電型の半導体層からなるドレイン領域とを有することを特徴とする半導体装置。 A first conductivity type semiconductor substrate; a trench formed from the surface of the semiconductor substrate toward the inside; a second conductivity type source region formed on the surface of the semiconductor substrate; and a gate insulating film in the trench. And a drain region made of a second conductivity type semiconductor layer formed in the trench. 前記半導体層に接して、前記トレンチの底から側壁に渡って前記半導体基板に形成された第２導電型の半導体領域を有することを特徴とする請求項１に記載の半導体装置。 2. The semiconductor device according to claim 1, further comprising a second conductivity type semiconductor region formed on the semiconductor substrate in contact with the semiconductor layer from the bottom to the side wall of the trench. 第１導電型の半導体基板と、前記半導体基板上に形成された第１導電型の第１のエピタキシャル層と、該第１のエピタキシャル層の表面から内部に向けて形成されたトレンチと、前記第１のエピタキシャル層表面に形成された第２導電型のソース領域と、前記トレンチ内にゲート絶縁膜を介して形成されたゲート電極と、前記トレンチ内に形成された第２導電型の半導体層からなるドレイン領域と、前記トレンチの底から側壁に渡って前記第１のエピタキシャル層に形成され、前記半導体基板と接する第２導電型の半導体領域とを有することを特徴とする半導体装置。 A first conductivity type semiconductor substrate; a first conductivity type first epitaxial layer formed on the semiconductor substrate; a trench formed from the surface of the first epitaxial layer toward the inside; A source region of a second conductivity type formed on the surface of one epitaxial layer, a gate electrode formed in the trench via a gate insulating film, and a semiconductor layer of the second conductivity type formed in the trench And a second conductivity type semiconductor region formed in the first epitaxial layer from the bottom to the side wall of the trench and in contact with the semiconductor substrate. 前記半導体層が第２のエピタキシャル層もしくはポリシリコン層であることを特徴とする請求項１〜３のいずれか一項に記載の半導体装置。 The semiconductor device according to claim 1, wherein the semiconductor layer is a second epitaxial layer or a polysilicon layer. 前記半導体層が、前記トレンチ内に形成されたドレイン電極と電気的に接触することを特徴とする請求項１〜４のいずれか一項に記載の半導体装置。 The semiconductor device according to claim 1, wherein the semiconductor layer is in electrical contact with a drain electrode formed in the trench. 前記ドレイン領域と前記ソース領域の間の耐圧が、前記半導体領域と前記半導体基板との間に形成された前記トレンチ直下のｐｎ接合のアバランシェ降伏によって決定されることを特徴とする請求項２または３に記載の半導体装置。 4. The breakdown voltage between the drain region and the source region is determined by an avalanche breakdown of a pn junction formed immediately below the trench formed between the semiconductor region and the semiconductor substrate. A semiconductor device according to 1. 前記第１のエピタキシャル層と前記半導体基板の間に、第２導電型の埋め込み層が形成されていることを特徴とする請求項３に記載の半導体装置。 4. The semiconductor device according to claim 3, wherein a buried layer of a second conductivity type is formed between the first epitaxial layer and the semiconductor substrate. 前記ドレイン領域と前記ソース領域の間の耐圧が、前記埋め込み層と前記半導体基板との間に形成されたｐｎ接合のアバランシェ降伏によって決定されることを特徴とする請求項７に記載の半導体装置。 8. The semiconductor device according to claim 7, wherein a breakdown voltage between the drain region and the source region is determined by an avalanche breakdown of a pn junction formed between the buried layer and the semiconductor substrate. 前記トレンチの平面形状が、ループ状であることを特徴とする請求項１または３に記載の半導体装置。 The semiconductor device according to claim 1, wherein a planar shape of the trench is a loop shape.
JP2004221160A 2004-07-29 2004-07-29 Semiconductor apparatus Withdrawn JP2006041308A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006108514A (en) * 2004-10-07 2006-04-20 Fuji Electric Holdings Co Ltd Semiconductor device and its manufacturing method
JP2007201391A (en) * 2005-12-28 2007-08-09 Sanyo Electric Co Ltd Semiconductor device
JP2007324408A (en) * 2006-06-01 2007-12-13 Fuji Electric Device Technology Co Ltd Semiconductor device and method of manufacturing the same
JP2012212923A (en) * 2012-07-02 2012-11-01 Fuji Electric Co Ltd Semiconductor device manufacturing method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006108514A (en) * 2004-10-07 2006-04-20 Fuji Electric Holdings Co Ltd Semiconductor device and its manufacturing method
JP2007201391A (en) * 2005-12-28 2007-08-09 Sanyo Electric Co Ltd Semiconductor device
JP2007324408A (en) * 2006-06-01 2007-12-13 Fuji Electric Device Technology Co Ltd Semiconductor device and method of manufacturing the same
JP2012212923A (en) * 2012-07-02 2012-11-01 Fuji Electric Co Ltd Semiconductor device manufacturing method

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