JP2006108514A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To incur an avalanche drop in a bulk region in a lateral power semiconductor device including a trench gate structure. <P>SOLUTION: A channel region between an n<SP>+</SP>source region 6a and an n<SP>-</SP>expansion drain region 2 is constructed from a (p) epitaxial layer 21 of uniform density to incur discontinuous density distribution in the vicinity of a pn junction between the n<SP>-</SP>expansion drain region 2 and the (p) epitaxial layer 21. The density of the n<SP>-</SP>expansion drain region 2 and the (p) epitaxial layer 21 is then optimized so that a potential becomes fine on the junction interface between the n<SP>-</SP>expansion drain region 2 and the (p) epitaxial layer 21, and so that, on the other hand, a potential becomes coarse on an interface between a gate oxide film 7 and the n<SP>-</SP>expansion drain region 2, thereby incurring breakdown in a bulk region. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and in particular, a low on-resistance power used for an IC that controls a large current with a high withstand voltage, such as a switching power supply IC, an automotive power system driving IC, or a flat panel display driving IC The present invention relates to a MOSFET (field effect transistor having an insulated gate structure made of metal-oxide film-semiconductor).

  In recent years, with the rapid spread of portable information devices and the advancement of communication technology, the importance of power ICs incorporating power MOSFETs has increased. In a power IC that integrates a horizontal power MOSFET and a control circuit, the size, power consumption, high reliability, and cost reduction are reduced compared to a conventional configuration in which a power MOSFET alone and a control drive circuit are combined. Be expected. Therefore, development of a high-performance lateral power MOSFET based on a CMOS process has been actively conducted. In particular, in recent years, lateral power MOSFETs have a structure in which a trench is formed in a semiconductor layer in which a channel is formed and a gate electrode is embedded in the lateral power MOSFET in order to achieve higher integration and lower on-resistance. (Trench gate structure) has been proposed.

  The following two structures have been proposed as a lateral power MOSFET (hereinafter referred to as TLPM) to which such a trench gate structure is applied. The first is a structure in which there is a drain region at the bottom of the trench, and electrical connection is made to the drain region through a buried electrode buried in the trench. The second is a structure in which a source region is provided at the bottom of the trench, and electrical connection to the source region is performed via a buried electrode in the trench (see, for example, Patent Document 1). Hereinafter, the first structure and the second structure are abbreviated as TLPM / D and TLPM / S because they are TLPMs having a drain contact and a source contact at the bottom of the trench, respectively.

The structure of the conventional TLPM / D and TLPM / S and the manufacturing process thereof will be described below. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. Further, “ ⁺ ” and “ ⁻ ” attached to n or p mean a relatively high impurity concentration or a relatively low impurity concentration, respectively. Note that the same reference numerals are given to the same components in all the attached drawings, and redundant description is omitted.

FIG. 52 is a cross-sectional view showing the structure of a conventional TLPM / D. The number of TLPM / D trenches is one. As shown in FIG. 52, trench 4 is formed in p ⁻ silicon substrate 1. A gate oxide film 7 is provided inside the trench 4. A gate electrode 8 is provided inside the gate oxide film 7. An interlayer insulating film 9 is formed inside the gate electrode 8. A buried electrode 10 serving as a plug is provided inside the interlayer insulating film 9. The buried electrode 10 is electrically connected to the n ⁺ drain region 16 at the bottom of the trench 4.

Another interlayer insulating film 11 is formed on the interlayer insulating film 9 and the buried electrode 10. Here, in order to distinguish several different interlayer insulating films, the interlayer insulating film labeled 9 is a first interlayer insulating film, and the interlayer insulating film labeled 11 is a third interlayer insulating film. The drain electrode 13 penetrates through the third interlayer insulating film 11 and is electrically connected to the buried electrode 10. An n ⁺ source region 6 a is provided in the surface region outside the opening end of the trench 4. A p ⁺ contact region 6b is provided in a surface region further outside the n ⁺ source region 6a.

The source electrode 12 penetrates the third interlayer insulating film 11 and is electrically connected to the n ⁺ source region 6a and the p ⁺ contact region 6b. The source electrode 12 and the drain electrode 13 are separated by the third interlayer insulating film 11. An n ⁻ extended drain region 2 is formed from the bottom of the trench 4 to the lower portion of the side wall of the trench 4. A P base region 5 serving as a channel region is formed between the n ⁻ extended drain region 2 and the n ⁺ source region 6a.

The TLPM / D shown in FIG. 52 is manufactured as follows. First, as shown in FIG. 53, mask oxide film 3 is formed on p ⁻ silicon substrate 1. Next, as shown in FIG. 54, a photoresist 101 is applied to the surface of the mask oxide film 3, and exposure and development are performed. Then, the mask oxide film 3 is patterned. After removing the photoresist 101, a trench 4 is formed in the p ⁻ silicon substrate 1 using the mask oxide film 3 as a mask, as shown in FIG. Next, as shown in FIG. 56, after forming a buffer oxide film 102 inside the trench 4, for example, phosphorus (P ₃₁ ) is ion-implanted as an n-type impurity into the bottom of the trench 4.

Next, as shown in FIG. 57, n ⁻ extended drain region 2 is formed at the bottom of trench 4. After removing the buffer oxide film 102, a gate oxide film 7 is formed inside the trench 4. Next, polysilicon to be the gate electrode 8 is deposited. Then, as shown in FIG. 58, the polysilicon is etched, leaving the polysilicon only in the portion along the side wall of the trench 4. Thereby, the gate electrode 8 is formed. Thereafter, shadow oxidation is performed to form a shadow oxide film 103 inside the gate electrode 8. Next, as shown in FIG. 59, a first interlayer insulating film 9 is deposited. Then, as shown in FIG. 60, the first interlayer insulating film 9 is etched to form a contact hole at the bottom of the trench 4.

Next, as shown in FIG. 61, an n-type impurity is introduced into n ⁻ extended drain region 2 through a contact hole at the bottom of trench 4 to form n ⁺ drain region 16. Next, a conductor to be the embedded electrode 10 is deposited. Then, as shown in FIG. 62, the conductor is etched to form the buried electrode 10. Subsequently, boron (B ₁₁ ), for example, is ion-implanted as a p-type impurity into the outer region of the opening end of the trench 4.

Next, as shown in FIG. 63, after forming the P base region 5, a region away from the opening end of the trench 4 is covered with a resist 104 in the outer region of the opening end of the trench 4. Then, for example, arsenic (As ₇₅ ) is ion-implanted as an n-type impurity into a region in contact with the opening end of the trench 4. After removing the resist 104, as shown in FIG. 64, the arsenic implantation region (the region indicated by the dotted line in FIG. 64) and the open end of the trench 4 are covered with a resist 105. Then, for example, boron is ion-implanted as a p-type impurity in a region away from the opening end of the trench 4. Next, as shown in FIG. 65, an n ⁺ source region 6a and a p ⁺ contact region 6b are formed in the outer region of the opening end of the trench 4, and after removing the resist 105, the third interlayer insulating film 11 is formed. accumulate.

  Thereafter, a photoresist 106 is applied, exposed and developed, and patterned for contact formation. Then, the third interlayer insulating film 11 is etched to open a source contact on the outer surface of the opening end of the trench 4 and open a drain contact on the surface of the buried electrode 10. Finally, after the photoresist 106 is removed, wiring is performed to form the source electrode 12 and the drain electrode 13. In this way, the device shown in FIG. 52 is completed.

66 and 67 are cross-sectional views showing the structure of a conventional TLPM / S having a one-stage trench structure. 66 and 67 show cross-sectional configurations of the active region and the base pickup region, respectively. In the active region, an n ⁺ source region 6 a is provided at the bottom of the trench 4. In contrast, in the base pickup region, a p ⁺ contact region 6b is provided at the bottom of the trench 4. Other configurations of the active region and the base pickup region are the same.

Similar to the above-described conventional TLPM / D (see FIG. 52), trench 4, gate oxide film 7, gate electrode 8, first interlayer insulating film 9 and buried electrode 10 are formed in p ⁻ silicon substrate 1. Yes. As shown in FIG. 66, in the active region, the buried electrode 10 is electrically connected to the n ⁺ source region 6 a at the bottom of the trench 4. On the other hand, as shown in FIG. 67, in the base pickup region, the buried electrode 10 is electrically connected to the p ⁺ contact region 6 b at the bottom of the trench 4. A mask oxide film 3 is formed on the outer surface of the opening end of the trench 4. A third interlayer insulating film 11 is formed on the mask oxide film 3, the first interlayer insulating film 9 and the buried electrode 10.

The source electrode 12 penetrates the third interlayer insulating film 11 and is electrically connected to the buried electrode 10. An n ⁺ drain region 16 is provided in the surface region outside the opening end of the trench 4. The drain electrode 13 penetrates the third interlayer insulating film 11 and the mask oxide film 3 therebelow and is electrically connected to the n ⁺ drain region 16. An n ⁻ extended drain region 2 is formed from the outer surface of the opening end of the trench 4 to the lower part of the side wall of the trench 4. A P base region 5 is formed between n ⁻ extended drain region 2 and n ⁺ source region 6a and p ⁺ contact region 6b.

The TLPM / S shown in FIGS. 66 and 67 is manufactured as follows. First, as shown in FIG. 68, n ⁻ extended drain region 2 is formed on the surface of p ⁻ silicon substrate 1, and mask oxide film 3 is deposited thereon. Next, as shown in FIG. 69, a photoresist 101 is applied to the surface of the mask oxide film 3, and exposure and development are performed. Then, the mask oxide film 3 is patterned. After removing the photoresist 101, as shown in FIG. 70, using the mask oxide film 3 as a mask, a trench 4 penetrating the n ⁻ extended drain region 2 and reaching the p ⁻ silicon substrate 1 is formed. Thereafter, as shown in FIG. 71, a buffer oxide film 102 is formed inside the trench 4.

  Next, as shown in FIG. 72, after removing the buffer oxide film 102, a gate oxide film 7 is formed inside the trench 4. Next, polysilicon to be the gate electrode 8 is deposited. Then, as shown in FIG. 73, the polysilicon is etched to form the gate electrode 8 only in the portion along the side wall of the trench 4. Thereafter, shadow oxidation is performed to form a shadow oxide film 103 inside the gate electrode 8. Next, as shown in FIG. 74, for example, boron is ion-implanted as a p-type impurity into the bottom of the trench 4. The process so far is common to the active region and the base pickup region.

  Next, the P base region 5 is formed in the active region and the base pickup region. Thereafter, in the active region, for example, arsenic is ion-implanted as an n-type impurity at the bottom of the trench 4 as shown in FIG. At this time, in the pickup region, as shown in FIG. 76, the bottom of the trench 4 is covered with a mask 107 so that arsenic is not implanted. After removing the mask 107, in the pickup region, for example, boron is ion-implanted as a p-type impurity into the bottom of the trench 4 as shown in FIG. At that time, in the active region, as shown in FIG. 77, a mask 108 is put on the bottom of the trench 4 so that boron is not implanted. In FIG. 77, a dotted line in the P base region 5 represents an arsenic implantation region.

The mask 108 is removed, and an n ⁺ source region 6a is formed at the bottom of the trench 4 in the active region, as shown in FIG. At the same time, as shown in FIG. 80, ap ⁺ contact region 6b is formed at the bottom of the trench 4 in the pickup region. Next, a first interlayer insulating film 9 is deposited in the active region and the base pickup region. Then, the first interlayer insulating film 9 is etched to form a contact hole at the bottom of the trench 4. Thereby, as shown in FIG. 81, n ⁺ source region 6a is exposed at the bottom of trench 4 in the active region. As shown in FIG. 82, p ⁺ contact region 6b is exposed at the bottom of trench 4 in the base pickup region.

Next, as shown in FIGS. 83 and 84, a conductor to be the buried electrode 10 is deposited in the active region and the base pickup region. Then, as shown in FIGS. 85 and 86, this conductor is etched to form the buried electrode 10. The buried electrode 10 is electrically connected to the n ⁺ source region 6a in the active region, and is electrically connected to the p ⁺ contact region 6b in the base pickup region.

  Next, as shown in FIGS. 87 and 88, a third interlayer insulating film 11 is deposited in the active region and the base pickup region. Then, the third interlayer insulating film 11 is etched using the mask of the resist 106 to open a drain contact on the outer surface of the opening end of the trench 4 and open a source contact on the surface of the buried electrode 10. After removing the resist 106, as shown in FIGS. 89 and 90, for example, arsenic is ion-implanted as an n-type impurity from the openings for the drain contact and the source contact. Finally, wiring is performed to form the source electrode 12 and the drain electrode 13. In this way, the device shown in FIGS. 66 and 67 is completed.

  FIG. 91 is a cross-sectional view showing a TLPM / D configuration having a conventional two-stage trench structure. As shown in FIG. 91, the TLPM / D having the two-stage trench structure is different from the TLPM / D having the one-stage trench structure shown in FIG. 52 on the lower surface of the trench 4 and the outer surface of the opening end of the trench 4. An interlayer insulating film (hereinafter referred to as a second interlayer insulating film) 15a thicker than the gate oxide film 7 is provided. The other configuration is the same as that of the TLPM / D having a one-stage trench structure, and thus redundant description is omitted.

The TLPM / D shown in FIG. 91 is manufactured as follows. First, according to the process shown in FIGS. 53 to 55, trench 4 is formed in p ⁻ silicon substrate 1 using mask oxide film 3 as a mask. Here, in the description of the manufacturing process of the TLPM / D having the two-stage trench structure, the first trench 4 to be formed is referred to as a first trench 4a, which is distinguished from a trench to be formed later (referred to as a second trench). . Next, as shown in FIG. 92, a nitride film 109 is deposited further inside the oxide film 110 formed on the inner wall of the first trench 4a. Then, as shown in FIG. 93, the nitride film 109 is etched to leave the nitride film 109 only on the side wall portion of the first trench 4a.

Next, as shown in FIG. 94, n ⁻ extended drain region 2 is formed at the bottom of first trench 4a using nitride film 109 as a mask. Thereafter, a second trench 4b having a narrower width than the first trench 4a is formed at the bottom of the first trench 4a. At this time, the mask oxide film 3 remaining on the substrate surface also disappears. Next, as shown in FIG. 95, a second interlayer insulating film 15a is formed on the bottom surface of the second trench 4b and the outer surface of the opening end of the first trench 4a. Next, as shown in FIG. 96, after removing the nitride film 109 and the oxide film 110, a gate oxide film 7 is formed on the side wall of the first trench 4a. Thereafter, polysilicon to be the gate electrode 8 is deposited.

Next, as shown in FIG. 97, the polysilicon is etched to form the gate electrode 8 only in the portion along the side wall of the first trench 4a. Next, as shown in FIG. 98, a first interlayer insulating film 9 is deposited inside the first trench 4a and the second trench 4b. Then, as shown in FIG. 99, the first interlayer insulating film 9 is etched to form a contact hole at the bottom of the second trench 4b. Thereafter, according to the process shown in FIGS. 61 to 65, n ⁺ drain region 16, buried electrode 10, P base region 5, n ⁺ source region 6a, p ⁺ contact region 6b, third interlayer insulating film 11, source Electrode 12 and drain electrode 13 are formed. In this way, the device shown in FIG. 91 is completed.

  100 and 101 are cross-sectional views showing the structure of a conventional TLPM / S having a two-stage trench structure. 100 and 101 show the cross-sectional configurations of the active region and the base pickup region, respectively. As shown in FIGS. 100 and 101, the TLPM / S of the two-stage trench structure is different from the TLPM / S of the one-stage trench structure shown in FIGS. 66 and 67 in the upper half of the sidewall of the trench 4. An interlayer insulating film thicker than the gate oxide film 7 is provided. In the TLPM / S having a two-stage trench structure, this thick interlayer insulating film is used as a second interlayer insulating film 15b. The other configuration is the same as that of the TLPM / S having a one-stage trench structure, and thus redundant description is omitted.

The TLPM / S shown in FIGS. 100 and 101 is manufactured as follows. First, the process shown in FIGS. That is, the n ⁻ extended drain region 2 is formed, and the trench 4 is formed in the p ⁻ silicon substrate 1 using the mask oxide film 3 as a mask. However, the trench 4 is made shallower than the n ⁻ extended drain region 2. In the description of the manufacturing process of the TLPM / S having the two-stage trench structure, the first trench 4 formed as the first trench 4a. Next, as shown in FIG. 102, a second interlayer insulating film 15b is deposited.

Then, as shown in FIG. 103, the second interlayer insulating film 15b is etched to leave the second interlayer insulating film 15b only on the side wall portion of the first trench 4a. Note that the n ⁻ extended drain region 2 may be formed in the outer region of the side wall portion of the first trench 4a before the second interlayer insulating film 15b is deposited.

Next, as shown in FIG. 104, the bottom of the first trench 4a is etched using the second interlayer insulating film 15b as a mask to form a second trench 4b having a width narrower than that of the first trench 4a. To do. Second trench 4 b penetrates n ⁻ extended drain region 2 and reaches p ⁻ silicon substrate 1. Thereafter, as shown in FIG. 105, a buffer oxide film 102 is formed inside the second trench 4b. Thereafter, according to the process shown in FIGS. 72 to 90, gate oxide film 7, gate electrode 8, P base region 5, n ⁺ source region 6a, p ⁺ contact region 6b, first interlayer insulating film 9, buried electrode 10. A third interlayer insulating film 11, a source electrode 12, and a drain electrode 13 are formed. In this way, the device shown in FIGS. 100 and 101 is completed.

  As described above, in each TLPM, transistors are formed on the trench sidewalls, so that higher integration can be achieved than in conventional planar type power MOS devices. Therefore, TLPM has an advantage that the on-resistance per unit area, which is one of the important indexes for measuring the performance of the power MOS device, can be reduced.

JP 2002-353447 A

However, in the conventional TLPM, breakdown is dense at the interface between the gate oxide film and the substrate. The reason for this will be described by taking TLPM / D shown in FIG. 52 as an example. FIG. 106 is a diagram showing the potential distribution of the main part when the TLPM / D shown in FIG. 52 is avalanche yielded, and the potential curve is indicated by a broken line. The potential becomes dense at the interface (indicated by “A” in FIG. 106) between the gate oxide film 7 and the substrate (n ⁻ extended drain region 2). On the other hand, the potential is sparse at the junction interface between n ⁻ extended drain region 2 and p ⁻ silicon substrate 1 (indicated by “B” and “C” in FIG. 106).

This potential distribution is due to the following reason. That is, the n ⁻ extended drain region 2 and the gate electrode 8 are opposed to each other through the thin gate oxide film 7, that is, the overlap is large. On the other hand, in “B” and “C” in FIG. 106, the depletion layer easily spreads, so that the electric field is relaxed. This is because the P base region 5 and the n ⁻ extended drain region 2 are both formed by impurity diffusion, so that the concentration distribution in the pn diode formed between the P base region 5 and the n ⁻ extended drain region 2 is This is because it changes continuously. Since the impurity concentration of the p ⁻ silicon substrate 1 is sufficiently lower than that of the n ⁻ extended drain region 2 and the P base region 5, a discontinuous concentration distribution is not formed.

  Thus, the conventional TLPM / D has a structure in which the electric field concentrates at “A” in FIG. 106 and breakdown occurs. Therefore, not only the phenomenon of avalanche walkout in which the charge is trapped in the gate oxide film 7 due to the avalanche breakdown and the on / off characteristics of the TLPM fluctuate occurs, but also the reliability of the gate oxide film 7 is lowered. There is.

Further, since the channel concentration continuously changes in the direction of current flow (depth direction), there is also a problem that the threshold value tends to vary due to the pn junction shift. Further, a diffusion resistance (indicated by “R _base ” in FIG. 106) of the P base region 5 is generated between the p ⁺ contact region 6b and the channel, and the base resistance increases, so that the SOA (safe operation region) is narrow. There is also the problem of becoming.

There is a similar problem in the conventional TLPM / S. FIG. 107 is a diagram showing a potential distribution of main parts when the TLPM / S shown in FIG. 66 is avalanche yielded. In FIG. 107, a broken line represents a potential curve. Also in TLPM / S, since the P base region 5 and the n ⁻ extended drain region 2 are both formed by impurity diffusion, the concentration gradient of these pn junctions changes gently. Therefore, the electric field is relaxed at the junction interface between n ⁻ extended drain region 2 and P base region 5 (indicated by “D” in FIG. 107).

On the other hand, in the region close to the opening end of the trench 4 (indicated by “E” in FIG. 107), the concentration of the n ⁻ extended drain region 2 increases as the opening end of the trench 4 is approached. Become. Furthermore, since the gate electrode 8 faces the n ⁻ extended drain region 2 through the gate oxide film 7, breakdown occurs at the interface between the gate oxide film 7 and the substrate (n ⁻ extended drain region 2). Sex is reduced. The above problems are common to the conventional TLPM having a two-stage trench structure.

  In order to solve the above-described problems caused by the conventional technology, an object of the present invention is to provide a structure in which avalanche breakdown occurs in a bulk region and a manufacturing method thereof in a lateral power semiconductor device having a trench gate structure. . It is another object of the present invention to provide a horizontal power semiconductor device having a trench gate structure and having a low threshold value variation, and a method for manufacturing the same.

In order to solve the above-described problems and achieve the object, a semiconductor device according to the invention of claim 1 includes:
A first conductive type semiconductor layer provided on a semiconductor substrate; a first second conductive type semiconductor region provided at a bottom of the trench formed in the first conductive type semiconductor layer; and adjacent to the trench. A second second conductive type semiconductor region provided on a surface layer of the first conductive type semiconductor layer, and provided between the first conductive type semiconductor layer and the first second conductive type semiconductor region. A third second conductivity type semiconductor region, an insulating film provided inside the trench along the side of the trench, the second second conductivity type semiconductor region, and the third second conductivity A first electrode provided on the surface of the first conductive semiconductor layer between the first semiconductor layer and the insulating film via the insulating film, and connected to the first second conductive semiconductor region at the bottom of the trench And embedded in an interlayer insulating film provided inside the first electrode. And write electrode, a second electrode connected to the buried electrode,
A third electrode connected to the second second-conductivity-type semiconductor region, wherein the first-conductivity-type semiconductor layer has a uniform impurity concentration, and the third second-conductivity-type semiconductor region The impurity concentration is lower than the impurity concentration of the first second conductivity type semiconductor region.

  According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the first second conductivity type semiconductor region is a drain region, and the second second conductivity type semiconductor region is a source region. The third second conductivity type semiconductor region is a lateral field effect transistor having an insulated gate structure made of a metal-oxide film-semiconductor which is an extended drain region. According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, the third second-conductivity-type semiconductor region is an impurity diffusion layer having a concentration distribution due to impurity diffusion. And According to a fourth aspect of the present invention, there is provided the semiconductor device according to the first or second aspect, wherein the third second-conductivity-type semiconductor region has a uniform impurity concentration. A semiconductor device according to a fifth aspect of the present invention is the semiconductor device according to any one of the first to fourth aspects, wherein the conductivity type of the semiconductor substrate is a first conductivity type. According to a sixth aspect of the present invention, in the semiconductor device according to any one of the first to fourth aspects, the conductivity type of the semiconductor substrate is a second conductivity type.

  According to a seventh aspect of the present invention, there is provided a semiconductor device comprising: a first conductivity type semiconductor layer provided on a semiconductor substrate; a second conductivity type semiconductor layer provided on the first conductivity type semiconductor layer; A first second conductivity type semiconductor region provided in a surface region of the second conductivity type semiconductor layer; and a second second conductivity type semiconductor provided in a bottom portion of a trench penetrating the second conductivity type semiconductor layer. The first conductivity type between the region, the insulating film provided inside the trench along the side of the trench, and the second conductivity type semiconductor layer and the second second conductivity type semiconductor region A first electrode provided on the surface of the semiconductor layer via the insulating film; and connected to the second second-conductivity-type semiconductor region at the bottom of the trench and provided inside the first electrode A buried electrode surrounded by the formed interlayer insulating film, and the first second conductor A second electrode connected to the type semiconductor region and a third electrode connected to the buried electrode, wherein the first conductivity type semiconductor layer has a uniform impurity concentration, and the second conductivity type semiconductor The layer has a uniform impurity concentration lower than the impurity concentration of the first second conductivity type semiconductor region.

  The semiconductor device according to an eighth aspect of the present invention is the semiconductor device according to the seventh aspect, wherein the first second conductivity type semiconductor region is a drain region, and the second second conductivity type semiconductor region is a source region. The second conductive semiconductor layer is a lateral field effect transistor having an insulated gate structure made of a metal-oxide film-semiconductor serving as an extended drain region. According to a ninth aspect of the present invention, in the semiconductor device according to the seventh or eighth aspect, the conductivity type of the semiconductor substrate is a first conductivity type. According to a tenth aspect of the present invention, in the semiconductor device according to the seventh or eighth aspect, the conductivity type of the semiconductor substrate is a second conductivity type. The semiconductor device according to an eleventh aspect of the present invention is the semiconductor device according to any one of the first to tenth aspects, wherein a second interlayer insulating film thicker than the insulating film is provided on a side of the trench inside the trench. It is provided along the part.

  According to a twelfth aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: forming a first conductivity type impurity layer having a uniform impurity concentration on a semiconductor substrate; and forming a trench in the first conductivity type impurity layer. A step of diffusing impurities in the bottom of the trench to form a third second-conductivity-type semiconductor region, a step of forming an insulating film inside the trench along the side of the trench, and an inner side of the insulating film Forming a first electrode, forming an interlayer insulating film inside the first electrode, exposing the semiconductor to the bottom of the trench through the interlayer insulating film, the third third Forming a first second conductivity type semiconductor region at the bottom of the trench in a two conductivity type semiconductor region, inside the interlayer insulating film, and at the bottom of the trench in the first second conductivity type semiconductor region; Embedded to connect Forming a pole, forming a second second-conductivity-type semiconductor region in a surface layer of the first-conductivity-type impurity layer adjacent to the trench, a second electrode connected to the buried electrode, and the first Forming a third electrode connected to the second second conductive type semiconductor region in order.

  According to a thirteenth aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming a first first conductivity type impurity layer having a uniform impurity concentration on a semiconductor substrate; and the first first conductivity type impurity layer. Forming a third trench, forming a second conductivity type impurity layer having a uniform impurity concentration inside the third trench, the first first conductivity type impurity layer, and the second conductivity type. Forming a second first-conductivity-type impurity layer having a uniform impurity concentration on the impurity layer; and a first penetrating through the second first-conductivity-type impurity layer with a narrower width than the third trench. Forming a trench; forming an insulating film inside the first trench along a side of the first trench; forming a first electrode inside the insulating film; Forming an interlayer insulating film on the inner side of the electrode, the interlayer Exposing the semiconductor to the bottom of the first trench through the edge film; forming the first second conductivity type semiconductor region at the bottom of the first trench in the second conductivity type impurity layer; Forming a buried electrode connected to the first second-conductivity-type semiconductor region at the bottom of the first trench inside the interlayer insulating film; a first-conductivity-type impurity layer adjacent to the trench; Forming a second second-conductivity-type semiconductor region on the surface layer, forming a second electrode connected to the buried electrode, and a third electrode connected to the second second-conductivity-type semiconductor region Are performed in order.

  According to a fourteenth aspect of the present invention, there is provided a semiconductor device manufacturing method according to the twelfth or thirteenth aspect of the present invention, wherein the semiconductor substrate has a first conductivity type. According to a fifteenth aspect of the present invention, in the semiconductor device manufacturing method according to the twelfth or thirteenth aspect of the present invention, the conductivity type of the semiconductor substrate is a second conductivity type.

  According to a sixteenth aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: forming a first conductivity type impurity layer having a uniform impurity concentration on a semiconductor substrate; and forming a uniform impurity on the first conductivity type impurity layer. Forming a second conductivity type impurity layer having a concentration; forming a trench penetrating the second conductivity type impurity layer; forming an insulating film inside the trench along a side of the trench; A step of forming a first electrode inside the insulating film, a step of forming a second second conductive semiconductor region at the bottom of the trench, a step of forming an interlayer insulating film inside the first electrode, Exposing the second second conductivity type semiconductor region to the bottom of the trench through the interlayer insulation film, the second second conductivity type semiconductor region at the bottom of the trench inside the interlayer insulation film Embedded power to connect to A step of forming a first second conductivity type semiconductor region outside the first trench, a second electrode connected to the first second conductivity type semiconductor region, and a connection to the buried electrode The step of forming the third electrode is sequentially performed.

  According to a seventeenth aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming a first first conductivity type impurity layer having a uniform impurity concentration on a semiconductor substrate; and the first first conductivity type impurity layer. Forming a third trench, forming a second first conductivity type impurity layer having a uniform impurity concentration inside the third trench, the first first conductivity type impurity layer and the first trench Forming a second conductivity type impurity layer having a uniform impurity concentration on the second first conductivity type impurity layer, a first through the second conductivity type impurity layer with a width narrower than that of the third trench. Forming a trench; forming an insulating film inside the first trench along a side of the first trench; forming a first electrode inside the insulating film; Forming a second second-conductivity-type semiconductor region at the bottom of each trench A step of forming an interlayer insulating film inside the first electrode, a step of exposing the second second-conductivity-type semiconductor region at the bottom of the first trench through the interlayer insulating film, Forming a buried electrode connected to the second second-conductivity-type semiconductor region at the bottom of the first trench on the inner side of the interlayer insulating film; and first second conductive on the outer side of the first trench. A step of forming a type semiconductor region, a step of forming a second electrode connected to the first second conductivity type semiconductor region, and a third electrode connected to the buried electrode.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device comprising: forming a first conductivity type impurity layer having a uniform impurity concentration on a semiconductor substrate; and forming a first trench in the first conductivity type impurity layer. A step of forming a third second conductivity type semiconductor region by diffusing impurities in a bottom portion of the first trench, and inside the first trench along a side portion of the first trench. Forming an insulating film; forming a mask insulating film on a sidewall of the first trench; forming a second trench shallower than the third second-conductivity-type semiconductor region at a bottom of the first trench; A step of forming a second interlayer insulating film thicker than the insulating film at the bottom of the second trench, a step of removing the mask insulating film, and forming a first electrode inside the insulating film. Step, inside the first electrode Forming a first interlayer insulating film, exposing the semiconductor to the bottom of the second trench through the first interlayer insulating film and the second interlayer insulating film, the third second Forming a first second conductive type semiconductor region at the bottom of the second trench in the conductive type semiconductor region, and inside the first interlayer insulating film and the second interlayer insulating film, Forming a buried electrode connected to the first second-conductivity-type semiconductor region at the bottom of the trench, and adjacent to the trench, a second second-conductivity-type semiconductor is formed on the surface layer of the first-conductivity-type impurity layer. A step of forming a region, a step of forming a second electrode connected to the buried electrode and a third electrode connected to the second second conductivity type semiconductor region are sequentially performed.

  According to a nineteenth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a first first conductivity type impurity layer having a uniform impurity concentration on a semiconductor substrate; and the first first conductivity type impurity layer. Forming a third trench, forming a second conductivity type impurity layer having a uniform impurity concentration inside the third trench, the first first conductivity type impurity layer, and the second conductivity type. Forming a second first-conductivity-type impurity layer having a uniform impurity concentration on the impurity layer; and a first penetrating through the second first-conductivity-type impurity layer with a narrower width than the third trench. Forming a trench; forming an insulating film inside the first trench along a side of the first trench; forming a mask insulating film on a sidewall of the first trench; The first trench at the bottom of one trench Forming a second trench having a narrow width, forming a second interlayer insulating film thicker than the insulating film at the bottom of the second trench, removing the mask insulating film, and the insulating film Forming a first electrode inside the first electrode, forming a first interlayer insulating film inside the first electrode, penetrating the first interlayer insulating film and the second interlayer insulating film Exposing the semiconductor to the bottom of the second trench, forming a first second conductivity type semiconductor region at the bottom of the second trench in the second conductivity type impurity layer, the first interlayer Forming a buried electrode connected to the first second conductivity type semiconductor region at the bottom of the second trench inside the insulating film and the second interlayer insulating film; adjacent to the trench; The second conductive layer is formed on the surface layer of the first conductive type impurity layer. Forming a semiconductor region, and performing the step of forming a third electrode connected to the second electrode and the second second-conductivity type semiconductor region to be connected to the buried electrode, in this order.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device comprising: forming a first conductivity type impurity layer having a uniform impurity concentration on a semiconductor substrate; and forming a uniform impurity on the first conductivity type impurity layer. Forming a second conductivity type impurity layer having a concentration; forming a second trench shallower than the second conductivity type impurity layer in the second conductivity type impurity layer; and forming a second trench on the sidewall of the second trench. Forming a first interlayer insulating film, wherein a first width penetrating the second conductivity type impurity layer at a bottom width of the second trench with a width narrower than that of the second trench using the second interlayer insulating film as a mask. Forming a trench; forming an insulating film inside the first trench along a side portion of the first trench; a first electrode inside the second interlayer insulating film and the insulating film Forming the first electrode Forming a first interlayer insulating film on the side; exposing the semiconductor to the bottom of the first trench through the first interlayer insulating film; and a second second at the bottom of the first trench. Forming a two-conductivity type semiconductor region; forming a buried electrode connected to the second second-conductivity type semiconductor region at the bottom of the first trench inside the first interlayer insulating film; Forming a first second conductivity type semiconductor region outside the first trench; a second electrode connected to the first second conductivity type semiconductor region; and a third electrode connected to the buried electrode. The forming step is performed in order.

  According to a twenty-first aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to any one of the sixteenth to twentieth aspects, wherein the semiconductor substrate has a first conductivity type. According to a twenty-second aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to any one of the sixteenth to twentieth aspects, wherein the conductivity type of the semiconductor substrate is a second conductivity type.

  According to the invention of each of the above claims, a discontinuous concentration distribution is formed in the vicinity of the pn junction surface between the first conductivity type semiconductor layer having a uniform concentration and the second conductivity type semiconductor region or semiconductor layer in contact therewith. The avalanche breakdown occurs at the pn diode junction surface. Further, since the concentration of the inversion layer through which the current flows is uniform in the direction in which the current flows, the variation in threshold value is reduced.

  According to the semiconductor device and the manufacturing method thereof according to the present invention, it is possible to obtain a lateral power semiconductor device having a trench gate structure and in which avalanche breakdown occurs in a bulk region. In addition, there is an effect that a lateral power semiconductor device having a trench gate structure and with less variation in threshold value can be obtained.

  Exemplary embodiments of a semiconductor device and a method for manufacturing the same according to the present invention will be explained below in detail with reference to the accompanying drawings. Although not particularly limited, in each of the following embodiments, an example in which an epitaxial layer is used as an impurity layer having a uniform concentration will be described.

Embodiment 1 FIG.
FIG. 1 is a cross-sectional view showing the configuration of the TLPM / D according to the first embodiment of the present invention. The number of trenches is one. As shown in FIG. 1, a p-type epitaxial layer 21 having a uniform concentration serving as a channel region is provided on a p ⁻ silicon substrate 1. Trench 4 is formed in epitaxial layer 21 and is shallower than the interface between p epitaxial layer 21 and p ⁻ silicon substrate 1. The n ⁺ drain region 16 provided at the bottom of the trench 4 and the n ⁻ extended drain region 2 surrounding the n ⁺ drain region 16 are provided in the p epitaxial layer 21. The n ⁻ extended drain region 2 is an impurity diffusion layer formed by impurity diffusion and has a concentration distribution.

N ⁺ source region 6 a and p ⁺ contact region 6 b are provided in the surface region of p epitaxial layer 21. For the gate oxide film 7, the gate electrode 8, the first interlayer insulating film 9, the buried electrode 10, the third interlayer insulating film 11, the source electrode 12, and the drain electrode 13, the conventional TLPM / D configuration shown in FIG. It is the same. However, in the first embodiment, the P base region is not provided. In other words, the p epitaxial layer 21 is provided instead of the conventional P base region.

Here, the p ⁻ silicon substrate 1, the p epitaxial layer 21, the n ⁺ drain region 16, the n ⁺ source region 6a, and the n ⁻ extended drain region 2 are respectively a semiconductor substrate, a first conductivity type semiconductor layer, and a first second layer. It corresponds to a conductive semiconductor region, a second second conductive semiconductor region, and a third second conductive semiconductor region. The gate oxide film 7, the gate electrode 8, the drain electrode 13, the source electrode 12, and the first interlayer insulating film 9 are respectively an insulating film inside the trench, a first electrode, a second electrode, and a third electrode. It corresponds to an interlayer insulating film inside the first electrode.

In the configuration shown in FIG. 1, in order to obtain a withstand voltage of 30 V, it is desirable that the depth of the trench 4 be, for example, about 2.0 μm. For the profile, for example, the concentration of the p epitaxial layer 21 is 1 × 10 ¹⁷ cm ⁻³ , the surface concentration of the n ⁻ extended drain region 2 is 5 × 10 ¹⁶ cm ⁻³ , and the diffusion length is 0.6 μm. Good. In this case, a device having a threshold voltage of about 2.0 V, an off breakdown voltage of about 33 V, and an on breakdown voltage of about 30 V can be obtained.

A method of manufacturing the TLPM / D having the configuration shown in FIG. 1 will be described. First, as shown in FIG. 2, ap epitaxial layer 21 is grown on the p ⁻ silicon substrate 1. Next, as shown in FIG. 3, a mask oxide film 3 is formed on the p epitaxial layer 21. Then, a photoresist 101 is applied to the surface of the mask oxide film 3, and exposure and development are performed. Thereafter, the mask oxide film 3 is patterned. After removing the photoresist 101, a trench 4 is formed in the p epitaxial layer 21 using the mask oxide film 3 as a mask, as shown in FIG. At that time, the trench 4 is formed shallower than the p epitaxial layer 21. This is because a channel is formed only by the p epitaxial layer 21.

Thereafter, according to the process shown in FIGS. 56 to 65, n ⁻ extended drain region 2, gate oxide film 7, gate electrode 8, first interlayer insulating film 9, n ⁺ drain region 16, buried electrode 10, n ⁺ A source region 6a, ap ⁺ contact region 6b, a third interlayer insulating film 11, a source electrode 12 and a drain electrode 13 are formed. However, in the first embodiment, the channel concentration is adjusted by the impurity concentration of the p epitaxial layer 21 without forming the P base region. Therefore, in the processes shown in FIGS. 62 to 63, the ion implantation step and the diffusion step of the p-type impurity for forming the P base region can be omitted. As described above, the device shown in FIG. 1 is completed. The gate electrode 8 may be formed with a length corresponding to the surface portion (channel forming portion) of the p epitaxial layer 21 between the n ⁺ source region 6a and the n ⁻ extended drain region 2, but in FIG. It is formed to the vicinity of the bottom of the trench 4 and is formed so as to extend from the channel forming portion. This extended part acts as a field plate.

According to the first embodiment, a discontinuous concentration distribution is generated in the vicinity of the pn junction between the n ⁻ extended drain region 2 and the p epitaxial layer 21, so that breakdown occurs in the vicinity of the pn junction interface. Further, according to the first embodiment, by optimizing the concentrations of the n ⁻ extended drain region 2 and the p epitaxial layer 21, as shown in FIG. 5, a potential curve at the time of avalanche breakdown (shown by a broken line) is n ^The potential becomes dense at the junction interface between the extended drain region 2 and the p epitaxial layer 21 (indicated by “F” in FIG. 5), while the interface between the gate oxide film 7 and the n ⁻ extended drain region 2 (shown in FIG. 5). The potential can be made sparse by “G”. That is, breakdown can occur in the bulk region. Therefore, it is possible to prevent the avalanche walkout and the reliability of the gate oxide film 7 from being lowered.

Further, according to the first embodiment, since the channel concentration becomes uniform along the side wall of the trench 4, the variation in threshold value can be reduced regardless of the variation (shift) in the pn junction position. Furthermore, since the base resistance is determined only by the diffusion resistance of the p epitaxial layer 21 and the p ⁺ contact region 6b, the base resistance can be reduced. Therefore, the SOA can be widened.

Incidentally, p ^- in place of the silicon substrate 1, as shown in FIG. 6, n ^- may be a silicon substrate 1a. In this case, the configuration other than the n ⁻ silicon substrate 1a is the same as that when the p ⁻ silicon substrate 1 is used. The manufacturing method, n ^- that use a silicon substrate 1a is different only, otherwise p ^- is the same as when using a silicon substrate 1. Further, even when the n ⁻ silicon substrate 1a is used, the same effect as that obtained when the p ⁻ silicon substrate 1 is used can be obtained.

Embodiment 2. FIG.
FIG. 7: is sectional drawing which shows the structure of TLPM / D concerning Embodiment 2 of this invention. The number of trenches is one. As shown in FIG. 7, in the second embodiment, the n ⁻ extended drain region is formed by the n ⁻ epitaxial layer 22 having a uniform concentration in the first embodiment. That is, as shown in FIG. 7, the first p epitaxial layer 21 a is provided on the p ⁻ silicon substrate 1. In the first p epitaxial layer 21a, an n ⁻ epitaxial layer 22 having a uniform concentration is provided as an extended drain region.

On the first p epitaxial layer 21a and the n ⁻ epitaxial layer 22, a second p epitaxial layer 21b serving as a channel region is provided. The trench 4 penetrates through the second p epitaxial layer 21b and reaches the n ⁻ epitaxial layer 22. Other configurations are the same as those in the first embodiment. In the illustrated example, the trench 4 is deeper than the second p epitaxial layer 21b. However, the bottom of the trench 4 may just reach the n ⁻ epitaxial layer 22.

  In the second embodiment, the first p epitaxial layer 21a and the second p epitaxial layer 21b correspond to a first first conductivity type impurity layer and a second first conductivity type impurity layer, respectively. A combination of the first p epitaxial layer 21a and the second p epitaxial layer 21b corresponds to the first conductivity type semiconductor layer.

In the configuration shown in FIG. 7, in order to obtain a withstand voltage of 30 V, it is desirable that the depth of the trench 4 be, for example, about 2.0 μm. Regarding the profile, for example, the concentration of the first p epitaxial layer 21a and the second p epitaxial layer 21b is 1 × 10 ¹⁷ cm ^−3, and the concentration of the n ⁻ epitaxial layer 22 is 3 × 10 ¹⁶ cm ^−3. It is good to. In this case, a device having a threshold voltage of about 2.0 V, an off breakdown voltage of about 33 V, and an on breakdown voltage of about 30 V can be obtained.

Alternatively, the concentration of the second p epitaxial layer 21b may be lower than the concentration of the first p epitaxial layer 21a. For example, in the above-described concentration, only the concentration of the second p epitaxial layer 21b may be 5 × 10 ¹⁶ cm ⁻³ . In this case, a device having a threshold voltage of about 1.2 V can be obtained without reducing the on-breakdown voltage and the off-breakdown voltage.

A method for manufacturing the TLPM / D having the configuration shown in FIG. 7 will be described. First, as shown in FIG. 8, a first p epitaxial layer 21 a is grown on the p ⁻ silicon substrate 1. Next, as shown in FIG. 9, a mask oxide film 3a is formed on first p epitaxial layer 21a. Then, a photoresist 111 is applied to the surface of the mask oxide film 3a, and exposure and development are performed. Thereafter, the mask oxide film 3a is patterned. After removing the photoresist 111, as shown in FIG. 10, a trench is formed in the first p epitaxial layer 21a using the mask oxide film 3a as a mask. This trench is referred to as a third trench 4c.

As shown in the example, the third trench 4c may be shallower than the first p epitaxial layer 21a, the third trench 4c may be deeper than the first p epitaxial layer 21a, The bottom of the third trench 4c may have just reached the p ⁻ silicon substrate 1.

Next, as shown in FIG. 11, an n ⁻ epitaxial layer 22 to be an extended drain region is grown in the third trench 4c. At that time, the mask oxide film 3a is used as a stopper. Next, as shown in FIG. 12, mask oxide film 3a is removed, and the surface formed of first p epitaxial layer 21a and n ⁻ epitaxial layer 22 is planarized. Then, as shown in FIG. 13, a second p epitaxial layer 21b serving as a channel region is grown on the surfaces of first p epitaxial layer 21a and n ⁻ epitaxial layer 22.

At that time, the concentration can be adjusted independently between the first p epitaxial layer 21a and the second p epitaxial layer 21b, but the first p epitaxial layer 21a is thicker than the second p epitaxial layer 21b. Is preferable. This is because the avalanche breakdown is caused at the junction interface between the first p epitaxial layer 21a and the n ⁻ epitaxial layer 22, that is, in the bulk region, by increasing the concentration of the first p epitaxial layer 21a.

  Next, as shown in FIG. 14, a mask oxide film 3 is formed on the second p epitaxial layer 21b. Then, a photoresist 101 is applied to the surface of the mask oxide film 3, and exposure and development are performed. Thereafter, the mask oxide film 3 is patterned. After removing the photoresist 101, as shown in FIG. 15, a first trench 4a (to be the trench 4 in FIG. 7) is formed in the second p epitaxial layer 21b using the mask oxide film 3 as a mask. At that time, the width of the first trench 4a is made smaller than the width of the third trench 4c.

Also, the first trench 4a is formed so that the bottom of the first trench 4a reaches the n ⁻ epitaxial layer 22 just as shown, or the first trench 4a is formed as the second p-epitaxial as in the illustrated example. It is formed so as to be deeper than the layer 21b. This is because a channel is formed in the second p epitaxial layer 21b along the side wall of the first trench 4a.

Next, as shown in FIG. 16, the mask oxide film 3 is removed. Then, as shown in FIG. 17, a gate oxide film 7 is formed inside the first trench 4a, and then polysilicon to be the gate electrode 8 is deposited. Thereafter, according to the processes shown in FIGS. 58 to 65, the gate electrode 8, the first interlayer insulating film 9, the n ⁺ drain region 16, the buried electrode 10, the n ⁺ source region 6a, the p ⁺ contact region 6b, the third The interlayer insulating film 11, the source electrode 12, and the drain electrode 13 are formed. However, in the second embodiment, the channel concentration is adjusted by the impurity concentration of the second p epitaxial layer 21b without forming the P base region. Therefore, in the processes shown in FIGS. 62 to 63, the ion implantation step and the diffusion step of the p-type impurity for forming the P base region can be omitted. As described above, the device shown in FIG. 7 is completed.

According to the second embodiment, the same effect as in the first embodiment can be obtained. Further, since the n ⁻ extended drain region is made of the n ⁻ epitaxial layer 22, the concentration of the extended drain region becomes uniform, so that an increase in on-resistance due to a concentration gradient can be prevented.

Embodiment 3 FIG.
18 and 19 are cross-sectional views showing the configuration of the TLPM / S according to the third embodiment of the present invention. 18 and 19 show cross-sectional configurations of the active region and the base pickup region, respectively. The number of trenches is one. As shown in these figures, in the active region and the base pickup region, a p-epitaxial layer 21 having a uniform concentration serving as a channel region is provided on the p ⁻ silicon substrate 1. On the p epitaxial layer 21, an n ⁻ epitaxial layer 22 serving as an extended drain region is provided. The concentration of n ⁻ epitaxial layer 22 is lower than n ⁺ drain region 16 and is uniform. The trench 4 penetrates through the n ⁻ epitaxial layer 22 and reaches the p epitaxial layer 21.

In the active region, an n ⁺ source region 6 a is provided at the bottom of the trench 4. In the base pickup region, a p ⁺ contact region 6 b is provided at the bottom of the trench 4. N ⁺ source region 6 a and p ⁺ contact region 6 b are provided in p epitaxial layer 21. The n ⁺ drain region 16 is provided in the surface region outside the open end of the trench 4 in the n ⁻ epitaxial layer 22.

The gate oxide film 7, gate electrode 8, first interlayer insulating film 9, buried electrode 10, mask oxide film 3, third interlayer insulating film 11, source electrode 12 and drain electrode 13 are shown in FIGS. It is the same as that of the conventional TLPM / S shown. However, in the third embodiment, the P base region is not provided. The p epitaxial layer 21 replaces the conventional P base region. In the illustrated example, the trench 4 is deeper than the n ⁻ epitaxial layer 22, but the bottom of the trench 4 may just reach the p epitaxial layer 21.

Here, the p ⁻ silicon substrate 1, the p epitaxial layer 21, the n ⁻ epitaxial layer 22, the n ⁺ drain region 16 and the n ⁺ source region 6a are respectively a semiconductor substrate, a first conductivity type semiconductor layer, and a second conductivity type semiconductor layer. These correspond to the first second conductivity type semiconductor region and the second second conductivity type semiconductor region. The gate oxide film 7, the gate electrode 8, the drain electrode 13, the source electrode 12, and the first interlayer insulating film 9 are respectively an insulating film inside the trench, a first electrode, a second electrode, and a third electrode. It corresponds to an interlayer insulating film inside the first electrode.

In the configurations shown in FIGS. 18 and 19, it is desirable that the channel length be at least about 0.4 μm in order to prevent punch-through. For the profile, for example, the concentration of the p epitaxial layer 21 may be 1 × 10 ¹⁷ cm ⁻³ and the concentration of the n ⁻ epitaxial layer 22 may be 3 × 10 ¹⁶ cm ⁻³ . In this case, a device having a threshold voltage of about 2.0 V, an off breakdown voltage of about 33 V, and an on breakdown voltage of about 30 V can be obtained.

A method for manufacturing the TLPM / S having the configuration shown in FIGS. 18 and 19 will be described. First, as shown in FIG. 20, ap epitaxial layer 21 is grown on the p ⁻ silicon substrate 1. Subsequently, an n ⁻ epitaxial layer 22 is grown on the p epitaxial layer 21. Next, as shown in FIG. 21, mask oxide film 3 is formed on n ⁻ epitaxial layer 22. Then, a photoresist 101 is applied to the surface of the mask oxide film 3, and exposure and development are performed.

Thereafter, the mask oxide film 3 is patterned. After removing the photoresist 101, as shown in FIG. 22, a trench 4 that penetrates the n ⁻ epitaxial layer 22 and reaches the p epitaxial layer 21 is formed using the mask oxide film 3 as a mask. The process so far is common to the active region and the base pickup region.

Thereafter, according to the process shown in FIGS. 72 to 90, the gate oxide film 7, the gate electrode 8, the n ⁺ source region 6a, the p ⁺ contact region 6b, the first interlayer insulating film 9, the buried electrode 10, and the third electrode Interlayer insulating film 11, source electrode 12 and drain electrode 13 are formed. However, in the third embodiment, the channel concentration is adjusted by the impurity concentration of the p epitaxial layer 21 without forming the P base region. Therefore, in the process shown in FIGS. 74 to 75, the ion implantation step and the diffusion step of the p-type impurity for forming the P base region can be omitted. As described above, the devices shown in FIGS. 18 and 19 are completed. The p epitaxial layer 21 may also serve as the p ⁺ contact region 6b. In this case, the ion implantation step of the p-type impurity (FIG. 78) for forming the p ⁺ contact region 6b can be omitted. The gate electrode 8 may be formed with a length corresponding to the surface portion (channel formation portion) of the p epitaxial layer 22 between the n ⁺ source region 6a and the n ⁻ extended drain region 2, but in FIG. It is formed up to the vicinity of the opening end of the trench 4 and is formed to extend from the channel forming portion. This extended part acts as a field plate.

According to the third embodiment, the same effect as in the second embodiment can be obtained. Further, according to the third embodiment, since the concentration gradient of the pn junction formed by the p epitaxial layer 21 and the n ⁻ epitaxial layer 22 is steep, FIG. 23 shows a potential curve (shown by a broken line) at the time of avalanche breakdown. Thus, the electric field concentrates at the junction interface (indicated by “H” in FIG. 23) between the p epitaxial layer 21 and the n ⁻ epitaxial layer 22. On the other hand, since the concentration of n ⁻ epitaxial layer 22 is uniform, the electric field tends to spread at the interface between gate oxide film 7 and n ⁻ epitaxial layer 22 (indicated by “I” in FIG. 23). Alleviated. Therefore, in FIG. 23, since breakdown occurs in the region indicated by “H” in the bulk region, the reliability is greatly improved as compared with the conventional TLPM / S (see FIGS. 66 and 107).

Embodiment 4 FIG.
24 and 25 are cross-sectional views showing the configuration of the TLPM / S according to the fourth embodiment of the present invention. 24 and 25 show cross-sectional configurations of the active region and the base pickup region, respectively. The number of trenches is one. As shown in these drawings, the fourth embodiment is obtained by dividing the p epitaxial layer into the first p epitaxial layer 21a and the second p epitaxial layer 21b in the third embodiment. Here, the concentration of the first p epitaxial layer 21a and the concentration of the second p epitaxial layer 21b are generally different and can be adjusted independently.

A first p epitaxial layer 21 a is provided on the p ⁻ silicon substrate 1. A second p epitaxial layer 21b having a uniform concentration is provided in the first p epitaxial layer 21a. An n ⁻ epitaxial layer 22 is provided on the first p epitaxial layer 21a and the second p epitaxial layer 21b. Trench 4 passes through n ⁻ epitaxial layer 22 and reaches second p epitaxial layer 21b. The n ⁺ source region 6a provided at the bottom of the trench 4 in the active region is provided in the second p epitaxial layer 21b. Similarly, the p ⁺ contact region 6b provided at the bottom of the trench 4 in the base pickup region is provided in the second p epitaxial layer 21b.

Other configurations are the same as those of the third embodiment. In the illustrated example, the trench 4 is deeper than the n ⁻ epitaxial layer 22, but the bottom of the trench 4 may just reach the second p epitaxial layer 21 b. In the fourth embodiment, the first p epitaxial layer 21a and the second p epitaxial layer 21b correspond to a first first conductivity type impurity layer and a second first conductivity type impurity layer, respectively. A combination of the first p epitaxial layer 21a and the second p epitaxial layer 21b corresponds to the first conductivity type semiconductor layer.

24 and 25, it is desirable that the concentration of the first p epitaxial layer 21a is higher than the concentration of the second p epitaxial layer 21b. This is for the purpose of avalanche breakdown at the junction interface between the first p epitaxial layer 21a and the n ⁻ epitaxial layer 22, that is, in the bulk region. For example, the concentration of the first p epitaxial layer 21a is 1.3 × 10 ¹⁷ cm ⁻³ , the concentration of the second p epitaxial layer 21b is 7 × 10 ¹⁶ cm ^−3, and the concentration of the n ⁻ epitaxial layer 22 is It may be 3 × 10 ¹⁶ cm ⁻³ .

In this case, a device having a threshold voltage of about 1.4 V, an off breakdown voltage of about 30 V, and an on breakdown voltage of about 30 V can be obtained. However, when the concentration of the first p epitaxial layer 21a is 5 × 10 ¹⁶ cm ⁻³ or less, punch-through occurs and it becomes difficult to exhibit sufficient characteristics.

A method for manufacturing TLPM / S having the configuration shown in FIGS. 24 and 25 will be described. First, according to the process shown in FIGS. 8 to 10, third trench 4c is formed in first p epitaxial layer 21a using mask oxide film 3a as a mask. Thereafter, in the same manner as the process shown in FIGS. 11 to 15, the first trench 4a (which becomes the trench 4 in FIGS. 24 and 25) is formed. However, not the n ⁻ epitaxial layer 22 but the second p epitaxial layer 21b serving as a channel region is grown in the third trench 4c.

In addition, the surface of the first p epitaxial layer 21a and the second p epitaxial layer 21b (in FIG. 13, the first p epitaxial layer 21a and the n ⁻ epitaxial layer 22) is not the second p epitaxial layer 21b. Then, the n ⁻ epitaxial layer 22 to be the extended drain region is grown. The process so far is common to the active region and the base pickup region.

Thereafter, according to the process shown in FIGS. 72 to 90, the gate oxide film 7, the gate electrode 8, the n ⁺ source region 6a, the p ⁺ contact region 6b, the first interlayer insulating film 9, the buried electrode 10, and the third electrode Interlayer insulating film 11, source electrode 12 and drain electrode 13 are formed. However, in the third embodiment, the channel concentration is adjusted by the impurity concentration of the second p epitaxial layer 21b without forming the P base region. Therefore, in the process shown in FIGS. 74 to 75, the ion implantation step and the diffusion step of the p-type impurity for forming the P base region can be omitted.

As described above, the devices shown in FIGS. 24 and 25 are completed. The p epitaxial layer 21 may also serve as the p ⁺ contact region 6b. In this case, the ion implantation step of the p-type impurity (FIG. 78) for forming the p ⁺ contact region 6b can be omitted. According to the fourth embodiment, the same effect as in the second embodiment can be obtained.

Embodiment 5. FIG.
FIG. 26: is sectional drawing which shows the structure of TLPM / D concerning Embodiment 5 of this invention. The number of trenches is two. As shown in FIG. 26, in the fifth embodiment, the first trench 4a (the trench 4 in the first embodiment) in the n ⁻ extended drain region 2 in the first embodiment is formed at the bottom of the first trench 4a. A second trench 4 b having a width wider than that of the trench 4 a is provided, and the second trench 4 b is filled with a second interlayer insulating film 15 a thicker than the gate oxide film 7. An n ⁺ drain region 16 is provided at the bottom of the second trench 4b. The n ⁺ drain region 16 is surrounded by the n ⁻ extended drain region 2. The buried electrode 10 penetrates the first interlayer insulating film 9 and the second interlayer insulating film 15a, and is electrically connected to the n ⁺ drain region 16 at the bottom of the second trench 4b. Other configurations are the same as those in the first embodiment.

In the configuration shown in FIG. 26, in order to obtain a withstand voltage of 60 V or more, it is desirable that the depth of the first trench 4a is about 4 μm, for example, and the thickness of the second interlayer insulating film 15a is about 1 μm, for example. . Regarding the profile, for example, the concentration of the p epitaxial layer 21 is 1 × 10 ¹⁷ cm ^−3, and the surface concentration of the n ⁻ extended drain region 2 is 2.5 × 10 ^{16 to} 5 × 10 ¹⁶ cm ⁻³ . The diffusion length is preferably about 3 μm. In this case, a device having an off breakdown voltage of about 65 to 80 V and an on breakdown voltage of 60 V or more can be obtained.

  A method of manufacturing TLPM / D having the configuration shown in FIG. 26 will be described. First, according to the process shown in FIGS. 2 to 4, first trench 4 a (corresponding to trench 4 in FIG. 4) is formed in p epitaxial layer 21 using mask oxide film 3 as a mask. Next, similarly to the conventional TLPM / D having a two-stage trench structure, the process shown in FIGS. 92 to 99 and the subsequent processes shown in FIGS. 61 to 65 are followed. However, in the fifth embodiment, the channel concentration is adjusted by the impurity concentration of the p epitaxial layer 21 without forming the P base region. Therefore, in the processes shown in FIGS. 62 to 63, the ion implantation step and the diffusion step of the p-type impurity for forming the P base region can be omitted. As described above, the device shown in FIG. 26 is completed. According to the fifth embodiment, a TLPM having a higher breakdown voltage than that of the first embodiment can be obtained.

Embodiment 6 FIG.
FIG. 27 is a cross-sectional view showing the configuration of the TLPM / D according to the sixth embodiment of the present invention. The number of trenches is two. As shown in FIG. 27, in the sixth embodiment, the first trench is formed at the bottom of first trench 4a (trench 4 in the second embodiment) in n ⁻ epitaxial layer 22 in the second embodiment. A second trench 4 b having a width wider than 4 a is provided, and the second trench 4 b is filled with a second interlayer insulating film 15 a thicker than the gate oxide film 7. An n ⁺ drain region 16 is provided at the bottom of the second trench 4b. The n ⁺ drain region 16 is surrounded by the n ⁻ epitaxial layer 22. The buried electrode 10 penetrates the first interlayer insulating film 9 and the second interlayer insulating film 15a, and is electrically connected to the n ⁺ drain region 16 at the bottom of the second trench 4b. Other configurations are the same as those of the second embodiment.

In the configuration shown in FIG. 27, in order to obtain a withstand voltage of 60 V or more, it is desirable that the depth of the first trench 4a is about 4 μm, for example, and the thickness of the second interlayer insulating film 15a is about 1 μm, for example. . Regarding the profile, for example, the concentration of the first p epitaxial layer 21a and the second p epitaxial layer 21b is 1 × 10 ¹⁷ cm ^−3, and the concentration of the n ⁻ epitaxial layer 22 is 8 × 10 ¹⁵ to 1 ×. 10 ¹⁶ cm ^-3 is recommended. In this case, a device having a threshold voltage of about 2.0 V, an off breakdown voltage of about 65 to 80 V, and an on breakdown voltage of 60 V or more can be obtained.

Alternatively, the concentration of the second p epitaxial layer 21b may be lower than the concentration of the first p epitaxial layer 21a. For example, in the above-described concentration, only the concentration of the second p epitaxial layer 21b may be 5 × 10 ¹⁶ cm ⁻³ . In this case, a device having a threshold voltage of about 1.2 V can be obtained without reducing the on-breakdown voltage and the off-breakdown voltage.

  A method for manufacturing TLPM / D having the configuration shown in FIG. 27 will be described. First, the process shown in FIGS. 8 to 16 is followed as in the second embodiment. At that time, in the process shown in FIG. 15, the first trench 4a penetrates through the second p epitaxial layer 21b and becomes deeper than the second p epitaxial layer 21b. Next, as shown in FIG. 28, a nitride film 109 is deposited further inside the oxide film 110 formed on the inner wall of the first trench 4a. Then, as shown in FIG. 29, the nitride film 109 is etched to leave the nitride film 109 only on the side wall portion of the first trench 4a. Next, as shown in FIG. 30, oxide film 110 on the surface of second p epitaxial layer 21b is removed, and second trench 4b is formed at the bottom of first trench 4a using nitride film 109 as a mask. .

  Next, as shown in FIG. 31, a second interlayer insulating film 15a is formed on the bottom surface of the second trench 4b and the outer surface of the opening end of the first trench 4a. Next, as shown in FIG. 32, the nitride film 109 and the oxide film 110 are removed. Then, a gate oxide film 7 is formed on the side wall of the first trench 4a. Thereafter, polysilicon to be the gate electrode 8 is deposited. Next, the process shown in FIGS. 97 to 99 and the subsequent processes shown in FIGS. 61 to 65 are followed in the same manner as the conventional TLPM / D having a two-stage trench structure. However, in the sixth embodiment, the channel concentration is adjusted by the impurity concentration of the p epitaxial layer 21b without forming the P base region. Therefore, in the processes shown in FIGS. 62 to 63, the ion implantation step and the diffusion step of the p-type impurity for forming the P base region can be omitted. As described above, the device shown in FIG. 27 is completed. According to the sixth embodiment, a TLPM having a higher breakdown voltage than that of the second embodiment can be obtained.

Embodiment 7 FIG.
33 and 34 are cross-sectional views showing the configuration of the TLPM / S according to the seventh embodiment of the present invention. 33 and 34 show cross-sectional configurations of the active region and the base pickup region, respectively. The number of trenches is two. As shown in these drawings, in the seventh embodiment, gate oxidation is performed on the side of the first trench 4a (trench 4 in the third embodiment) in the n ⁻ epitaxial layer 22 in the third embodiment. A second interlayer insulating film 15b thicker than the film 7 is provided. The second interlayer insulating film 15b is, n ^- a first width wider than the trench 4a in the epitaxial layer 22, and the n ^- buried in the second trench 4b formed shallower than the epitaxial layer 22 Yes. Other configurations are the same as those of the third embodiment.

In the configuration shown in FIGS. 33 and 34, in order to obtain a withstand voltage of 60 V or higher, the depth of the first trench 4a on the basis of the opening end substrate surface of the trench 4b is set to 5 μm or more, for example. The overlap amount with the second interlayer insulating film 15b is desirably 4 μm or more. In order to prevent punch through, the channel length is desirably 0.4 μm or more. Regarding the profile, for example, the concentration of the p epitaxial layer 21 may be 1 × 10 ¹⁷ cm ⁻³ and the concentration of the n ⁻ epitaxial layer 22 may be 8 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ⁻³ . In this case, a device having a threshold voltage of about 2.0 V, an off breakdown voltage of about 65 to 83 V, and an on breakdown voltage of about 60 to 80 V can be obtained.

A method of manufacturing TLPM / S having the configuration shown in FIGS. 33 and 34 will be described. First, the process shown in FIGS. 20 to 21 is followed as in the third embodiment. After removing the photoresist 101, a second trench 4b shallower than the n ⁻ epitaxial layer 22 is formed using the mask oxide film 3 as a mask, as shown in FIG. Next, as shown in FIG. 36, a second interlayer insulating film 15b is deposited. Then, as shown in FIG. 37, the second interlayer insulating film 15b is etched to leave the second interlayer insulating film 15b only on the side wall portion of the second trench 4b.

Next, as shown in FIG. 38, the bottom of second trench 4b is etched using second interlayer insulating film 15b as a mask to form first trench 4a having a narrower width than second trench 4b. To do. First trench 4 a penetrates n ⁻ epitaxial layer 22 and reaches p epitaxial layer 21. In the illustrated example, the first trench 4 a is deeper than the n ⁻ epitaxial layer 22, but the bottom of the first trench 4 a may have just reached the p epitaxial layer 21. Thereafter, as shown in FIG. 39, a buffer oxide film 102 is formed inside the first trench 4a. The process so far is common to the active region and the base pickup region.

  Thereafter, the process shown in FIGS. 72 to 90 is followed. However, in the seventh embodiment, the channel concentration is adjusted by the impurity concentration of the p epitaxial layer 21 without forming the P base region. Therefore, in the process shown in FIGS. 74 to 75, the ion implantation step and the diffusion step of the p-type impurity for forming the P base region can be omitted. As described above, the devices shown in FIGS. 33 and 34 are completed.

The p epitaxial layer 21 may also serve as the p ⁺ contact region 6b. In this case, the ion implantation step of the p-type impurity (FIG. 78) for forming the p ⁺ contact region 6b can be omitted. According to the seventh embodiment, a TLPM having a higher breakdown voltage than that of the third embodiment can be obtained.

Embodiment 8 FIG.
40 and 41 are cross-sectional views showing the configuration of the TLPM / S according to the eighth embodiment of the present invention. 40 and 41 show cross-sectional configurations of the active region and the base pickup region, respectively. The number of trenches is two. As shown in these drawings, in the eighth embodiment, gate oxidation is performed on the side of the first trench 4a (trench 4 in the fourth embodiment) in the n ⁻ epitaxial layer 22 in the fourth embodiment. A second interlayer insulating film 15b thicker than the film 7 is provided. The second interlayer insulating film 15b is, n ^- a first width wider than the trench 4a in the epitaxial layer 22, and the n ^- buried in the second trench 4b formed shallower than the epitaxial layer 22 Yes. Other configurations are the same as those in the fourth embodiment.

A method of manufacturing TLPM / S having the configuration shown in FIGS. 40 and 41 will be described. First, as in the fourth embodiment, the process shown in FIGS. However, in the process shown in FIG. 11, not the n ⁻ epitaxial layer 22 but the second p epitaxial layer 21b serving as a channel region is grown in the third trench 4c. In the process shown in FIG. 13, the surface of the first p epitaxial layer 21a and the second p epitaxial layer 21b (in FIG. 13, the first p epitaxial layer 21a and the n ⁻ epitaxial layer 22) are not Instead of the p epitaxial layer 21b, an n ⁻ epitaxial layer 22 to be an extended drain region is grown.

After removing the photoresist 101, a second trench 4b shallower than the n ⁻ epitaxial layer 22 is formed using the mask oxide film 3 as a mask, as shown in FIG. Next, as shown in FIG. 43, a second interlayer insulating film 15b is deposited. Then, as shown in FIG. 44, the second interlayer insulating film 15b is etched to leave the second interlayer insulating film 15b only on the side wall portion of the second trench 4b. Next, as shown in FIG. 45, the bottom of second trench 4b is etched using second interlayer insulating film 15b as a mask to form first trench 4a having a narrower width than second trench 4b. To do.

First trench 4a passes through n ⁻ epitaxial layer 22 and reaches second p epitaxial layer 21b. In the illustrated example, the first trench 4a is deeper than the n ⁻ epitaxial layer 22. However, the bottom of the first trench 4a may just reach the second p epitaxial layer 21b. Thereafter, a buffer oxide film 102 is formed inside the first trench 4a. The process so far is common to the active region and the base pickup region.

  Thereafter, the process shown in FIGS. 72 to 90 is followed. However, in the eighth embodiment, the channel concentration is adjusted by the impurity concentration of the second p epitaxial layer 21b without forming the P base region. Therefore, in the process shown in FIGS. 74 to 75, the ion implantation step and the diffusion step of the p-type impurity for forming the P base region can be omitted. As described above, the devices shown in FIGS. 40 and 41 are completed.

The second p epitaxial layer 21b can also serve as the p ⁺ contact region 6b. In this case, the ion implantation step of the p-type impurity (FIG. 78) for forming the p ⁺ contact region 6b can be omitted. According to the eighth embodiment, a TLPM having a higher breakdown voltage than that of the fourth embodiment can be obtained.

Embodiment 9 FIG.
FIG. 46 is a sectional view showing the configuration of the semiconductor device according to the ninth embodiment of the present invention. As shown in FIG. 46, in the ninth embodiment, the n-channel TLPM / D of the first embodiment and the p-channel TLPM / D having the same structure and different conductivity types are integrated. The configuration of the p-channel TLPM / D located on the right side in FIG. 46 is the same as that in the description of the first embodiment in that n ⁻ extended drain region 2, trench 4, n ⁺ source region 6 a, p ⁺ contact region 6 b, and gate oxide film 7. , Gate electrode 8, first interlayer insulating film 9, buried electrode 10, source electrode 12, drain electrode 13, n ⁺ drain region 16, and p epitaxial layer 21, p ⁻ extended drain region 202, trench 204, p ⁺ , respectively. Source region 206a, n ⁺ contact region 206b, gate oxide film 207, gate electrode 208, first interlayer insulating film 209, buried electrode 210, source electrode 212, drain electrode 213, p ⁺ drain region 216 and n epitaxial layer 221 It has been replaced.

A method for manufacturing the semiconductor device having the structure shown in FIG. 46 will be described. First, an oxide film is deposited on the p ⁻ silicon substrate 1 and the oxide film is partially etched to expose the p ⁻ silicon substrate 1 partially. Next, a p epitaxial layer 21 is grown on the exposed surface of the p ⁻ silicon substrate 1. Subsequently, the oxide film remaining on the surface of the p ⁻ silicon substrate 1 is etched to expose the remaining portion of the p ⁻ silicon substrate 1. Then, an n epitaxial layer 221 is grown on the exposed surface of the p ⁻ silicon substrate 1. Thereafter, according to the manufacturing process of the first embodiment, n-channel TLPM / D and p-channel TLPM / D shown in FIG. 46 are formed in p epitaxial layer 21 and n epitaxial layer 221, respectively.

  Note that, in the n-channel TLPM / D and the p-channel TLPM / D, the respective trenches 4, 204, the respective gate oxide films 7, 207, the polysilicon serving as the respective gate electrodes 8, 208, and the respective first layers The insulating films 9, 209, the respective buried electrodes 10, 210, or the respective source and drain electrodes 12, 13, 212, 213 may be formed simultaneously. By doing so, the number of steps is reduced, so that the cost can be reduced.

Embodiment 10 FIG.
FIG. 47 is a cross-sectional view showing the configuration of the semiconductor device according to the tenth embodiment of the present invention. As shown in FIG. 47, in the tenth embodiment, the n-channel TLPM / D of the second embodiment and the p-channel TLPM / D having the same structure and different conductivity types are integrated. 47, the structure of the p-channel TLPM / D located on the right side in the description of the second embodiment is the trench 4, n ⁺ source region 6a, p ⁺ contact region 6b, gate oxide film 7, gate electrode 8, first Interlayer insulating film 9, buried electrode 10, source electrode 12, drain electrode 13, n ⁺ drain region 16, first p epitaxial layer 21 a, second p epitaxial layer 21 b and n ⁻ epitaxial layer 22. , P ⁺ source region 206a, n ⁺ contact region 206b, gate oxide film 207, gate electrode 208, first interlayer insulating film 209, buried electrode 210, source electrode 212, drain electrode 213, p ⁺ drain region 216, first N epitaxial layer 221a, second n epitaxial layer 221b and p ^- epitaxy This is replaced with the layer 222.

A method for manufacturing the semiconductor device having the structure shown in FIG. 47 will be described. First, the p epitaxial layer 21 and the n epitaxial layer 221 are formed on the p ⁻ silicon substrate 1 in the same manner as in the ninth embodiment. Thereafter, according to the manufacturing process of the second embodiment, n-channel TLPM / D and p-channel TLPM / D shown in FIG. 47 are formed in p epitaxial layer 21 and n epitaxial layer 221, respectively.

  Note that, in the n-channel TLPM / D and the p-channel TLPM / D, the respective trenches 4, 204, the respective gate oxide films 7, 207, the polysilicon serving as the respective gate electrodes 8, 208, and the respective first layers The insulating films 9, 209, the respective buried electrodes 10, 210, or the respective source and drain electrodes 12, 13, 212, 213 may be formed simultaneously. By doing so, the number of steps is reduced, so that the cost can be reduced.

Embodiment 11 FIG.
48 and 49 are cross-sectional views showing the configuration of the semiconductor device according to Embodiment 11 of the present invention. 48 and 49 show cross-sectional configurations of the active region and the base pickup region, respectively. As shown in these drawings, in the eleventh embodiment, the n-channel TLPM / S of the third embodiment and the p-channel TLPM / S having the same structure and different conductivity types are integrated.

48 and 49, the structure of the p-channel TLPM / S located on the right side in the description of the third embodiment is the trench 4, n ⁺ source region 6a, p ⁺ contact region 6b, gate oxide film 7, and gate electrode 8. , First interlayer insulating film 9, buried electrode 10, source electrode 12, drain electrode 13, n ⁺ drain region 16, p epitaxial layer 21 and n ⁻ epitaxial layer 22 are formed as trench 204, p ⁺ source region 206a, n, respectively. ⁺ Contact region 206b, gate oxide film 207, gate electrode 208, first interlayer insulating film 209, buried electrode 210, source electrode 212, drain electrode 213, p ⁺ drain region 216, n epitaxial layer 221 and p ⁻ epitaxial layer 222 Is read as However, n ⁻ epitaxial layer 22 and p ⁻ epitaxial layer 222 are embedded in fourth trenches 4 d and 204 d formed in p epitaxial layer 21 and n epitaxial layer 221, respectively.

A method for manufacturing the semiconductor device having the structure shown in FIGS. 48 and 49 will be described. First, the p epitaxial layer 21 and the n epitaxial layer 221 are formed on the p ⁻ silicon substrate 1 in the same manner as in the ninth embodiment. Thereafter, fourth trenches 4 d and 204 d are formed in the p epitaxial layer 21 and the n epitaxial layer 221. Then, an n ⁻ epitaxial layer 22 is grown in the fourth trench 4 d of the p epitaxial layer 21. Further, the p ⁻ epitaxial layer 222 is grown in the fourth trench 204 d of the n epitaxial layer 221.

  Thereafter, for each of the n-channel TLPM / S and the p-channel TLPM / S, the process shown in FIGS. 21 to 22 is followed, and then the process shown in FIGS. 72 to 90 is followed. However, in the eleventh embodiment, the channel concentration is adjusted by the impurity concentration of the p epitaxial layer 21 and the n epitaxial layer 221 without forming the P base region and the N base region. Therefore, in the process shown in FIGS. 74 to 78, the ion implantation process and the diffusion process of the p-type impurity for forming the P base region, and the ion implantation process and the diffusion process of the n-type impurity for forming the N base region. Can be omitted. As described above, the devices shown in FIGS. 48 and 49 are completed.

Incidentally, there is a p ⁺ source region 206a at the bottom of the trench 204 in the n epitaxial layer 221 in the active region (FIG. 48), the bottom of the trench 4 in the p epitaxial layer 21 in the base pick-up region (Fig. 49) p ⁺ The contact region 6b can be formed by patterning the same mask. Similarly, n ⁺ source region 6a at the bottom of trench 4 in p epitaxial layer 21 in the active region (FIG. 48) and n at the bottom of trench 204 in n epitaxial layer 221 in the base pickup region (FIG. 49). ⁺ Contact region 206b can be formed by patterning the same mask. In the base pickup region (FIG. 49), the p epitaxial layer 21 may also serve as the p ⁺ contact region 6b, or the n epitaxial layer 221 may serve as the n ⁺ contact region 206b.

Embodiment 12 FIG.
FIG. 50 is a cross-sectional view showing the configuration of the semiconductor device according to the twelfth embodiment of the present invention. As shown in FIG. 50, in the twelfth embodiment, TLPM (the left end in the figure), a planar p-channel MOSFET (the center in the figure), and a planar n-channel MOSFET (the right end in the figure) are integrated. . In the illustrated example, the TLPM of the first embodiment is integrated, but any TLPM of the second to eighth embodiments may be integrated. The structure of a planar type MOSFET is well known. In this specification, a planar MOSFET is a low breakdown voltage logic device and does not include a power MOSFET.

A method for manufacturing the semiconductor device having the structure shown in FIG. 50 will be described. First, p epitaxial layers 21 and 321 and n epitaxial layers 421 are alternately formed on a p ⁻ silicon substrate 1. Then, for example, in FIG. 50, the TLPM according to any one of the first to eighth embodiments is formed in the leftmost p epitaxial layer 21, and the planar n-channel MOSFET is formed in the rightmost p epitaxial layer 321. In FIG. 50, a planar type p-channel MOSFET is formed in the central n epitaxial layer 421. At that time, the n ⁺ source region 306a and n ⁺ drain region 316 of the planar n-channel MOSFET and the n ⁺ source region 6a of TLPM may be formed by patterning the same mask. By doing so, the number of masks can be saved, and the cost can be reduced.

The p-channel TLPM, in the case where the integrated with planar p-channel MOSFET and a planar type of n-channel MOSFET of the planar type of p-channel MOSFET and the p ⁺ source region 406a and a p ⁺ drain region 416, the TLPM p ⁺ The source region may be formed by patterning the same mask. Further, the source electrode 12 and the drain electrode 13 of TLPM, the source electrode 312 and the drain electrode 313 of the planar type n-channel MOSFET, and the source electrode 412 and the drain electrode 413 of the planar type p-channel MOSFET may be formed simultaneously. . In FIG. 50, reference numerals 308 and 408 denote the gate electrodes of the planar MOSFETs.

Embodiment 13 FIG.
FIG. 51 is a cross-sectional view showing the configuration of the semiconductor device according to the thirteenth embodiment of the present invention. As shown in FIG. 51, the thirteenth embodiment includes a semiconductor device of the ninth embodiment (second from the left end and the left in the figure), a planar n-channel MOSFET (second from the right in the figure), and a planar type p. The channel MOSFET (the right end of the figure) is integrated. In the illustrated example, the semiconductor device of the ninth embodiment is integrated, but the semiconductor device of the tenth or eleventh embodiment may be integrated. The structure of a planar type MOSFET is well known.

A method for manufacturing the semiconductor device having the structure shown in FIG. 51 will be described. First, p epitaxial layers 21 and 321 and n epitaxial layers 221 and 421 are alternately formed on a p ⁻ silicon substrate 1. Then, for example, the n-channel TLPM according to any one of the first to eighth embodiments is formed in the leftmost p epitaxial layer 21 in FIG. Then, in the second n epitaxial layer 221 from the left in FIG. 51, a p-channel TLPM having the same structure as that of any of the n-channel TLPMs of the first to eighth embodiments and having a different conductivity type is manufactured. Further, in FIG. 51, a planar n-channel MOSFET is fabricated in the second p epitaxial layer 321 from the right, and a planar p-channel MOSFET is fabricated in the n epitaxial layer 421 at the right end of FIG.

At this time, the n ⁺ source region 306a and the n ⁺ drain region 316 of the planar n-channel MOSFET and the n ⁺ source region 6a of the n-channel TLPM may be formed by patterning the same mask. Further, the planar type p-channel MOSFET and the p ⁺ source region 406a and a p ⁺ drain region 416, a p ⁺ source region of the p-channel TLPM, may be formed by patterning the same mask. By doing so, the number of masks can be saved, and the cost can be reduced.

  In addition, the source electrode 12 and the drain electrode 13 of the n-channel TLPM, the source electrode 212 and the drain electrode 213 of the P-channel TLPM, the source electrode 312 and the drain electrode 313 of the planar n-channel MOSFET, and the planar p-channel MOSFET The source electrode 412 and the drain electrode 413 may be formed at the same time.

As described above, the present invention is not limited to the above-described embodiments, and various modifications can be made. For example, in the form 2 to 13 embodiment, as in the first embodiment, p ^- in place of the silicon substrate 1, n ^- it may be a silicon substrate. In this case, each of the embodiments, n ^- other configurations except for the silicon substrate, p ^- is the same as the case of using the silicon substrate 1. The manufacturing method, n ^- that use a silicon substrate is only different, otherwise p ^- is the same as when using a silicon substrate 1. Further, even when an n ⁻ silicon substrate is used, the same effect as when the p ⁻ silicon substrate 1 is used can be obtained.

  Furthermore, in the first to eighth embodiments, the twelfth and thirteenth embodiments, the p-type and n-type of each semiconductor region or semiconductor layer may be reversed. Furthermore, in the ninth to eleventh embodiments, the n-channel TLPM in any of the first to eighth embodiments and the n-channel TLPM in any of the first to eighth embodiments have the same structure and conductivity type. P-channel TLPMs having different values may be integrated. Further, in the ninth to eleventh embodiments, even if any n-channel TLPM in the first to eighth embodiments and any n-channel TLPM in the first to eighth embodiments are integrated. Good.

  Further, in the ninth to eleventh embodiments, a p-channel TLPM having the same structure as that of any n-channel TLPM in the first to eighth embodiments and having a different conductivity type, and any one of the first to eighth embodiments. A p-channel TLPM having the same structure as that of the n-channel TLPM and having a different conductivity type may be integrated. Furthermore, in Embodiments 1 to 13, a part or all of the epitaxial layer may be replaced with an impurity layer having a uniform concentration other than the epitaxial layer.

  As described above, the semiconductor device and the manufacturing method thereof according to the present invention are useful for a low on-resistance power MOSFET suitable for an integrated circuit that controls a large current with a high breakdown voltage, and in particular, an IC for a switching power supply, an automobile power system Suitable for power MOSFETs integrated in driving ICs, flat panel display driving ICs, and the like.

It is sectional drawing which shows the structure of TLPM / D of the 1 step | paragraph trench structure concerning Embodiment 1 of this invention. It is sectional drawing which shows the state in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the state in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the state in the middle of manufacture of TLPM shown in FIG. It is a figure which shows the potential distribution of the principal part when making TLPM / D shown in FIG. 1 yield avalanche. It is sectional drawing which shows the other structure of TLPM / D of the 1 step | paragraph trench structure concerning Embodiment 1 of this invention. It is sectional drawing which shows the structure of TLPM / D of the 1 step | paragraph trench structure concerning Embodiment 2 of this invention. It is sectional drawing which shows the state in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the state in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the state in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the state in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the state in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the state in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the state in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the state in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the state in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the state in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the structure of the active region of TLPM / S of the 1 step | paragraph trench structure concerning Embodiment 3 of this invention. It is sectional drawing which shows the structure of the pick-up area | region of TLPM / S of the 1 step | paragraph trench structure concerning Embodiment 3 of this invention. It is sectional drawing which shows the state in the middle of manufacture of TLPM shown in FIG. 18 and FIG. It is sectional drawing which shows the state in the middle of manufacture of TLPM shown in FIG. 18 and FIG. It is sectional drawing which shows the state in the middle of manufacture of TLPM shown in FIG. 18 and FIG. It is a figure which shows the potential distribution of the principal part when making TLPM / S shown in FIG. 18 avalanche yield. It is sectional drawing which shows the structure of the active region of TLPM / S of the 1 step | paragraph trench structure concerning Embodiment 4 of this invention. It is sectional drawing which shows the structure of the pick-up area | region of TLPM / S of the 1 step | paragraph trench structure concerning Embodiment 4 of this invention. It is sectional drawing which shows the structure of TLPM / D of the two-step trench structure concerning Embodiment 5 of this invention. It is sectional drawing which shows the structure of TLPM / D of the two-step trench structure concerning Embodiment 6 of this invention. It is sectional drawing which shows the state in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the state in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the state in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the state in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the state in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the structure of the active region of TLPM / S of the two-step trench structure concerning Embodiment 7 of this invention. It is sectional drawing which shows the structure of the pick-up area | region of TLPM / S of the two-step trench structure concerning Embodiment 7 of this invention. It is sectional drawing which shows the state in the middle of manufacture of TLPM shown in FIG.33 and FIG.34. It is sectional drawing which shows the state in the middle of manufacture of TLPM shown in FIG.33 and FIG.34. It is sectional drawing which shows the state in the middle of manufacture of TLPM shown in FIG.33 and FIG.34. It is sectional drawing which shows the state in the middle of manufacture of TLPM shown in FIG.33 and FIG.34. It is sectional drawing which shows the state in the middle of manufacture of TLPM shown in FIG.33 and FIG.34. It is sectional drawing which shows the structure of the active region of TLPM / S of the two-step trench structure concerning Embodiment 8 of this invention. It is sectional drawing which shows the structure of the pick-up area | region of TLPM / S of the two-step trench structure concerning Embodiment 8 of this invention. It is sectional drawing which shows the state in the middle of manufacture of TLPM shown in FIG. 40 and FIG. It is sectional drawing which shows the state in the middle of manufacture of TLPM shown in FIG. 40 and FIG. It is sectional drawing which shows the state in the middle of manufacture of TLPM shown in FIG. 40 and FIG. It is sectional drawing which shows the state in the middle of manufacture of TLPM shown in FIG. 40 and FIG. It is sectional drawing which shows the structure of the semiconductor device concerning Embodiment 9 of this invention. It is sectional drawing which shows the structure of the semiconductor device concerning Embodiment 10 of this invention. It is sectional drawing which shows the structure of the active region of the semiconductor device concerning Embodiment 11 of this invention. It is sectional drawing which shows the structure of the pick-up area | region of the semiconductor device concerning Embodiment 11 of this invention. It is sectional drawing which shows the structure of the semiconductor device concerning Embodiment 12 of this invention. It is sectional drawing which shows the structure of the semiconductor device concerning Embodiment 13 of this invention. It is sectional drawing which shows the structure of TLPM / D of the conventional 1 step | paragraph trench structure. FIG. 53 is a cross-sectional view showing a state in the middle of manufacturing the TLPM shown in FIG. 52. FIG. 53 is a cross-sectional view showing a state in the middle of manufacturing the TLPM shown in FIG. 52. FIG. 53 is a cross-sectional view showing a state in the middle of manufacturing the TLPM shown in FIG. 52. FIG. 53 is a cross-sectional view showing a state in the middle of manufacturing the TLPM shown in FIG. 52. FIG. 53 is a cross-sectional view showing a state in the middle of manufacturing the TLPM shown in FIG. 52. FIG. 53 is a cross-sectional view showing a state in the middle of manufacturing the TLPM shown in FIG. 52. FIG. 53 is a cross-sectional view showing a state in the middle of manufacturing the TLPM shown in FIG. 52. FIG. 53 is a cross-sectional view showing a state in the middle of manufacturing the TLPM shown in FIG. 52. FIG. 53 is a cross-sectional view showing a state in the middle of manufacturing the TLPM shown in FIG. 52. FIG. 53 is a cross-sectional view showing a state in the middle of manufacturing the TLPM shown in FIG. 52. FIG. 53 is a cross-sectional view showing a state in the middle of manufacturing the TLPM shown in FIG. 52. FIG. 53 is a cross-sectional view showing a state in the middle of manufacturing the TLPM shown in FIG. 52. FIG. 53 is a cross-sectional view showing a state in the middle of manufacturing the TLPM shown in FIG. 52. It is sectional drawing which shows the structure of the active region of TLPM / S of the conventional 1 step | paragraph trench structure. It is sectional drawing which shows the structure of the pick-up area | region of the conventional TLPM / S of 1 step | paragraph trench structure. FIG. 68 is a cross-sectional view showing a state in the middle of manufacturing the TLPM shown in FIGS. 66 and 67. FIG. 68 is a cross-sectional view showing a state in the middle of manufacturing the TLPM shown in FIGS. 66 and 67. FIG. 68 is a cross-sectional view showing a state in the middle of manufacturing the TLPM shown in FIGS. 66 and 67. FIG. 68 is a cross-sectional view showing a state in the middle of manufacturing the TLPM shown in FIGS. 66 and 67. FIG. 68 is a cross-sectional view showing a state in the middle of manufacturing the TLPM shown in FIGS. 66 and 67. FIG. 68 is a cross-sectional view showing a state in the middle of manufacturing the TLPM shown in FIGS. 66 and 67. FIG. 68 is a cross-sectional view showing a state in the middle of manufacturing the TLPM shown in FIGS. 66 and 67. FIG. 67 is a cross-sectional view showing a state in the middle of manufacturing the TLPM shown in FIG. 66. FIG. 68 is a cross-sectional view showing a state in the middle of manufacturing the TLPM shown in FIG. 67. FIG. 67 is a cross-sectional view showing a state in the middle of manufacturing the TLPM shown in FIG. 66. FIG. 68 is a cross-sectional view showing a state in the middle of manufacturing the TLPM shown in FIG. 67. FIG. 67 is a cross-sectional view showing a state in the middle of manufacturing the TLPM shown in FIG. 66. FIG. 68 is a cross-sectional view showing a state in the middle of manufacturing the TLPM shown in FIG. 67. FIG. 67 is a cross-sectional view showing a state in the middle of manufacturing the TLPM shown in FIG. 66. FIG. 68 is a cross-sectional view showing a state in the middle of manufacturing the TLPM shown in FIG. 67. FIG. 67 is a cross-sectional view showing a state in the middle of manufacturing the TLPM shown in FIG. 66. FIG. 68 is a cross-sectional view showing a state in the middle of manufacturing the TLPM shown in FIG. 67. FIG. 67 is a cross-sectional view showing a state in the middle of manufacturing the TLPM shown in FIG. 66. FIG. 68 is a cross-sectional view showing a state in the middle of manufacturing the TLPM shown in FIG. 67. FIG. 67 is a cross-sectional view showing a state in the middle of manufacturing the TLPM shown in FIG. 66. FIG. 68 is a cross-sectional view showing a state in the middle of manufacturing the TLPM shown in FIG. 67. FIG. 67 is a cross-sectional view showing a state in the middle of manufacturing the TLPM shown in FIG. 66. FIG. 68 is a cross-sectional view showing a state in the middle of manufacturing the TLPM shown in FIG. 67. It is sectional drawing which shows the structure of TLPM / D of the conventional 2 step | paragraph trench structure. It is sectional drawing which shows the state in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the state in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the state in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the state in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the state in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the state in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the state in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the state in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the structure of the active region of TLPM / S of the conventional 2 step | paragraph trench structure. It is sectional drawing which shows the structure of the pick-up area | region of TLPM / S of the conventional 2 step | paragraph trench structure. It is sectional drawing which shows the state in the middle of manufacture of TLPM shown to FIG. 100 and FIG. It is sectional drawing which shows the state in the middle of manufacture of TLPM shown to FIG. 100 and FIG. It is sectional drawing which shows the state in the middle of manufacture of TLPM shown to FIG. 100 and FIG. It is sectional drawing which shows the state in the middle of manufacture of TLPM shown to FIG. 100 and FIG. FIG. 53 is a diagram showing a potential distribution of a main part when the TLPM / D shown in FIG. 52 is avalanche yielded. FIG. 67 is a diagram showing a potential distribution of main parts when the TLPM / S shown in FIG. 66 is avalanche yielded.

Explanation of symbols

1 Semiconductor substrate (p ^- silicon substrate)
1a Semiconductor substrate (n ^- silicon substrate)
2 Third second conductivity type semiconductor region, impurity diffusion layer (n ⁻ extended drain region)
3 Mask insulation film (mask oxide film)
4 trench 4a first trench 4b second trench 4c third trench 6a second second conductivity type semiconductor region (n ⁺ source region)
7 Insulation film (gate oxide film) inside the trench
8 First electrode (gate electrode)
9 Interlayer insulating film inside first electrode, first interlayer insulating film 10 Embedded electrode 12 Third electrode (source electrode)
13 Second electrode (drain electrode)
15a, 15b Second interlayer insulating film 16 First second conductivity type semiconductor region (n ⁺ drain region)
21 1st conductivity type semiconductor layer, 1st conductivity type impurity layer (p epitaxial layer)
21a First first conductivity type impurity layer (first p epitaxial layer)
21b Second first conductivity type impurity layer (second p epitaxial layer)
22 3rd 2nd conductivity type semiconductor region, 2nd conductivity type impurity layer, 2nd conductivity type semiconductor layer (n < ^- > epitaxial layer)

Claims (22)

A first conductivity type semiconductor layer provided on a semiconductor substrate;
A first second conductivity type semiconductor region provided at the bottom of a trench formed in the first conductivity type semiconductor layer;
A second second conductivity type semiconductor region provided in a surface layer of the first conductivity type semiconductor layer adjacent to the trench;
A third second conductivity type semiconductor region provided between the first conductivity type semiconductor layer and the first second conductivity type semiconductor region;
An insulating film provided inside the trench along the side of the trench;
A first electrode provided on the surface of the first conductive type semiconductor layer between the second second conductive type semiconductor region and the third second conductive type semiconductor region via the insulating film; ,
A buried electrode connected to the first second conductivity type semiconductor region at the bottom of the trench and surrounded by an interlayer insulating film provided inside the first electrode;
A second electrode connected to the embedded electrode;
A third electrode connected to the second second conductivity type semiconductor region,
The first conductivity type semiconductor layer has a uniform impurity concentration, and the impurity concentration of the third second conductivity type semiconductor region is lower than the impurity concentration of the first second conductivity type semiconductor region. A semiconductor device.   The first second conductivity type semiconductor region is a drain region, the second second conductivity type semiconductor region is a source region, and the third second conductivity type semiconductor region is an extended drain region. 2. The semiconductor device according to claim 1, wherein the semiconductor device is a lateral field effect transistor having an insulated gate structure made of an oxide film and a semiconductor.   3. The semiconductor device according to claim 1, wherein the third second conductivity type semiconductor region is an impurity diffusion layer having a concentration distribution due to impurity diffusion.   3. The semiconductor device according to claim 1, wherein the third second conductivity type semiconductor region has a uniform impurity concentration.   The semiconductor device according to claim 1, wherein a conductivity type of the semiconductor substrate is a first conductivity type.   The semiconductor device according to claim 1, wherein a conductivity type of the semiconductor substrate is a second conductivity type. A first conductivity type semiconductor layer provided on a semiconductor substrate;
A second conductivity type semiconductor layer provided on the first conductivity type semiconductor layer;
A first second conductivity type semiconductor region provided in a surface region of the second conductivity type semiconductor layer;
A second second conductivity type semiconductor region provided at the bottom of a trench penetrating the second conductivity type semiconductor layer;
An insulating film provided inside the trench along the side of the trench;
A first electrode provided on the surface of the first conductivity type semiconductor layer between the second conductivity type semiconductor layer and the second second conductivity type semiconductor region via the insulating film;
A buried electrode connected to the second second-conductivity-type semiconductor region at the bottom of the trench and surrounded by an interlayer insulating film provided inside the first electrode;
A second electrode connected to the first second conductivity type semiconductor region;
A third electrode connected to the embedded electrode,
The first conductivity type semiconductor layer has a uniform impurity concentration, and the second conductivity type semiconductor layer has a uniform impurity concentration lower than the impurity concentration of the first second conductivity type semiconductor region. A semiconductor device.   The metal oxide film in which the first second conductivity type semiconductor region is a drain region, the second second conductivity type semiconductor region is a source region, and the second conductivity type semiconductor layer is an extended drain region. 8. The semiconductor device according to claim 7, wherein the semiconductor device is a lateral field effect transistor having an insulated gate structure made of a semiconductor.   The semiconductor device according to claim 7, wherein a conductivity type of the semiconductor substrate is a first conductivity type.   The semiconductor device according to claim 7, wherein a conductivity type of the semiconductor substrate is a second conductivity type.   11. The semiconductor according to claim 1, wherein a second interlayer insulating film thicker than the insulating film is provided inside the trench along a side portion of the trench. apparatus. Forming a first conductivity type impurity layer having a uniform impurity concentration on a semiconductor substrate;
Forming a trench in the first conductivity type impurity layer;
A step of diffusing impurities at the bottom of the trench to form a third second conductivity type semiconductor region;
Forming an insulating film inside the trench along a side of the trench;
Forming a first electrode inside the insulating film;
Forming an interlayer insulating film inside the first electrode;
Exposing the semiconductor through the interlayer insulating film at the bottom of the trench;
Forming a first second conductivity type semiconductor region at the bottom of the trench in the third second conductivity type semiconductor region;
Forming a buried electrode connected to the first second conductivity type semiconductor region at the bottom of the trench inside the interlayer insulating film;
Forming a second second conductivity type semiconductor region in a surface layer of the first conductivity type impurity layer adjacent to the trench;
Forming a second electrode connected to the embedded electrode and a third electrode connected to the second second conductivity type semiconductor region;
In order. Forming a first first conductivity type impurity layer having a uniform impurity concentration on a semiconductor substrate;
Forming a third trench in the first first conductivity type impurity layer;
Forming a second conductivity type impurity layer having a uniform impurity concentration inside the third trench;
Forming a second first conductivity type impurity layer having a uniform impurity concentration on the first first conductivity type impurity layer and the second conductivity type impurity layer;
Forming a first trench penetrating the second first conductivity type impurity layer with a width narrower than that of the third trench;
Forming an insulating film inside the first trench along the side of the first trench;
Forming a first electrode inside the insulating film;
Forming an interlayer insulating film inside the first electrode;
Exposing the semiconductor through the interlayer insulating film at the bottom of the first trench;
Forming a first second conductivity type semiconductor region at the bottom of the first trench in the second conductivity type impurity layer;
Forming a buried electrode connected to the first second-conductivity-type semiconductor region at the bottom of the first trench inside the interlayer insulating film;
Forming a second second conductivity type semiconductor region in a surface layer of the first conductivity type impurity layer adjacent to the trench;
Forming a second electrode connected to the embedded electrode and a third electrode connected to the second second conductivity type semiconductor region;
In order.   The method of manufacturing a semiconductor device according to claim 12, wherein a conductivity type of the semiconductor substrate is a first conductivity type.   The method of manufacturing a semiconductor device according to claim 12, wherein a conductivity type of the semiconductor substrate is a second conductivity type. Forming a first conductivity type impurity layer having a uniform impurity concentration on a semiconductor substrate;
Forming a second conductivity type impurity layer having a uniform impurity concentration on the first conductivity type impurity layer;
Forming a trench penetrating the second conductivity type impurity layer;
Forming an insulating film inside the trench along a side of the trench;
Forming a first electrode inside the insulating film;
Forming a second second conductivity type semiconductor region at the bottom of the trench;
Forming an interlayer insulating film inside the first electrode;
Exposing the second second-conductivity-type semiconductor region through the interlayer insulating film at the bottom of the trench;
Forming a buried electrode connected to the second second-conductivity-type semiconductor region at the bottom of the trench inside the interlayer insulating film;
Forming a first second conductivity type semiconductor region outside the first trench;
Forming a second electrode connected to the first second conductivity type semiconductor region and a third electrode connected to the buried electrode;
In order. Forming a first first conductivity type impurity layer having a uniform impurity concentration on a semiconductor substrate;
Forming a third trench in the first first conductivity type impurity layer;
Forming a second first conductivity type impurity layer having a uniform impurity concentration in the third trench;
Forming a second conductivity type impurity layer having a uniform impurity concentration on the first first conductivity type impurity layer and the second first conductivity type impurity layer;
Forming a first trench penetrating the second conductivity type impurity layer with a narrower width than the third trench;
Forming an insulating film inside the first trench along the side of the first trench;
Forming a first electrode inside the insulating film;
Forming a second second conductivity type semiconductor region at the bottom of the first trench;
Forming an interlayer insulating film inside the first electrode;
Exposing the second second-conductivity-type semiconductor region through the interlayer insulating film at the bottom of the first trench;
Forming a buried electrode connected to the second second conductivity type semiconductor region at the bottom of the first trench inside the interlayer insulating film;
Forming a first second conductivity type semiconductor region outside the first trench;
Forming a second electrode connected to the first second conductivity type semiconductor region and a third electrode connected to the buried electrode;
In order. Forming a first conductivity type impurity layer having a uniform impurity concentration on a semiconductor substrate;
Forming a first trench in the first conductivity type impurity layer;
A step of diffusing impurities at the bottom of the first trench to form a third second conductivity type semiconductor region;
Forming an insulating film inside the first trench along the side of the first trench;
Forming a mask insulating film on a sidewall of the first trench;
Forming a second trench shallower than the third second-conductivity-type semiconductor region at the bottom of the first trench;
Forming a second interlayer insulating film thicker than the insulating film at the bottom of the second trench;
Removing the mask insulating film;
Forming a first electrode inside the insulating film;
Forming a first interlayer insulating film inside the first electrode;
Exposing the semiconductor to the bottom of the second trench through the first interlayer insulating film and the second interlayer insulating film;
Forming a first second conductivity type semiconductor region at the bottom of the second trench in the third second conductivity type semiconductor region;
Forming a buried electrode connected to the first second-conductivity-type semiconductor region at the bottom of the second trench inside the first interlayer insulating film and the second interlayer insulating film;
Forming a second second conductivity type semiconductor region in a surface layer of the first conductivity type impurity layer adjacent to the trench;
Forming a second electrode connected to the embedded electrode and a third electrode connected to the second second conductivity type semiconductor region;
In order. Forming a first first conductivity type impurity layer having a uniform impurity concentration on a semiconductor substrate;
Forming a third trench in the first first conductivity type impurity layer;
Forming a second conductivity type impurity layer having a uniform impurity concentration inside the third trench;
Forming a second first conductivity type impurity layer having a uniform impurity concentration on the first first conductivity type impurity layer and the second conductivity type impurity layer;
Forming a first trench penetrating the second first conductivity type impurity layer with a width narrower than that of the third trench;
Forming an insulating film inside the first trench along the side of the first trench;
Forming a mask insulating film on a sidewall of the first trench;
Forming a second trench having a narrower width than the first trench at the bottom of the first trench;
Forming a second interlayer insulating film thicker than the insulating film at the bottom of the second trench;
Removing the mask insulating film;
Forming a first electrode inside the insulating film;
Forming a first interlayer insulating film inside the first electrode;
Exposing the semiconductor to the bottom of the second trench through the first interlayer insulating film and the second interlayer insulating film;
Forming a first second conductivity type semiconductor region at the bottom of the second trench in the second conductivity type impurity layer;
Forming a buried electrode connected to the first second-conductivity-type semiconductor region at the bottom of the second trench inside the first interlayer insulating film and the second interlayer insulating film;
Forming a second second conductivity type semiconductor region in a surface layer of the first conductivity type impurity layer adjacent to the trench;
Forming a second electrode connected to the embedded electrode and a third electrode connected to the second second conductivity type semiconductor region;
In order. Forming a first conductivity type impurity layer having a uniform impurity concentration on a semiconductor substrate;
Forming a second conductivity type impurity layer having a uniform impurity concentration on the first conductivity type impurity layer;
Forming a second trench shallower than the second conductivity type impurity layer in the second conductivity type impurity layer;
Forming a second interlayer insulating film on a sidewall of the second trench;
Forming a first trench penetrating the second conductivity type impurity layer with a width narrower than that of the second trench at the bottom of the second trench using the second interlayer insulating film as a mask;
Forming an insulating film inside the first trench along the side of the first trench;
Forming a first electrode inside the second interlayer insulating film and the insulating film;
Forming a first interlayer insulating film inside the first electrode;
Exposing the semiconductor to the bottom of the first trench through the first interlayer insulating film;
Forming a second second conductivity type semiconductor region at the bottom of the first trench;
Forming a buried electrode connected to the second second-conductivity-type semiconductor region at the bottom of the first trench inside the first interlayer insulating film;
Forming a first second conductivity type semiconductor region outside the first trench;
Forming a second electrode connected to the first second conductivity type semiconductor region and a third electrode connected to the buried electrode;
In order.   21. The method of manufacturing a semiconductor device according to claim 16, wherein a conductivity type of the semiconductor substrate is a first conductivity type.   21. The method of manufacturing a semiconductor device according to claim 16, wherein a conductivity type of the semiconductor substrate is a second conductivity type.

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