JP2004253470A

JP2004253470A - Semiconductor device and its fabricating process

Info

Publication number: JP2004253470A
Application number: JP2003040067A
Authority: JP
Inventors: Masanobu Iwatani; 将伸岩谷; Mutsumi Kitamura; 睦美北村
Original assignee: Fuji Electric Device Technology Co Ltd
Current assignee: Fuji Electric Co Ltd
Priority date: 2003-02-18
Filing date: 2003-02-18
Publication date: 2004-09-09
Anticipated expiration: 2023-02-18
Also published as: JP4374866B2

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which a high gate breakdown voltage of a trench power MOSFET and an appropriate gate threshold voltage of a low breakdown voltage planar MOSFET constituting a CMOS circuit integrated on the same semiconductor substrate can be realized simultaneously, and to provide its fabricating process. <P>SOLUTION: Thick oxide films 23 and 24 of a trench MOSFET are formed by depositing a thin second oxide film on a thick first oxide film (not shown), and thin gate oxide films 25 and 26 of a planar MOSFET at a CMOS section are formed only of the second oxide film. Since the thick first oxide film covering the CMOS section is removed by wet etching and the thick first oxide film remaining on the trench MOSFET is removed by anisotropic etching in the fabrication process, the gate oxide film in the trench does not sink and a high gate breakdown voltage can be ensured. Furthermore, a low gate threshold voltage can be ensured because the gate oxide film of the planar MOSFET is thin at the CMOS section. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
この発明は、スイッチング電源用ＩＣ、自動車パワー系駆動用ＩＣ、フラットパネルディスプレー駆動用ＩＣなど、高耐圧・大電流を制御する集積回路に適する低オン抵抗のパワーＭＯＳＦＥＴとそれを制御するＣＭＯＳ回路を構成するＭＯＳＦＥＴとを集積した半導体装置およびその製造方法に関し、特に、パワーＭＯＳＦＥＴは半導体基板表面を掘り下げたトレンチ内にゲート電極を設けたトレンチ型ラテラルパワーＭＯＳＦＥＴ（ＴＬＰＭ）であり、トレンチ構造のパワーＭＯＳＦＥＴとＣＭＯＳ回路を構成するプレーナ構造のＭＯＳＦＥＴのゲート絶縁膜の膜厚とゲート絶縁膜の形成方法に関する。
【０００２】
【従来の技術】
携帯機器の急速な普及、通信技術の高度化などに伴い、パワーＭＯＳＦＥＴを内蔵したパワーＩＣの重要性は高まっている。従来のパワーＭＯＳＦＥＴ単体と制御駆動回路とを組み合わせに対し、横型パワーＭＯＳＦＥＴを制御回路に集積することにより、小型化、低消費電力化、高信頼性化、低コスト化などが期待されているため、ＣＭＯＳプロセスをベースにした高性能横型ＭＯＳＦＥＴの開発が精力的に進められている。従来のプレーナ構造の横型パワーＭＯＳＦＥＴを改良したトレンチ型の横型パワーＭＯＳＦＥＴとＣＭＯＳ回路のプレーナＭＯＳＦＥＴを集積した半導体装置およびその製造方法が出願人により特願２００１−３８４９０４にて提案されている。その半導体装置およびその製造方法について以下に説明する。
【０００３】
図２０は、この半導体装置の、ＭＯＳＦＥＴとして電流を駆動する活性領域における要部断面図である。図２０に示すように、この半導体装置は同一のｐ型基板１５０上に、トレンチ横型パワーＭＯＳＦＥＴ１０１とＰＭＯＳ１０２とＮＭＯＳ１０３がそれぞれ１個づつ製作された構成となっている。トレンチ横型パワーＭＯＳＦＥＴ１０１、ＰＭＯＳ１０２およびＮＭＯＳ１０３は素子分離用の選択酸化膜１９３により互いに分離される。
まず、トレンチ横型パワーＭＯＳＦＥＴ１０１の構成について説明する。ｐ型基板１５０にはｐ型ウェル領域１１０が形成されており、トレンチ横型パワーＭＯＳＦＥＴはこのｐ型ウェル領域１１０内に形成されている。ゲート絶縁膜となるゲート酸化膜１５９はトレンチ１５１の側面に沿って均一な厚さで形成されている。このゲート酸化膜１５９はトレンチ１５１の底面のゲート酸化膜１８３と繋がっている。トレンチ底面のゲート酸化膜１８３はトレンチ側面のゲート酸化膜１５９より厚く形成されている。第１の導電体であるゲートポリシリコン１５２はトレンチ側面のゲート酸化膜１５９の内側に沿ってトレンチ１５１のほぼ上下にわたって形成されている。
【０００４】
トレンチ１５１の下半部の外側領域は、ｎ型のドリフト領域となるｎ拡散領域１６０である。このｎ拡散領域１６０の外側は前記ｐ型ウェル領域１１０である。なお、トレンチ横型パワーＭＯＳＦＥＴがｐ型ウェル領域１１０内ではなく、ＰＭＯＳ１０２の後述するｎウェル領域１２０の外側のｐ型の部分に形成された構成となってもよい。ｎ拡散領域１６０内に於いて、トレンチ１５１の底の中央部にはドレイン領域となるｎ^＋拡散領域１５８が設けられている。ｎ^＋拡散領域１５８（ドレイン領域）は、ゲートポリシリコン１５２の内側に層間絶縁膜である層間酸化膜１６５を介して設けられた第２の導電体であるドレインポリシリコン１６３に接続されている。ドレインポリシリコン１６３はドレイン電極１５５に接続されている。層間酸化膜１６５は基板表面を覆っており、さらにその上には層間酸化膜１６６が積層されている。
【０００５】
トレンチ１５１の上半部の外側領域はｐベース領域１６２であり、そのｐベース領域１６２上の基板表面領域にソース領域となるｎ^＋拡散領域１６１が形成されている。ｎ^＋拡散領域１６１（ソース領域）は、基板表面に形成されたソース電極１５４に電気的に接続されている。ｐベース領域１６２は、平面的に接続されている。
つぎに、ＰＭＯＳ１０２の構成について説明する。ＰＭＯＳ１０２は、ｐ型基板１５０に設けられたｎ型ウェル領域１２０内に形成されている。ゲート絶縁膜となるゲート酸化膜１２９は、ソース領域またはドレイン領域（以下、ソース／ドレイン領域とする）となるｐ^＋拡散領域１２１、１２１およびその間のチャネル領域の上に、２つのｐ^＋拡散領域１２１、１２１とオーバーラップした状態で形成されている。ゲート酸化膜１２９の上には第１の導電体であるゲートポリシリコン１２５が形成されている。ゲートポリシリコン１２５はゲート電極１２３に電気的に接続されている。
【０００６】
各ｐ^＋拡散領域１２１の上にはソース電極またはドレイン電極となるソース／ドレイン電極１２４が形成されており、それぞれｐ^＋拡散領域１２１と電気的に接続されている。ゲート電極１２３と各ソース／ドレイン電極１２４は前記層間酸化膜１６５、１６６によって電気的に絶縁されている。図２０に示す例では、ｎ型ウェル領域１２０は選択酸化膜１９３の下側でｐ型ウェル領域１１０に接している。ただし、ｐ型ウェル領域１１０がない場合には、ｎ型ウェル領域１２０は選択酸化膜１９３の下側で終端となっている。
つぎに、ＮＭＯＳ１０３の構成について説明する。ＮＭＯＳ１０３は、ｐ型ウェル領域１１０内に形成されている。ゲート絶縁膜となるゲート酸化膜１１９は、ソース／ドレイン領域となるｎ^＋拡散領域１１１、１１１およびその間のチャネル領域の上に、各ｎ^＋拡散領域１１１、１１１とオーバーラップした状態で形成されている。なお、ＮＭＯＳ１０３がｐ型ウェル領域１１０内ではなく、ＰＭＯＳ１０２のｎ型ウェル領域１２０の外側のｐ型の部分に形成された構成となっていてもよい。
【０００７】
ゲート酸化膜１１９の上には第１の導電体であるゲートポリシリコン１１５が形成されている。ゲートポリシリコン１１５はゲート電極１１３に電気的に接続されている。ソース電極またはドレイン電極となるソース／ドレイン電極１１４はｎ^＋拡散領域１１１に電気的に接続されている。ゲート電極１１３と各ソース／ドレイン電極１１４は前記層間酸化膜１６５、１６６によって電気的に絶縁されている。
前記のトレンチ横型パワーＭＯＳＦＥＴ１０１のゲート酸化膜１８３とＰＭＯＳ１０２、ＮＭＯＳ１０３のゲート酸化膜１２９、１１９は同時に形成された酸化膜であるために、それぞれの膜厚は同じである。
【０００８】
また、前記のゲート酸化膜１１９、１２９、１８３をゲート電極下に残し、その他の箇所のゲート酸化膜を除去する方法として、ＲＩＥ（反応性イオンエッチ）法などの異方性エッチングを用いる。
【０００９】
【発明が解決しようとする課題】
前記のように、トレンチ横型パワーＭＯＳＦＥＴ１０１のゲート酸化膜１８３とＰＭＯＳ１０２、ＮＭＯＳ１０３のゲート酸化膜１２９、１１９の膜厚は同じであり、ＣＭＯＳ回路を構成するＰＭＯＳ１０２、ＮＭＯＳ１０３のゲートしきい値電圧を低くするためにゲート酸化膜の膜厚は薄くする。そうすると、トレンチ横型パワーＭＯＳＦＥＴ１０１のゲート酸化膜の膜厚も薄くなり、このトレンチ横型パワーＭＯＳＦＥＴ１０１を、例えば、ハイサイドスイッチとして用いた場合には、ゲート電極とソース電極間に高いゲート電圧が印加され、ゲート酸化膜の絶縁耐量を超えてしまい、ゲート酸化膜が絶縁破壊を起こして、トレンチ横型パワーＭＯＳＦＥＴ１０１が破壊する場合がある。そのため、トレンチ横型パワーＭＯＳＦＥＴ１０１を高ゲート耐圧化することが困難である。一方、トレンチ横型パワーＭＯＳＦＥＴの厚いゲート絶縁膜に合わせてプレーナ横型ＭＯＳＦＥＴのゲート絶縁膜を形成すると、プレーナ横型ＭＯＳＦＥＴのゲートしきい値電圧が高く成りすぎるという不具合を生じる。
【００１０】
この発明の目的は、前記の課題を解決して、同一半導体基板に集積したトレンチパワーＭＯＳＦＥＴの高ゲート耐圧化とＣＭＯＳ回路を構成する低耐圧プレーナＭＯＳＦＥＴのゲートしきい値電圧の適正化を同時に図ることができる半導体装置およびその製造方法を提供することにある。
【００１１】
【課題を解決するための手段】
前記の目的を達成するために、トレンチＭＯＳ素子とプレーナＭＯＳＦＥＴとが同一基板上に集積された半導体装置であって、トレンチＭＯＳ素子のゲート絶縁膜の膜厚がプレーナＭＯＳＦＥＴのゲート絶縁膜の膜厚より厚い構成とする。
また、トレンチＭＯＳ素子とプレーナＭＯＳＦＥＴとが同一基板上に集積された半導体装置であって、半導体基板の前記トレンチＭＯＳ素子形成領域に形成されるトレンチと、前記トレンチＭＯＳ素子と前記プレーナＭＯＳＦＥＴを分離する分離領域と、該トレンチの底面に形成される第１導電形の第１拡散領域と、前記半導体基板の表面層に前記トレンチと接して形成される第１導電形の第２拡散領域と、前記プレーナＭＯＳＦＥＴ形成領域に第１のゲート絶縁膜を介して形成される第１のゲート電極と、前記第１拡散領域と前記第２拡散領域とに挟まれた前記トレンチ側壁に前記第１のゲート絶縁膜より厚い第２のゲート絶縁膜を介して形成される第２のゲート電極と、前記第２のゲート電極をマスクとして形成される前記第２のゲート電極を挟んで対向する第１導電形の第３拡散領域および第１導電形の第４拡散領域とを具備する構成とする。
【００１２】
また、トレンチＭＯＳ素子とプレーナＭＯＳＦＥＴとが同一基板上に集積された半導体装置であって、半導体基板の前記トレンチＭＯＳ素子形成領域に形成されるトレンチと、前記トレンチＭＯＳ素子と前記プレーナＭＯＳＦＥＴを分離する分離領域と、該トレンチの底面に形成される第１導電形の第１拡散領域と、前記半導体基板の表面層に前記トレンチと接して形成される第１導電形の第２拡散領域と、前記プレーナＭＯＳＦＥＴ形成領域に第１のゲート絶縁膜を介して形成される第１のゲート電極と、前記第１拡散領域と前記第２拡散領域とに挟まれた前記トレンチ内壁に前記第１のゲート絶縁膜より厚い第２のゲート絶縁膜を介して形成される第２のゲート電極と、前記第２のゲート電極をマスクとして形成される前記第２のゲート電極を挟んで対向する第２導電形の第３拡散領域および第２導電形の第４拡散領域とを具備する構成とする。
【００１３】
また、トレンチＭＯＳ素子とプレーナＭＯＳＦＥＴとが同一基板上に集積された半導体装置の製造方法において、半導体基板に前記トレンチＭＯＳ素子形成領域にトレンチを形成する工程と、前記トレンチの底面に第１導電形の第１拡散領域を形成する工程と、前記トレンチＭＯＳ素子とプレーナＭＯＳＦＥＴを分離する分離領域を前記半導体基板に形成する工程と、前記トレンチＭＯＳ素子形成領域上と前記プレーナＭＯＳＦＥＴ形成領域上に第１の絶縁膜を形成する工程と、前記トレンチ上の前記第１の絶縁膜をマスクしてウエットエッチングにより前記第１の絶縁膜をエッチングする工程と、前記トレンチＭＯＳ素子形成領域上と前記プレーナＭＯＳＦＥＴ形成領域上に第２の絶縁膜を形成する工程と、該第２の絶縁膜上に第１の導電体を形成し、前記プレーナＭＯＳＦＥＴのゲート電極となる前記第１の導電体をマスクして異方性エッチングにより前記第１の導電体をエッチングし前記トレンチ側壁に第１のゲート電極と前記プレーナＭＯＳＦＥＴの第２のゲート電極を形成する工程と、前記半導体基板の表面層に前記トレンチ側壁と接して第１導電形の第２の拡散層を形成する工程と、前記第２のゲート電極をマスクとして前記第２のゲート電極を挟んで対向する第１導電形の第３拡散領域および第１導電形の第４拡散領域を形成する工程とを含む製造方法とする。
【００１４】
また、トレンチＭＯＳ素子とプレーナＭＯＳＦＥＴとが同一基板上に集積された半導体装置の製造方法において、半導体基板に前記トレンチＭＯＳ素子形成領域にトレンチを形成する工程と、前記トレンチの底面に第１導電形の第１拡散領域を形成する工程と、前記トレンチＭＯＳ素子とプレーナＭＯＳＦＥＴを分離する分離領域を前記半導体基板に形成する工程と、前記トレンチＭＯＳ素子形成領域上と前記プレーナＭＯＳＦＥＴ形成領域上に第１の絶縁膜を形成する工程と、前記トレンチ上の前記第１の絶縁膜をマスクしてウエットエッチングにより前記第１の絶縁膜をエッチングする工程と、前記トレンチＭＯＳ素子形成領域上と前記プレーナＭＯＳＦＥＴ形成領域上に第２の絶縁膜を形成する工程と、該第２の絶縁膜上に第１の導電体を形成し、前記プレーナＭＯＳＦＥＴのゲート電極となる前記第１の導電体をマスクして異方性エッチングにより前記第１の導電体をエッチングし前記トレンチ側壁に第１のゲート電極と前記プレーナＭＯＳＦＥＴの第２のゲート電極を形成する工程と、前記半導体基板の表面層に前記トレンチ側壁と接して第１導電形の第２の拡散層を形成する工程と、前記第２のゲート電極をマスクとして前記第２のゲート電極を挟んで対向する第２導電形の第３拡散領域および第２導電形の第４拡散領域を形成する工程とを含む製造方法とする。
【００１５】
また、前記第１の絶縁膜をエッチングする工程は、前記トレンチＭＯＳ素子形成領域上の前記第１の絶縁膜をマスクしてウエットエッチングにより前記第１の絶縁膜をエッチングするとよい。
また、前記分離領域は、選択酸化もしくは分離溝に絶縁膜を充填した絶縁分離領域で形成するとよい。
また、前記トレンチＭＯＳ素子の第２の拡散領域は、前記第２のゲート電極と前記第１、第２の絶縁膜とをマスクとして形成されるとよい。
また、前記第２のゲート電極の側壁にスペーサを形成し、該スペーサと前記第２のゲート電極をマスクとして、ＬＤＤ構造を形成するとよい。
【００１６】
【発明の実施の形態】
〔実施例１〕
図１は、この発明の第１実施例の半導体装置の要部断面図である。この図は、ＣＭＯＳを構成するプレーナ横型ＭＯＳＦＥＴとトレンチ横型パワーＭＯＳＦＥＴを集積したデバイスの断面模式図を示す。以下の説明ではトレンチ横型パワーＭＯＳＦＥＴとを単にトレンチＭＯＳＦＥＴと呼び、プレーナ横型ＭＯＳＦＥＴを単にプレーナＭＯＳＦＥＴと呼ぶこととする。尚、ＣＭＯＳ部はｎチャネルのプレーナＭＯＳＦＥＴとｐチャネルのプレーナＭＯＳＦＥＴで構成される。
【００１７】
ｐ半導体基板１に、ＣＭＯＳを構成するプレーナＭＯＳＦＥＴとトレンチＭＯＳＦＥＴを形成するｐウェル領域２、４とｎウェル領域３、５をそれぞれ形成し、プレーナＭＯＳＦＥＴを形成するｐウェル領域４上とｎウェル領域４上に１７μｍ程度の薄いゲート酸化膜２５、２６を介してポリシリコンなどでゲート電極２０、２１を形成し、このゲート電極２０、２１の側壁にスペーサ２２を形成してＬＤＤ構造のｎソース領域またはｎドレイン領域になるｎソース／ドレイン領域２９とｐソース領域またはｐドレイン領域になるｐソース／ドレイン領域３０をそれぞれ形成する。
【００１８】
トレンチＭＯＳＦＥＴを形成するｐウェル領域２とｎウェル領域３に、トレンチ７、８をそれぞれ形成し、トレンチ７、８内にｎドレイン領域１０（またはｎソース領域）とｐドレイン領域１１（またはｐソース領域）をそれぞれ形成し、トレンチ７の側壁に６２μｍ程度の厚いゲート酸化膜２３、２４を介してポリシリコンなどでゲート電極１８、１９を形成し、トレンチ７、８の外側表面にトレンチ７と接するｎソース領域２７（またはｎドレイン領域）、ｐソース領域２８（ｐドレイン領域）を形成し、ゲート電極１８、１９の内側を層間絶縁膜３１の酸化膜で充填し、この酸化膜を開口してｎドレイン領域１０（またはｎソース領域）、ｐドレイン領域１１（ｐソース領域）にポリシリコンなどでプラグ導体３２、３３を充填し、プラグ導体３２、３３上にドレイン電極３４、３５、ソース領域２７、２８上にソース電極３６、３７をアルミニウムなどで形成し、プレーナＭＯＳＦＥＴのｎソース／ドレイン領域２９上およびｐソース／ドレイン領域３０上にそれぞれソース／ドレイン電極３８、３９をアルミニウムなどで形成する。
【００１９】
プレーナＭＯＳＦＥＴの薄いゲート酸化膜２５、２６を１７ｎｍ程度とすることで０．８Ｖ±０．１Ｖ程度の低ゲートしきい値電圧とすることができ、トレンチＭＯＳＦＥＴの厚いゲート酸化膜２３、２４を６２ｎｍ程度とすることで所定のゲートしきい値電圧と６０Ｖ以上の高いゲート耐圧を得ることができる。
〔実施例２〕
図２から図１０は、この発明の第２実施例の半導体装置の製造方法であり、工程順に示した要部製造工程断面図である。この製造方法は図１の半導体装置で、ＣＭＯＳ部（プレーナＭＯＳＦＥＴでｎチャネルＭＯＳＦＥＴとｐチャネルＭＯＳＦＥＴを含む）とトレンチＭＯＳＦＥＴの製造方法である。
【００２０】
まず、ｐ半導体基板１の表面層に選択的にｐウェル領域２、４、ｎウェル領域３、５を形成する。ｐ半導体基板１の不純物濃度を適正に選定した場合はｐウェル領域２、４は必ずしも形成する必要はない（図２）。
つぎに、トレンチＭＯＳＦＥＴを形成する部分に、例えば４００ｎｍの酸化膜６（熱酸化膜、または、堆積酸化膜）をマスクにトレンチ７、８を形成し、この酸化膜６をマスクとしてトレンチ７、８を形成する（図３）。
つぎに、トレンチの底部７ａ、８ａ底面に、選択的にｎおよびｐドレイン領域（ｎまたはｐソース領域）を形成し、素子分離するためのＬＯＣＯＳ９（選択酸化膜）を形成する。この際、必要に応じて、図示しないフィールドイオン注入や、ＣＭＯＳ部にパンチスルー防止用イオン注入を行う場合もある（図４）。
【００２１】
つぎに、犠牲酸化膜１２を形成し、１３イオン注入などによりチャネル領域１４を形成する。このチャネル領域１４の形成はゲートしきい値を調整するためであり、ｎウェル領域４やｐウェル領域５の表面濃度が適正である場合は犠牲酸化膜１２の形成とチャネルイオン注入１３は必ずしも必要としない。イオン注入する場合はイオン注入１３の打ち込み角度を例えば４５°にしてトレンチ７、８側壁にも打ち込むことによりトレンチＭＯＳＦＥＴのしきい値調整を行うことができる（図５）。
つぎに、犠牲酸化膜１２を除去した後、第１の酸化膜１５を例えば５０ｎｍ形成し、フォトリソグラフィー工程で、トレンチＭＯＳＦＥＴのトレンチ７、８部を例えばレジスト１６でマスクして、ＣＭＯＳ形成領域上とトレンチ７、８の外側領域上の第１の酸化膜１５を弗酸緩衝溶液によりウェットエッチングして除去する。このウェットエッチングでは、異方性エッチングと異なり、ＣＭＯＳ形成領域の表面およびトレンチＭＯＳＦＥＴのソース形成領域表面を荒らしたりダメージを与えたりすることはない（図６）。
【００２２】
つぎに、第２の酸化膜１７を例えば１７ｎｍ形成する。つまり、ＣＭＯＳ形成領域上には第２の酸化膜１７のみの薄い酸化膜、トレンチＭＯＳＦＥＴ形成領域には第１と第２の酸化膜１５、１７を積層した６２ｎｍの厚い酸化膜が形成される。厚い酸化膜の膜厚が６７ｎｍでなく６２ｎｍになるのは、厚の酸化膜上に形成される酸化膜の成長速度はシリコン上に形成する酸化膜より遅いためである（図７）。
つぎに、ゲート電極１８、１９、２０、２１となるポリシリコンを全面に形成する。ＣＭＯＳのゲート電極形成領域のポリシリコンをレジストなどでマスクして、ポリシリコンを異方性エッチングによりエッチバックして、トレンチＭＯＳＦＥＴ部のゲート電極１８、１９とＣＭＯＳ部のゲート電極２０、２１を同時に形成する。このとき、ＣＭＯＳ部のゲート電極２０、２１とトレンチＭＯＳＦＥＴ部のゲート電極１８、１９を、それぞれ専用のフォトマスクを用いて、別々に形成してもよい（図８）。
【００２３】
つぎに、ＣＭＯＳ部にゲート電極２２、２１をマスクとして、不純物濃度が低い領域を形成し、その後、例えばＣＶＤ法で１５０ｎｍの酸化膜を堆積させ、通常のＣＭＯＳプロセスにしたがって、ＲＩＥ（ＲｅａｃｔｉｖｅＩｏｎＥｔｃｈｉｎｇ）によりこの酸化膜をエッチングしてＣＭＯＳ部のゲート電極側面にスペーサ２２を形成する。このスペーサを形成するときに、第２の酸化膜を除去する。このスペーサ２２とゲート電極２０、２１をマスクに不純物濃度の高い領域を拡散して、ＣＭＯＳ部にＬＤＤ（ＬｉｇｈｔＤｏｐｅｄＤｒａｉｎ）構造のｎまたはｐソース／ドレイン領域２９、３０を形成し、同時にトレンチＭＯＳＦＥＴ部のｎまたはｐソース領域２７、２８（ｎまたはｐドレイン領域）を形成する（図９）。
【００２４】
つぎに、層間絶縁膜３１となる酸化膜を、ＣＶＤ（ＣｈｅｍｉｃａｌＶａｐｏｒＤｅｐｏｓｉｔｉｏｎ）法などで形成し、その後、層間絶縁膜３１をエッチバックしてトレンチ８、９の底面８ａ、９ａを露出する。つぎに、ｎドレイン領域１０、ｐドレイン領域１１と接続するトレンチＭＯＳＦＥＴのプラグ導体３２、３３となるポリシリコンをＣＶＤ法などで形成し、エッチバックする。ここで、ポリシリコンの下に図示しないバリアメタル（ＴｉＮ／Ｔｉ）を堆積させてもよい。つぎに、トレンチＭＯＳＦＥＴのｎソース領域２７上、ｐソース領域２８上にソース電極３６、３７、ｎドレイン領域１０上、ｐドレイン領域１１上にドレイン電極３４、３５とプレーナＭＯＳＦＥＴのｎソース／ドレイン領域２７上、ｐソース／ドレイン領域２８上にソース／ドレイン電極３８、３９をアルミニウムなどでそれぞれ形成する（図１０）。
【００２５】
このように、異なる膜厚のゲート酸化膜を持つツインゲート構造とすることで、ＣＭＯＳ部を構成するプレーナＭＯＳＦＥＴのゲートしきい値電圧の低電圧化とトレンチＭＯＳＦＥＴのゲート耐圧の高耐圧化を図ることができる。
また、ＣＭＯＳ形成領域とトレンチの外側の領域から第１の酸化膜１５を弗酸緩衝溶液による等方性エッチングであるウェットエッチングすることで、異方性エッチングと異なり、ＣＭＯＳ形成領域の表面を荒らしたり、表面にダメージを与えたりすることがなく、良好な電気的特性が得られる。
しかし、前記のように、第１の酸化膜１５をウェットエッチングで除去した場合、エッチング量が多いと、図１１（ａ）に示すようにトレンチ内部まで第１の酸化膜１５が落ち込んでしまい、この落ち込んだ箇所は第２の酸化膜１７のみとなり、図１１（ｂ）に示すゲート酸化膜２３が薄くなるＤ部でゲート耐圧が低下する。また、エッチングが不足すると、図１２（ａ）に示すようにトレンチ肩部に第１の酸化膜１５が残り、図１２（ｂ）に示すように、この厚い第１の酸化膜１５が残った箇所にはイオン注入によるｎソース領域２７が形成されず、ソース領域２７はトレンチ側壁から離れて形成される。そうすると、トレンチ側壁に形成されたチャネルがｎソース領域２７と接続させるためには高いゲート電圧を印加する必要があり、ゲートしきい値電圧が高くなる。尚、図１１（ａ）、図１２（ａ）のＬは第１の酸化膜１５の落ち込み量を示し、図１１（ａ）に示す＋符号はトレンチ上部から第１の酸化膜１５が下方に落ち込んだ量を示し、図１２（ａ）に示す−符号はトレンチの外側領域上に第１の酸化膜１５が残る量を示す。
【００２６】
つぎに、このように第１の酸化膜１５の落ち込みを防止できる製造方法を説明する。
〔実施例３〕
図１３から図１６は、この発明の第３実施例の半導体装置の製造方法であり、工程順に示した要部製造工程断面図である。図１３から図１６の工程は図６から図９にそれぞれ相当する工程である。
前記の第２実施例と異なるのは、図６に相当する図１３のフォトリソグラフィー工程で、トレンチＭＯＳＦＥＴのトレンチ７、８およびトレンチ７、８の外側領域（ソース形成領域）上を広くレジスト１６ａでマスクしてＣＭＯＳ部から第１の酸化膜１５を弗酸緩衝溶液で除去し、トレンチ７、８の外側領域上に第１の酸化膜１５を残した点である。このように、第１の酸化膜１５をトレンチ７、８の外側領域上に残すことで、図１１のようにこの第１の酸化膜１５がトレンチ７、６の上部から落ち込むことを防止できる。つぎの工程からは第１実施例と同じである。
【００２７】
図１４の工程で第２の酸化膜１７を形成し、図１５の工程でゲート電極１８、１９、２０、２１を形成する。図１６の工程で、図示しない酸化膜を全面に被覆し、異方性エッチングでトレンチ７、８の外側領域が露出するまで、図示しない酸化膜と第１の酸化膜１５および第２の酸化膜１７を除去する。この異方性エッチングでゲート電極１８、１９、２０、２１の側面には酸化膜が残り、ゲート電極１８、１９の側面に残った酸化膜がスペーサ２２となる。図ではゲート電極２０、２１の側面に残った酸化膜は描かれていない。
このようにすることで、図１６のＣ部の拡大図で、図１１（ｂ）や図１２（ｂ）に相当する図１７に示すように、トレンチＭＯＳＦＥＴのトレンチ側壁に形成された第１の酸化膜１５のＥ部での落ち込みを防止できる。具体的には落ち込み量を±１０ｎｍ以内（±の意味は＋は落ち込み量、−は残渣量）に抑えることができる。
【００２８】
このように、異なるゲート酸化膜厚を持つツインゲート構造とし、ＣＭＯＳを構成するプレーナＭＯＳＦＥＴの薄いゲート酸化膜２５、２６の膜厚を１７ｎｍ程度にすることで、ＣＭＯＳを構成するプレーナＭＯＳＦＥＴのゲートしきい値電圧を０．８Ｖ±０．１Ｖ程度の低いゲートしきい値電圧することができる。また、トレンチＭＯＳＦＥＴの厚いゲート酸化膜２３、２４の膜厚を６２μｍ程度とし、この第１の酸化膜１５の落ち込み量を±１０ｎｍ程度に抑制することで、トレンチＭＯＳＦＥＴのゲート耐圧を６０Ｖ程度の高いゲート耐圧（後述の図１８）にし、ゲートしきい値電圧を所定の値（後述の図１９）にすることができる。
【００２９】
図１８、図１９は、第１の酸化膜１５の落ち込み量とゲート耐圧とゲートしきい値電圧の関係を示す図である。図の横軸の第１の酸化膜の落ち込み量（図１１、図１２のＬ）で、−符号（Ｌ（−））は第１の酸化膜１５がトレンチの外側領域上に残った状態（残渣がある状態）の量を示し、＋符号（Ｌ（＋）は側壁の第１の酸化膜１５がトレンチ上部から除去される量を示す。
図１８から、第１の酸化膜１５の落ち込み量が＋符号になると、トレンチ上部から第１の酸化膜が落ち込んだ箇所のトレンチ側壁は、薄い第２の酸化膜１７のみの被覆となり、ゲート耐圧が低下する。また、図１９から、第１の酸化膜１５の落ち込み量が−符号になると、ソース領域がトレンチ側壁から離れて形成されるために、チャネルがソース領域と接するゲート電圧が高くなり、ゲートしきい値は大きくなる。これらの結果から、トレンチＭＯＳＦＥＴにおいて、所定のゲートしきい値電圧と６０Ｖ程度の高いゲート耐圧を得るためには、落ち込み量を±１５ｎｍに抑制する必要がある。前記したように、第３実施例の場合はこの落ち込み量を±１０ｎｍ程度にすることができる。
【００３０】
【発明の効果】
この発明において、ＣＭＯＳ部のゲート酸化膜を薄く、トレンチＭＯＳＦＥＴ部のゲート酸化膜を厚くすることで、ＣＭＯＳ部は低しきい値電圧、トレンチＭＯＳＦＥＴ部は高ゲート耐圧を得ることができる。
また、トレンチＭＯＳＦＥＴ形成領域上の酸化膜をマスクして、ＣＭＯＳ部上に形成された酸化膜をウェットエッチで除去し、つぎに、トレンチＭＯＳＦＥＴ形成領域上に形成された厚い酸化膜を、異方性エッチングでエッチバックすることで、落ち込み量が小さい厚いゲート酸化膜をトレンチ内壁に形成できる。その結果、高いゲート耐圧と所定のゲートしきい値電圧を確保できるトレンチＭＯＳＦＥＴを製作できる。
【００３１】
また、ウェットエッチングでＣＭＯＳ部上の厚い酸化膜を除去することで、ＣＭＯＳ部の表面にダメージや荒れが導入されることが防止され、ＣＭＯＳ部で良好な電気的特性を得ることができる。
【図面の簡単な説明】
【図１】この発明の第１実施例の半導体装置の要部断面図
【図２】この発明の第２実施例の半導体装置の要部製造工程断面図
【図３】図２に続く、この発明の第２実施例の半導体装置の要部製造工程断面図
【図４】図３に続く、この発明の第２実施例の半導体装置の要部製造工程断面図
【図５】図４に続く、この発明の第２実施例の半導体装置の要部製造工程断面図
【図６】図５に続く、この発明の第２実施例の半導体装置の要部製造工程断面図
【図７】図６に続く、この発明の第２実施例の半導体装置の要部製造工程断面図
【図８】図７に続く、この発明の第２実施例の半導体装置の要部製造工程断面図
【図９】図８に続く、この発明の第２実施例の半導体装置の要部製造工程断面図
【図１０】図９に続く、この発明の第２実施例の半導体装置の要部製造工程断面図
【図１１】第１の酸化膜がトレンチ上部から落ち込んだ場合の図
【図１２】第１の酸化膜がトレンチの外側領域上に残った場合の図
【図１３】この発明の第３実施例の半導体装置の要部製造工程断面図
【図１４】図１３に続く、この発明の第３実施例の半導体装置の要部製造工程断面図
【図１５】図１４に続く、この発明の第３実施例の半導体装置の要部製造工程断面図
【図１６】図１５に続く、この発明の第３実施例の半導体装置の要部製造工程断面図
【図１７】図１５のＣ部拡大図
【図１８】第１の酸化膜１５の落ち込み量とゲート耐圧の関係を示す図
【図１９】第１の酸化膜１５の落ち込み量とゲートしきい値電圧の関係を示す図
【図２０】従来の半導体装置で、ＣＭＯＳ部とトレンチＭＯＳＦＥＴを同一半導体基板に形成した要部断面図
【符号の説明】
１ｐ半導体基板
２、３ｐウェル領域
４、５ｎウェル領域
６酸化膜
７、８トレンチ
７ａ、８ａ底面
９ＬＯＣＯＳ
１０ｎドレイン領域
１１ｐドレイン領域
１２犠牲酸化膜
１３イオン注入
１４チャネル領域
１５第１の酸化膜
１６、１６ａレジスト
１７第２の酸化膜
１８、１９、２０、２１ゲート電極
２２スペーサ
２３、２４厚いゲート酸化膜
２５、２６薄いゲート酸化膜
２７ｎソース領域
２８ｐソース領域
２９ｎソース／ドレイン領域
３０ｐソース／ドレイン領域
３１層間絶縁膜
３２、３３プラグ導体
３４、３５ドレイン電極
３６、３７ソース電極
３８、３９ソース／ドレイン電極[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a low on-resistance power MOSFET suitable for an integrated circuit for controlling a high withstand voltage and a large current, such as an IC for driving a switching power supply, an IC for driving a vehicle power system, and an IC for driving a flat panel display, and a CMOS circuit for controlling the same. More particularly, the power MOSFET is a trench-type lateral power MOSFET (TLPM) in which a gate electrode is provided in a trench formed by digging a surface of a semiconductor substrate, and a power MOSFET having a trench structure. The present invention relates to a method of forming a gate insulating film and a thickness of a gate insulating film of a MOSFET having a planar structure which forms a CMOS circuit.
[0002]
[Prior art]
With the rapid spread of portable devices and the advancement of communication technology, the importance of power ICs with built-in power MOSFETs is increasing. In contrast to the combination of a conventional power MOSFET and a control drive circuit, integration of a horizontal power MOSFET in the control circuit is expected to reduce size, reduce power consumption, increase reliability, reduce costs, etc. The development of high performance lateral MOSFETs based on the CMOS process has been energetically advanced. A semiconductor device in which a trench-type lateral power MOSFET in which a conventional planar-structure lateral power MOSFET is improved and a planar MOSFET of a CMOS circuit and a method of manufacturing the same have been proposed by the applicant in Japanese Patent Application No. 2001-384904. The semiconductor device and its manufacturing method will be described below.
[0003]
FIG. 20 is a cross-sectional view of main parts of an active region of the semiconductor device that drives a current as a MOSFET. As shown in FIG. 20, this semiconductor device has a configuration in which one trench lateral power MOSFET 101, one PMOS 102, and one NMOS 103 are manufactured on the same p-type substrate 150, respectively. The trench lateral power MOSFET 101, PMOS 102 and NMOS 103 are separated from each other by a selective oxide film 193 for element isolation.
First, the configuration of the trench lateral power MOSFET 101 will be described. A p-type well region 110 is formed in a p-type substrate 150, and a trench lateral power MOSFET is formed in the p-type well region 110. Gate oxide film 159 serving as a gate insulating film is formed with a uniform thickness along the side surface of trench 151. The gate oxide film 159 is connected to the gate oxide film 183 on the bottom of the trench 151. The gate oxide film 183 on the bottom of the trench is formed thicker than the gate oxide film 159 on the side of the trench. The gate polysilicon 152, which is the first conductor, is formed substantially over and under the trench 151 along the inside of the gate oxide film 159 on the side surface of the trench.
[0004]
The outer region in the lower half of the trench 151 is an n-diffusion region 160 serving as an n-type drift region. Outside the n-diffusion region 160 is the p-type well region 110. Note that the configuration may be such that the trench lateral power MOSFET is formed not in the p-type well region 110 but in the p-type portion of the PMOS 102 outside the n-well region 120 described later. In n diffusion region 160, n serving as a drain region is formed at the center of the bottom of trench 151. ⁺ A diffusion region 158 is provided. n ⁺ Diffusion region 158 (drain region) is connected to drain polysilicon 163 as a second conductor provided inside gate polysilicon 152 via an interlayer oxide film 165 as an interlayer insulating film. The drain polysilicon 163 is connected to the drain electrode 155. The interlayer oxide film 165 covers the surface of the substrate, and an interlayer oxide film 166 is further laminated thereon.
[0005]
The outer region in the upper half of the trench 151 is a p base region 162, and an n region serving as a source region is formed on the substrate surface region on the p base region 162. ⁺ A diffusion region 161 is formed. n ⁺ The diffusion region 161 (source region) is electrically connected to a source electrode 154 formed on the surface of the substrate. P base region 162 is planarly connected.
Next, the configuration of the PMOS 102 will be described. The PMOS 102 is formed in an n-type well region 120 provided on a p-type substrate 150. A gate oxide film 129 serving as a gate insulating film has a p-type serving as a source region or a drain region (hereinafter, referred to as a source / drain region). ⁺ On the diffusion regions 121, 121 and the channel region therebetween, two p ⁺ The diffusion regions 121 and 121 are formed so as to overlap with each other. On the gate oxide film 129, a gate polysilicon 125 as a first conductor is formed. Gate polysilicon 125 is electrically connected to gate electrode 123.
[0006]
Each p ⁺ On the diffusion region 121, a source / drain electrode 124 serving as a source electrode or a drain electrode is formed. ⁺ It is electrically connected to the diffusion region 121. The gate electrode 123 and each source / drain electrode 124 are electrically insulated by the interlayer oxide films 165 and 166. In the example shown in FIG. 20, the n-type well region 120 is in contact with the p-type well region 110 below the selective oxide film 193. However, when there is no p-type well region 110, the n-type well region 120 is terminated below the selective oxide film 193.
Next, the configuration of the NMOS 103 will be described. The NMOS 103 is formed in the p-type well region 110. A gate oxide film 119 serving as a gate insulating film has n ⁺ On each of the diffusion regions 111, 111 and the channel region therebetween, each n ⁺ It is formed so as to overlap with the diffusion regions 111, 111. Note that the NMOS 103 may be formed not in the p-type well region 110 but in a p-type portion outside the n-type well region 120 of the PMOS 102.
[0007]
On the gate oxide film 119, a gate polysilicon 115 as a first conductor is formed. Gate polysilicon 115 is electrically connected to gate electrode 113. A source / drain electrode 114 serving as a source electrode or a drain electrode has n ⁺ It is electrically connected to the diffusion region 111. The gate electrode 113 and each source / drain electrode 114 are electrically insulated by the interlayer oxide films 165 and 166.
Since the gate oxide film 183 of the trench lateral power MOSFET 101 and the gate oxide films 129 and 119 of the PMOS 102 and the NMOS 103 are formed simultaneously, they have the same film thickness.
[0008]
Anisotropic etching such as RIE (Reactive Ion Etch) is used as a method of leaving the gate oxide films 119, 129, and 183 below the gate electrode and removing the gate oxide film at other locations.
[0009]
[Problems to be solved by the invention]
As described above, the thicknesses of the gate oxide film 183 of the trench lateral power MOSFET 101 and the gate oxide films 129 and 119 of the PMOS 102 and the NMOS 103 are the same, and the gate threshold voltage of the PMOS 102 and the NMOS 103 constituting the CMOS circuit is reduced. Therefore, the thickness of the gate oxide film is reduced. Then, the thickness of the gate oxide film of the trench lateral power MOSFET 101 is also reduced. When this trench lateral power MOSFET 101 is used, for example, as a high-side switch, a high gate voltage is applied between the gate electrode and the source electrode. In some cases, the dielectric strength of the gate oxide film is exceeded, and the gate oxide film causes dielectric breakdown, and the trench lateral power MOSFET 101 is broken. Therefore, it is difficult to increase the gate breakdown voltage of the trench lateral power MOSFET 101. On the other hand, if the gate insulating film of the planar lateral MOSFET is formed in conformity with the thick gate insulating film of the trench lateral power MOSFET, a problem occurs that the gate threshold voltage of the planar lateral MOSFET becomes too high.
[0010]
SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and simultaneously increase the gate breakdown voltage of a trench power MOSFET integrated on the same semiconductor substrate and optimize the gate threshold voltage of a low breakdown voltage planar MOSFET constituting a CMOS circuit. And a method of manufacturing the same.
[0011]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor device in which a trench MOS element and a planar MOSFET are integrated on the same substrate, wherein the thickness of the gate insulating film of the trench MOS element is equal to the thickness of the gate insulating film of the planar MOSFET A thicker configuration.
A semiconductor device in which a trench MOS element and a planar MOSFET are integrated on the same substrate, wherein a trench formed in the trench MOS element formation region of the semiconductor substrate is separated from the trench MOS element and the planar MOSFET. An isolation region, a first diffusion region of a first conductivity type formed on a bottom surface of the trench, a second diffusion region of a first conductivity type formed on a surface layer of the semiconductor substrate in contact with the trench, A first gate electrode formed in a planar MOSFET formation region via a first gate insulating film; and a first gate insulating film formed on a trench sidewall sandwiched between the first diffusion region and the second diffusion region. A second gate electrode formed through a second gate insulating film thicker than a film, and the second gate formed using the second gate electrode as a mask A structure having a third diffusion region and the fourth diffusion region of the first conductivity type of a first conductivity type opposite to each other with respect to the pole.
[0012]
A semiconductor device in which a trench MOS element and a planar MOSFET are integrated on the same substrate, wherein a trench formed in the trench MOS element formation region of the semiconductor substrate is separated from the trench MOS element and the planar MOSFET. An isolation region, a first diffusion region of a first conductivity type formed on a bottom surface of the trench, a second diffusion region of a first conductivity type formed on a surface layer of the semiconductor substrate in contact with the trench, A first gate electrode formed in a planar MOSFET formation region via a first gate insulating film; and a first gate insulating film formed on an inner wall of the trench interposed between the first diffusion region and the second diffusion region. A second gate electrode formed through a second gate insulating film thicker than a film, and the second gate formed using the second gate electrode as a mask A third diffusion region of the second conductivity type and a fourth diffusion region of the second conductivity type opposed to each other with the electrode interposed therebetween are provided.
[0013]
In a method of manufacturing a semiconductor device in which a trench MOS element and a planar MOSFET are integrated on the same substrate, a step of forming a trench in the trench MOS element formation region in a semiconductor substrate; Forming a first diffusion region, forming an isolation region for separating the trench MOS device and the planar MOSFET in the semiconductor substrate, and forming a first region on the trench MOS device formation region and the planar MOSFET formation region. Forming the insulating film, etching the first insulating film by wet etching using the first insulating film on the trench as a mask, forming the trench MOS element formation region and the planar MOSFET. Forming a second insulating film on the region; and forming a first conductive film on the second insulating film. And etching the first conductor by anisotropic etching using the first conductor serving as a gate electrode of the planar MOSFET as a mask, and forming a first gate electrode and the planar MOSFET on the side walls of the trench. Forming a second gate electrode, forming a second diffusion layer of a first conductivity type in contact with the trench sidewall on a surface layer of the semiconductor substrate, and using the second gate electrode as a mask. Forming a third diffusion region of the first conductivity type and a fourth diffusion region of the first conductivity type opposed to each other with the second gate electrode interposed therebetween.
[0014]
In a method of manufacturing a semiconductor device in which a trench MOS element and a planar MOSFET are integrated on the same substrate, a step of forming a trench in the trench MOS element formation region in a semiconductor substrate; Forming a first diffusion region, forming an isolation region for separating the trench MOS device and the planar MOSFET in the semiconductor substrate, and forming a first region on the trench MOS device formation region and the planar MOSFET formation region. Forming the insulating film, etching the first insulating film by wet etching using the first insulating film on the trench as a mask, forming the trench MOS element formation region and the planar MOSFET. Forming a second insulating film on the region; and forming a first conductive film on the second insulating film. And etching the first conductor by anisotropic etching using the first conductor serving as a gate electrode of the planar MOSFET as a mask, and forming a first gate electrode and the planar MOSFET on the side walls of the trench. Forming a second gate electrode, forming a second diffusion layer of a first conductivity type in contact with the trench sidewall on a surface layer of the semiconductor substrate, and using the second gate electrode as a mask. Forming a third diffusion region of the second conductivity type and a fourth diffusion region of the second conductivity type opposed to each other with the second gate electrode interposed therebetween.
[0015]
In the step of etching the first insulating film, the first insulating film may be etched by wet etching using the first insulating film on the trench MOS element formation region as a mask.
The isolation region may be formed by selective oxidation or an isolation region in which an isolation film is filled in an isolation groove.
The second diffusion region of the trench MOS device may be formed using the second gate electrode and the first and second insulating films as a mask.
Preferably, a spacer is formed on a side wall of the second gate electrode, and an LDD structure is formed using the spacer and the second gate electrode as a mask.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
[Example 1]
FIG. 1 is a sectional view of a main part of a semiconductor device according to a first embodiment of the present invention. FIG. 1 is a schematic cross-sectional view of a device in which a planar lateral MOSFET and a trench lateral power MOSFET constituting a CMOS are integrated. In the following description, a lateral trench power MOSFET is simply referred to as a trench MOSFET, and a lateral planar MOSFET is simply referred to as a planar MOSFET. The CMOS section is composed of an n-channel planar MOSFET and a p-channel planar MOSFET.
[0017]
On a p-semiconductor substrate 1, p-well regions 2, 4 and n-well regions 3, 5 for forming a planar MOSFET and a trench MOSFET forming a CMOS are respectively formed, and a p-well region 4 for forming a planar MOSFET and an n-well region are formed. The gate electrodes 20 and 21 are formed of polysilicon or the like through thin gate oxide films 25 and 26 of about 17 μm on the gate electrode 4, and spacers 22 are formed on side walls of the gate electrodes 20 and 21 to form an n-source region having an LDD structure. Alternatively, an n source / drain region 29 serving as an n drain region and a p source / drain region 30 serving as a p source region or a p drain region are formed.
[0018]
Trenches 7 and 8 are respectively formed in the p-well region 2 and the n-well region 3 for forming the trench MOSFET, and the n-drain region 10 (or n-source region) and the p-drain region 11 (or p-source Regions) are formed, and gate electrodes 18 and 19 are formed of polysilicon or the like on the side walls of the trench 7 through thick gate oxide films 23 and 24 of about 62 μm and contact the trench 7 on the outer surfaces of the trenches 7 and 8. An n source region 27 (or n drain region) and a p source region 28 (p drain region) are formed, and the insides of the gate electrodes 18 and 19 are filled with an oxide film of an interlayer insulating film 31. The n-drain region 10 (or n-source region) and the p-drain region 11 (p-source region) are filled with plug conductors 32 and 33 with polysilicon or the like. The drain electrodes 34 and 35 are formed on the conductors 32 and 33, and the source electrodes 36 and 37 are formed on the source regions 27 and 28 using aluminum or the like. The n-source / drain regions 29 and the p-source / drain regions 30 of the planar MOSFET are formed. Then, source / drain electrodes 38 and 39 are respectively formed of aluminum or the like.
[0019]
By setting the thin gate oxide films 25 and 26 of the planar MOSFET to about 17 nm, a low gate threshold voltage of about 0.8 V ± 0.1 V can be obtained, and the thick gate oxide films 23 and 24 of the trench MOSFET can be reduced to 62 nm. With such a value, a predetermined gate threshold voltage and a high gate breakdown voltage of 60 V or more can be obtained.
[Example 2]
2 to 10 show a method of manufacturing a semiconductor device according to a second embodiment of the present invention, and are cross-sectional views of the main part manufacturing steps shown in the order of steps. This manufacturing method is a method for manufacturing a CMOS portion (planar MOSFET including n-channel MOSFET and p-channel MOSFET) and a trench MOSFET in the semiconductor device of FIG.
[0020]
First, p-well regions 2 and 4 and n-well regions 3 and 5 are selectively formed in the surface layer of p semiconductor substrate 1. If the impurity concentration of the p semiconductor substrate 1 is properly selected, the p well regions 2 and 4 need not always be formed (FIG. 2).
Next, trenches 7 and 8 are formed in a portion where a trench MOSFET is to be formed using, for example, a 400 nm oxide film 6 (thermal oxide film or deposited oxide film) as a mask, and the trenches 7 and 8 are formed using the oxide film 6 as a mask. Is formed (FIG. 3).
Next, n and p drain regions (n or p source regions) are selectively formed on the bottoms 7a and 8a of the trenches, and LOCOS 9 (selective oxide film) for element isolation is formed. At this time, if necessary, field ion implantation (not shown) or ion implantation for preventing punch-through into the CMOS portion may be performed (FIG. 4).
[0021]
Next, a sacrificial oxide film 12 is formed, and a channel region 14 is formed by 13 ion implantation or the like. The formation of the channel region 14 is for adjusting the gate threshold value. If the surface concentrations of the n-well region 4 and the p-well region 5 are appropriate, the formation of the sacrificial oxide film 12 and the channel ion implantation 13 are not necessarily required. And not. In the case of ion implantation, the threshold angle of the trench MOSFET can be adjusted by setting the implantation angle of the ion implantation 13 to, for example, 45 ° and implanting the sidewalls of the trenches 7 and 8 (FIG. 5).
Next, after the sacrificial oxide film 12 is removed, a first oxide film 15 is formed, for example, to a thickness of 50 nm, and the trenches 7 and 8 of the trench MOSFET are masked with, for example, a resist 16 in a photolithography process to form a first oxide film 15 on the CMOS formation region. And the first oxide film 15 on the outer regions of the trenches 7 and 8 is removed by wet etching using a hydrofluoric acid buffer solution. In this wet etching, unlike the anisotropic etching, the surface of the CMOS formation region and the surface of the source formation region of the trench MOSFET are not roughened or damaged (FIG. 6).
[0022]
Next, a second oxide film 17 is formed to a thickness of, for example, 17 nm. That is, a thin oxide film of only the second oxide film 17 is formed on the CMOS formation region, and a thick oxide film of 62 nm in which the first and second oxide films 15 and 17 are stacked is formed on the trench MOSFET formation region. The reason why the thickness of the thick oxide film is 62 nm instead of 67 nm is that the growth rate of the oxide film formed on the thick oxide film is lower than that of the oxide film formed on silicon (FIG. 7).
Next, polysilicon to be the gate electrodes 18, 19, 20, 21 is formed on the entire surface. The polysilicon in the CMOS gate electrode formation region is masked with a resist or the like, and the polysilicon is etched back by anisotropic etching, so that the gate electrodes 18 and 19 in the trench MOSFET portion and the gate electrodes 20 and 21 in the CMOS portion are simultaneously formed. Form. At this time, the gate electrodes 20 and 21 of the CMOS section and the gate electrodes 18 and 19 of the trench MOSFET section may be formed separately using a dedicated photomask (FIG. 8).
[0023]
Next, a region having a low impurity concentration is formed in the CMOS part using the gate electrodes 22 and 21 as a mask. Thereafter, an oxide film of 150 nm is deposited by, for example, a CVD method, and RIE (Reactive Ion Etching) is performed in accordance with a normal CMOS process. This oxide film is etched to form spacers 22 on the side surfaces of the gate electrode in the CMOS portion. When forming this spacer, the second oxide film is removed. Using the spacer 22 and the gate electrodes 20 and 21 as a mask, a region having a high impurity concentration is diffused to form n or p source / drain regions 29 and 30 having an LDD (Light Doped Drain) structure in the CMOS portion. Then, n or p source regions 27 and 28 (n or p drain regions) are formed (FIG. 9).
[0024]
Next, an oxide film to be the interlayer insulating film 31 is formed by a CVD (Chemical Vapor Deposition) method or the like, and then the interlayer insulating film 31 is etched back to expose the bottom surfaces 8a and 9a of the trenches 8 and 9. Next, polysilicon to be the plug conductors 32 and 33 of the trench MOSFET connected to the n drain region 10 and the p drain region 11 is formed by a CVD method or the like, and is etched back. Here, a barrier metal (not shown) (TiN / Ti) may be deposited under the polysilicon. Next, the source electrodes 36 and 37 on the trench MOSFET n source region 27, the source electrodes 36 and 37 on the p source region 28, the drain electrodes 34 and 35 on the p drain region 11, and the n source / drain region of the planar MOSFET. Source / drain electrodes 38 and 39 are formed of aluminum or the like on p and source / drain regions 28 (FIG. 10).
[0025]
As described above, by adopting the twin gate structure having the gate oxide films having different thicknesses, the gate threshold voltage of the planar MOSFET constituting the CMOS portion is reduced, and the gate breakdown voltage of the trench MOSFET is increased. be able to.
Also, unlike the anisotropic etching, the surface of the CMOS formation region is roughened by performing the isotropic etching using a hydrofluoric acid buffer solution on the first oxide film 15 from the CMOS formation region and the region outside the trench. And good electrical characteristics can be obtained without damaging or damaging the surface.
However, as described above, when the first oxide film 15 is removed by wet etching, if the etching amount is large, the first oxide film 15 falls into the trench as shown in FIG. The depressed portion is only the second oxide film 17, and the gate breakdown voltage is reduced in the portion D where the gate oxide film 23 shown in FIG. 11B is thin. When the etching is insufficient, the first oxide film 15 remains on the shoulder of the trench as shown in FIG. 12A, and the thick first oxide film 15 remains as shown in FIG. 12B. The n source region 27 is not formed at the location by ion implantation, and the source region 27 is formed apart from the trench side wall. Then, a high gate voltage needs to be applied in order for the channel formed on the trench side wall to be connected to n source region 27, and the gate threshold voltage increases. Note that L in FIGS. 11A and 12A indicates the amount of depression of the first oxide film 15, and the + sign shown in FIG. 11A indicates that the first oxide film 15 The minus sign shown in FIG. 12A indicates the amount by which the first oxide film 15 remains on the outer region of the trench.
[0026]
Next, a description will be given of a manufacturing method capable of preventing the first oxide film 15 from falling as described above.
[Example 3]
FIGS. 13 to 16 show a method of manufacturing a semiconductor device according to a third embodiment of the present invention, which is a cross-sectional view of a main part manufacturing step shown in the order of steps. 13 to 16 correspond to FIGS. 6 to 9, respectively.
The difference from the second embodiment is that in the photolithography process of FIG. 13 corresponding to FIG. 6, the resists 16a are widely formed over the trenches 7, 8 of the trench MOSFET and the outer regions (source forming regions) of the trenches 7, 8. The point is that the first oxide film 15 is removed from the CMOS portion by masking using a hydrofluoric acid buffer solution, and the first oxide film 15 is left on the outer regions of the trenches 7 and 8. By leaving the first oxide film 15 on the regions outside the trenches 7 and 8 in this manner, it is possible to prevent the first oxide film 15 from dropping from above the trenches 7 and 6 as shown in FIG. The subsequent steps are the same as in the first embodiment.
[0027]
The second oxide film 17 is formed in the step of FIG. 14, and the gate electrodes 18, 19, 20, 21 are formed in the step of FIG. In the step of FIG. 16, an oxide film (not shown) is entirely covered, and an oxide film (not shown), a first oxide film 15 and a second oxide film until the outer regions of the trenches 7 and 8 are exposed by anisotropic etching. 17 is removed. With this anisotropic etching, an oxide film remains on the side surfaces of the gate electrodes 18, 19, 20, and 21, and the oxide film remaining on the side surfaces of the gate electrodes 18, 19 becomes the spacer 22. In the figure, the oxide film remaining on the side surfaces of the gate electrodes 20 and 21 is not drawn.
By doing so, as shown in FIG. 17 corresponding to FIGS. 11B and 12B in an enlarged view of a portion C in FIG. 16, the first MOSFET formed on the trench sidewall of the trench MOSFET is formed. The drop in the portion E of the oxide film 15 can be prevented. Specifically, the amount of depression can be suppressed within ± 10 nm (+ means the amount of depression, and-represents the amount of residue).
[0028]
As described above, the twin gate structure having different gate oxide thicknesses is used, and the thicknesses of the thin gate oxide films 25 and 26 of the planar MOSFETs constituting the CMOS are set to about 17 nm, so that the gates of the planar MOSFETs constituting the CMOS are formed. The threshold voltage can be a gate threshold voltage as low as about 0.8V ± 0.1V. Further, the thickness of the thick gate oxide films 23 and 24 of the trench MOSFET is set to about 62 μm, and the amount of depression of the first oxide film 15 is suppressed to about ± 10 nm, so that the gate breakdown voltage of the trench MOSFET is increased to about 60V. The gate withstand voltage (FIG. 18 described later) can be set, and the gate threshold voltage can be set to a predetermined value (FIG. 19 described later).
[0029]
18 and 19 are diagrams showing the relationship between the amount of depression of the first oxide film 15, the gate breakdown voltage, and the gate threshold voltage. In the drop amount of the first oxide film (L in FIGS. 11 and 12) on the horizontal axis of the drawing, a minus sign (L (-)) indicates a state in which the first oxide film 15 remains on the outer region of the trench ( The sign + (L (+)) indicates the amount by which the first oxide film 15 on the side wall is removed from the upper part of the trench.
As shown in FIG. 18, when the amount of depression of the first oxide film 15 becomes a plus sign, the trench sidewall where the first oxide film falls from the upper portion of the trench is covered with only the thin second oxide film 17, and the gate breakdown voltage is reduced. Decreases. Also, from FIG. 19, when the amount of depression of the first oxide film 15 becomes negative, the source region is formed apart from the trench side wall, so that the gate voltage at which the channel contacts the source region increases and the gate threshold voltage increases. The value increases. From these results, in order to obtain a predetermined gate threshold voltage and a high gate withstand voltage of about 60 V in the trench MOSFET, it is necessary to suppress the fall amount to ± 15 nm. As described above, in the case of the third embodiment, the amount of drop can be set to about ± 10 nm.
[0030]
【The invention's effect】
In the present invention, the CMOS section can have a low threshold voltage and the trench MOSFET section can have a high gate breakdown voltage by making the gate oxide film of the CMOS section thin and the gate oxide film of the trench MOSFET section thick.
Further, the oxide film on the trench MOSFET formation region is masked, the oxide film formed on the CMOS portion is removed by wet etching, and then the thick oxide film formed on the trench MOSFET formation region is anisotropically removed. By etching back with the reactive etching, a thick gate oxide film having a small amount of depression can be formed on the inner wall of the trench. As a result, a trench MOSFET that can ensure a high gate breakdown voltage and a predetermined gate threshold voltage can be manufactured.
[0031]
Further, by removing the thick oxide film on the CMOS portion by wet etching, damage and roughening are prevented from being introduced into the surface of the CMOS portion, and good electrical characteristics can be obtained in the CMOS portion.
[Brief description of the drawings]
FIG. 1 is a sectional view of a main part of a semiconductor device according to a first embodiment of the present invention;
FIG. 2 is a sectional view of a main part manufacturing process of a semiconductor device according to a second embodiment of the present invention;
FIG. 3 is a sectional view of a main part manufacturing step of the semiconductor device according to the second embodiment of the present invention, following FIG. 2;
FIG. 4 is a sectional view of a main part manufacturing step of the semiconductor device according to the second embodiment of the present invention, following FIG. 3;
FIG. 5 is a sectional view of a main part manufacturing step of the semiconductor device according to the second embodiment of the present invention, following FIG. 4;
FIG. 6 is a sectional view of a main part manufacturing step of the semiconductor device according to the second embodiment of the present invention, following FIG. 5;
FIG. 7 is a sectional view of a main part manufacturing step of the semiconductor device according to the second embodiment of the present invention, following FIG. 6;
FIG. 8 is a sectional view of a main part manufacturing step of the semiconductor device according to the second embodiment of the present invention, following FIG. 7;
FIG. 9 is a sectional view of a main part manufacturing step of the semiconductor device according to the second embodiment of the present invention, following FIG. 8;
FIG. 10 is a sectional view of a main part manufacturing step of the semiconductor device according to the second embodiment of the present invention, following FIG. 9;
FIG. 11 is a view showing a case where a first oxide film is dropped from above a trench.
FIG. 12 is a view showing a case where a first oxide film remains on a region outside a trench.
FIG. 13 is a cross-sectional view of a main part manufacturing step of a semiconductor device according to a third embodiment of the present invention
FIG. 14 is a sectional view of a main part manufacturing step of the semiconductor device according to the third embodiment of the present invention, following FIG. 13;
FIG. 15 is a sectional view of a main part manufacturing step of the semiconductor device according to the third embodiment of the present invention, following FIG. 14;
FIG. 16 is a sectional view of a main part manufacturing step of the semiconductor device according to the third embodiment of the present invention, following FIG. 15;
17 is an enlarged view of a portion C in FIG.
FIG. 18 is a diagram showing a relationship between a fall amount of a first oxide film 15 and a gate breakdown voltage;
FIG. 19 is a diagram showing a relationship between a fall amount of a first oxide film 15 and a gate threshold voltage.
FIG. 20 is a cross-sectional view of a main part of a conventional semiconductor device in which a CMOS portion and a trench MOSFET are formed on the same semiconductor substrate.
[Explanation of symbols]
1p semiconductor substrate
2, 3 p-well region
4, 5 n-well area
6 oxide film
7, 8 trench
7a, 8a bottom
9 LOCOS
10 n drain region
11p drain region
12 Sacrificial oxide film
13 Ion implantation
14 Channel area
15 First oxide film
16, 16a resist
17 Second oxide film
18, 19, 20, 21 Gate electrode
22 Spacer
23, 24 Thick gate oxide
25, 26 Thin gate oxide
27 n source region
28p source region
29 n source / drain regions
30p source / drain region
31 Interlayer insulating film
32, 33 Plug conductor
34, 35 Drain electrode
36, 37 Source electrode
38, 39 source / drain electrodes

Claims

A semiconductor device in which a trench MOS element and a planar MOSFET are integrated on the same substrate,
A semiconductor device, wherein the thickness of a gate insulating film of a trench MOS element is larger than the thickness of a gate insulating film of a planar MOSFET.

A semiconductor device in which a trench MOS element and a planar MOSFET are integrated on the same substrate,
A trench formed in the trench MOS element formation region of the semiconductor substrate;
An isolation region for isolating the trench MOS element and the planar MOSFET,
A first diffusion region of a first conductivity type formed on a bottom surface of the trench;
A second diffusion region of a first conductivity type formed in contact with the trench in a surface layer of the semiconductor substrate;
A first gate electrode formed in the planar MOSFET formation region via a first gate insulating film;
A second gate electrode formed on the trench side wall sandwiched between the first diffusion region and the second diffusion region via a second gate insulating film thicker than the first gate insulating film;
A third diffusion region of the first conductivity type and a fourth diffusion region of the first conductivity type opposed to each other across the second gate electrode formed using the second gate electrode as a mask. Semiconductor device.

A semiconductor device in which a trench MOS element and a planar MOSFET are integrated on the same substrate,
A trench formed in the trench MOS element formation region of the semiconductor substrate;
An isolation region for isolating the trench MOS element and the planar MOSFET,
A first diffusion region of a first conductivity type formed on a bottom surface of the trench;
A second diffusion region of a first conductivity type formed in contact with the trench in a surface layer of the semiconductor substrate;
A first gate electrode formed in the planar MOSFET formation region via a first gate insulating film;
A second gate electrode formed on the inner wall of the trench between the first diffusion region and the second diffusion region via a second gate insulating film thicker than the first gate insulating film;
A third diffusion region of a second conductivity type and a fourth diffusion region of the second conductivity type, which are opposed to each other with the second gate electrode formed therebetween using the second gate electrode as a mask. Semiconductor device.

In a method of manufacturing a semiconductor device in which a trench MOS element and a planar MOSFET are integrated on the same substrate,
Forming a trench in the trench MOS element formation region in a semiconductor substrate;
Forming a first diffusion region of a first conductivity type on a bottom surface of the trench;
Forming an isolation region on the semiconductor substrate for isolating the trench MOS element and the planar MOSFET;
Forming a first insulating film on the trench MOS element formation region and the planar MOSFET formation region;
Etching the first insulating film by wet etching using the first insulating film on the trench as a mask;
Forming a second insulating film on the trench MOS element formation region and the planar MOSFET formation region;
A first conductor is formed on the second insulating film, and the first conductor serving as a gate electrode of the planar MOSFET is masked to etch the first conductor by anisotropic etching. Forming a first gate electrode and a second gate electrode of the planar MOSFET on a trench sidewall;
Forming a second diffusion layer of a first conductivity type in contact with the trench sidewall on a surface layer of the semiconductor substrate;
Forming a third diffusion region of the first conductivity type and a fourth diffusion region of the first conductivity type facing each other with the second gate electrode as a mask with the second gate electrode interposed therebetween. Semiconductor device manufacturing method.

In a method of manufacturing a semiconductor device in which a trench MOS element and a planar MOSFET are integrated on the same substrate,
Forming a trench in the trench MOS element formation region in a semiconductor substrate;
Forming a first diffusion region of a first conductivity type on a bottom surface of the trench;
Forming an isolation region on the semiconductor substrate for isolating the trench MOS element and the planar MOSFET;
Forming a first insulating film on the trench MOS element formation region and the planar MOSFET formation region;
Etching the first insulating film by wet etching using the first insulating film on the trench as a mask;
Forming a second insulating film on the trench MOS element formation region and the planar MOSFET formation region;
A first conductor is formed on the second insulating film, and the first conductor serving as a gate electrode of the planar MOSFET is masked to etch the first conductor by anisotropic etching. Forming a first gate electrode and a second gate electrode of the planar MOSFET on a trench sidewall;
Forming a second diffusion layer of a first conductivity type in contact with the trench sidewall on a surface layer of the semiconductor substrate;
Forming a third diffusion region of the second conductivity type and a fourth diffusion region of the second conductivity type facing each other with the second gate electrode interposed therebetween with the second gate electrode as a mask. Semiconductor device manufacturing method.

The step of etching the first insulating film includes:
6. The semiconductor device according to claim 4, wherein the first insulating film on the trench MOS element formation region is masked and the first insulating film is etched by wet etching. Manufacturing method.

7. The method according to claim 4, wherein the isolation region is formed by selective oxidation or an insulation isolation region in which an isolation film is filled in an isolation trench.

The second diffusion region of the trench MOS device is formed using the second gate electrode and the first and second insulating films as a mask. 13. The method for manufacturing a semiconductor device according to item 5.

The spacer according to any one of claims 4 to 6, wherein a spacer is formed on a side wall of the second gate electrode, and an LDD structure is formed using the spacer and the second gate electrode as a mask. A method for manufacturing a semiconductor device.