CN111785641A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
- Publication number
- CN111785641A CN111785641A CN202010872442.0A CN202010872442A CN111785641A CN 111785641 A CN111785641 A CN 111785641A CN 202010872442 A CN202010872442 A CN 202010872442A CN 111785641 A CN111785641 A CN 111785641A
- Authority
- CN
- China
- Prior art keywords
- layer
- source
- gate
- semiconductor substrate
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 155
- 238000000034 method Methods 0.000 title claims abstract description 47
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 39
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 226
- 239000000758 substrate Substances 0.000 claims abstract description 119
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 40
- 238000002955 isolation Methods 0.000 claims abstract description 25
- 238000005530 etching Methods 0.000 claims abstract description 23
- 230000008569 process Effects 0.000 claims abstract description 10
- 239000010410 layer Substances 0.000 claims description 332
- 229920005591 polysilicon Polymers 0.000 claims description 160
- 239000002184 metal Substances 0.000 claims description 42
- 239000011229 interlayer Substances 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 19
- 230000003647 oxidation Effects 0.000 claims description 15
- 238000007254 oxidation reaction Methods 0.000 claims description 15
- 238000005468 ion implantation Methods 0.000 claims description 12
- 230000000149 penetrating effect Effects 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 238000007517 polishing process Methods 0.000 claims description 3
- 229920006395 saturated elastomer Polymers 0.000 abstract description 9
- 230000007704 transition Effects 0.000 abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
Abstract
The invention provides a manufacturing method of a semiconductor device, which mainly comprises the steps of forming an oxide layer and a source polycrystalline silicon layer of which the upper surface is higher than the surface of a semiconductor substrate in a deep groove of the semiconductor substrate; forming a photoresist layer to distinguish the terminal region and the cell region; etching the source polycrystalline silicon layer at the primitive cell region; etching the oxide layer at the primitive cell region to form a gate trench; removing the photoresist; and forming a gate oxide layer and an isolation dielectric layer in the gate trench, and then forming a gate polycrystalline silicon layer. Because the height of the top of the source polycrystalline silicon layer filled in the deep groove is higher than the surface of the semiconductor substrate, the height difference between the top of the source polycrystalline silicon layer and the top of the oxide layer is reduced, and the problem that the gate polycrystalline silicon is not completely etched in the transition region of the gate polycrystalline silicon layer and the source polycrystalline silicon layer is avoided when the gate polycrystalline silicon layer is etched back in the follow-up process, so that the problem that the saturated gate current fails due to the short circuit of the gate and the shielding gate is solved.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuit manufacturing technology, and more particularly, to a method for manufacturing a semiconductor device.
Background
In a shielded gate trench device (SGT, shielded gate power device) mask-subtractive process, a polysilicon residue phenomenon occurs in a transition region between gate polysilicon and shielded gate polysilicon, which finally causes a short circuit between the gate and the shielded gate and causes a saturated gate current (IGSS) failure.
Fig. 1A to 1N are schematic diagrams of device structures in steps of a manufacturing method of a conventional shielded gate trench power device. In the prior art, a manufacturing process of a shielded gate power device includes the following steps:
step one, as shown in fig. 1A, providing a semiconductor substrate such as a silicon substrate 101; the hard mask layer 102 is formed on the surface of the semiconductor substrate 101, and the hard mask layer 102 may be an oxide layer or an oxide layer plus a nitride layer. As shown in fig. 1B and 1C, the hard mask layer 102 is etched by a photolithography process to define a gate formation region, and then the semiconductor substrate 101 is etched by using the hard mask layer 102 as a mask to form a deep trench 103.
Step two, as shown in fig. 1D, the hard mask layer 102 is removed, and an oxide layer 104 is formed on the side surface and the bottom surface of the deep trench 103, wherein the oxide layer 104 extends to cover the surface of the semiconductor substrate 101.
Step three, as shown in fig. 1E, a polysilicon material is filled in the deep trench 103 to form a source polysilicon layer 105, and the source polysilicon layer 105 is generally connected to the source for forming a shield gate.
Step four, as shown in fig. 1F, the source polysilicon layer 105 is etched back, so that the source polysilicon layer 105 outside the deep trench 103 is removed, and the top of the source polysilicon layer 105 in the deep trench 103 is leveled with the semiconductor substrate 101.
Step five, as shown in fig. 1G, a photoresist layer 106 is formed, the photoresist layer 106 covers a part of the source polysilicon layer 105 and a part of the oxide layer 104, a region covered by the photoresist layer 106 is a termination region, and a region not covered by the photoresist layer 106 is a cell region.
Sixthly, as shown in fig. 1H, etching the oxide layer 104 at the cell region to form a gate trench 107 between the semiconductor substrate 101 and the source polysilicon layer 105 at the cell region, wherein a bottom wall of the gate trench 107 is lower than a top surface of the semiconductor substrate 101.
Step seven, as shown in fig. 1I, the photoresist layer 106 is removed, an isolation dielectric layer 108a is formed on the surface of the source polysilicon layer 105, and a gate oxide layer 108b is formed on the surface of the semiconductor substrate 101 in the gate trench 107.
Step eight, as shown in fig. 1J, a gate polysilicon layer 109 is formed, where the gate polysilicon layer 109 is a deep trench gate, and an upper surface of the gate polysilicon layer 109 is flush with the surface of the semiconductor substrate 101.
The terminal region in the subsequent steps has no great change, and is only schematically illustrated by the structural diagram of the primitive cell region.
Step nine, as shown in fig. 1K, a well region 110 and a source region 111 are formed.
Step ten, as shown in fig. 1L, an interlayer film 112 is formed, and a contact hole 113 is formed on the interlayer film 112. As shown in fig. 1M, the contact hole 113 is then filled with metal.
Step eleven, as shown in fig. 1N, forming a front metal layer 114, and performing a patterned etching on the front metal layer 114 by using a photolithography etching process to form a source electrode and a gate electrode, respectively, wherein the source electrode is in contact with the source region 111 at the bottom and the source polysilicon 105 through the contact hole 113, and the gate electrode is in contact with the gate polysilicon layer 109 through the contact hole 113; a drain region and a back metal layer 115 are then formed on the back surface of the semiconductor substrate 101, and the back metal layer 115 is a drain.
In practical applications, the shielded gate trench device formed through the above steps is prone to saturation gate current (IGSS) failure.
Disclosure of Invention
The invention aims to provide a manufacturing method of a semiconductor device, which aims to solve the problem that a shielded gate trench device formed by the prior art is easy to have saturated gate current (IGSS) failure.
The inventors have discovered that shielded gate trench devices formed by the prior art are susceptible to saturation gate current (IGSS) failure due to: after the source polysilicon layer is etched back, the surface height of the source polysilicon layer is lower than that of the oxide layer because the oxide layer is also arranged on the surface of the substrate. Due to this height difference, more polysilicon is deposited on the surface of the source polysilicon layer during the gate polysilicon layer filling process. When the gate polysilicon layer is etched back, the height of the gate polysilicon layer needs to be flush with that of the source polysilicon layer, so that polysilicon deposited on the upper surface of the isolation dielectric layer is not easy to be etched completely, and polysilicon residues exist at corners of the isolation dielectric layer after etching (as shown in fig. 2). Because polysilicon residue exists on the corners of the isolation dielectric layer, the gate and the shield gate are easily short-circuited, and the saturated gate current (IGSS) fails.
In view of the above, in order to solve the above technical problems, the present invention provides a method for manufacturing a semiconductor device, the semiconductor device being used for forming a shielded gate power device, the method comprising:
providing a semiconductor substrate, and forming a deep groove in the semiconductor substrate;
forming an oxide layer which covers the bottom wall and the side wall of the deep groove and extends to cover the top surface of the semiconductor substrate;
filling the deep trench with a polysilicon material to form a source polysilicon layer, wherein the upper surface of the source polysilicon layer is higher than the top surface of the semiconductor substrate;
forming a photoresist layer, wherein the photoresist layer covers a part of a source polycrystalline silicon layer and a part of an oxidation layer, a region covered by the photoresist layer is a terminal region, and a region not covered by the photoresist layer is a primitive cell region;
etching the source polycrystalline silicon layer at the primitive cell region until the upper surface of the source polycrystalline silicon layer is flush with the top surface of the semiconductor substrate;
etching the oxide layer at the cell region to form a gate trench between the semiconductor substrate and the source polysilicon layer at the cell region;
removing the photoresist layer;
forming an isolation medium layer on the surface of the source polycrystalline silicon layer, and forming a gate oxide layer on the surface of the semiconductor substrate in the gate trench;
and filling the gate trench with a polysilicon material to form a gate polysilicon layer, wherein the upper surface of the gate polysilicon layer is flush with the surface of the semiconductor substrate.
Optionally, in the method for manufacturing a semiconductor device, a height difference between the surface of the source polysilicon layer and the surface of the oxide layer is not more than 20% of the thickness of the oxide layer.
Optionally, in the method for manufacturing a semiconductor device, an upper surface of the source polysilicon layer is flush with a surface of the oxide layer.
Optionally, in the manufacturing method of the semiconductor device, the method for filling the deep trench with the polysilicon material to form the source polysilicon layer includes:
filling the deep groove with a polysilicon material and extending to cover the surface of the oxide layer;
and removing the source polycrystalline silicon layer on the surface of the oxidation layer by adopting a chemical mechanical polishing process, and keeping the upper surface of the source polycrystalline silicon layer flush with the surface of the oxidation layer.
Optionally, in the manufacturing method of the semiconductor device, the method for forming the deep trench in the semiconductor substrate includes:
forming a patterned hard mask layer on the top surface of the semiconductor substrate;
etching the semiconductor substrate by taking the patterned hard mask layer as a mask to form a deep groove;
and removing the hard mask layer.
Optionally, in the manufacturing method of the semiconductor device, the gate oxide layer and the isolation dielectric layer are formed simultaneously by a thermal oxidation process.
Optionally, in the method for manufacturing a semiconductor device, after forming the gate polysilicon layer, the method for manufacturing a semiconductor device further includes:
forming a well region and a source region which are mutually overlapped from bottom to top on the top of the semiconductor substrate in sequence;
forming an interlayer film covering the top surface of the semiconductor substrate, the gate oxide layer, the isolation dielectric layer, the gate polysilicon layer and the source polysilicon layer;
forming a plurality of contact holes penetrating the interlayer film, filling metal in each of the contact holes to form a metal plug, and forming a source electrode and a gate electrode on the interlayer film, part of the metal plugs conducting the gate electrode and the gate polysilicon layer, the other part of the metal plugs conducting the source electrode and the source polysilicon layer, and the source electrode and the source region;
and forming a drain region at the bottom of the semiconductor substrate, and forming a back metal layer on the bottom surface of the semiconductor substrate, wherein the back metal layer is a drain.
Optionally, in the manufacturing method of the semiconductor device, the semiconductor substrate is doped with the first conductivity type, and the method of sequentially forming the well region and the source region overlapping each other on the top of the semiconductor substrate from bottom to top includes:
and sequentially performing second conductive type ion implantation and first conductive type ion implantation on the top of the semiconductor substrate from bottom to top so as to sequentially form a well region and a source region which are overlapped with each other.
Optionally, in the method for manufacturing a semiconductor device, before filling metal in each of the contact holes to form a metal plug, the method for manufacturing a semiconductor device further includes: and carrying out second conductive type heavily doped ion implantation on the source region for conducting with the source electrode to form a well region contact region.
Optionally, in the manufacturing method of the semiconductor device, the semiconductor substrate is doped with a first conductivity type, and the method of forming the drain region at the bottom of the semiconductor substrate includes: and carrying out ion implantation of the first conductivity type on the bottom of the semiconductor substrate to form a drain region.
The invention provides a manufacturing method of a semiconductor device, which comprises the steps of providing a semiconductor substrate, and forming a deep groove in the semiconductor substrate; forming an oxide layer covering the bottom wall and the side wall of the deep trench; filling the deep trench with a polysilicon material to form a source polysilicon layer, wherein the upper surface of the source polysilicon layer is higher than the top surface of the semiconductor substrate; forming a photoresist layer, wherein the photoresist layer covers a part of a source polycrystalline silicon layer and a part of an oxidation layer, a region covered by the photoresist layer is a terminal region, and a region not covered by the photoresist layer is a primitive cell region; etching the source polycrystalline silicon layer at the primitive cell region until the upper surface of the source polycrystalline silicon layer is flush with the top surface of the semiconductor substrate; etching the oxide layer at the cell region to form a gate trench between the semiconductor substrate and the source polysilicon layer at the cell region; removing the photoresist layer; forming an isolation medium layer on the surface of the source polycrystalline silicon layer, and forming a gate oxide layer on the surface of the semiconductor substrate in the gate trench; and filling the gate trench with a polysilicon material to form a gate polysilicon layer, wherein the upper surface of the gate polysilicon layer is flush with the surface of the semiconductor substrate. After the deep groove on the semiconductor substrate is filled with the source polycrystalline silicon, when the source polycrystalline silicon layer is etched back, the top of the source polycrystalline silicon is higher than the surface of the semiconductor substrate, so that the height difference between the top of the source polycrystalline silicon layer and the top of the oxide layer is reduced, and the gate polycrystalline silicon layer can be completely etched in the subsequent etching of the gate polycrystalline silicon layer, thereby avoiding the phenomenon of polycrystalline silicon residue in the transition region of the gate polycrystalline silicon and the source polycrystalline silicon, and solving the problem of saturated gate current failure caused by the short circuit of a gate and a shielding gate.
Drawings
FIGS. 1A-1N are schematic views of device structures at various steps of a prior art fabrication method;
FIG. 2 is a schematic diagram illustrating polysilicon residue occurring during gate polysilicon etchback in the prior art;
FIG. 3 is a flow chart illustrating the steps of fabricating a gate structure according to the present embodiment;
fig. 4A to 4P are schematic views of device structures in the steps of the manufacturing method provided in this embodiment;
wherein the reference numerals are as follows:
101-a semiconductor substrate; 102-hard mask layer; 103-deep trench; 104-an oxide layer; 105-a source polysilicon layer; 106-photoresist layer; 107-gate trenches; 108 a-an isolation dielectric layer; 108 b-a gate oxide layer; 109-a gate polysilicon layer; 109 a-gate polysilicon residue; 110-well region; a 111-source region; 112-interlayer film; 113-a contact hole; 114-front side metal layer; 115-back side metal layer;
201-a semiconductor substrate; 202-hard mask layer; 203-deep trenches; 204-an oxide layer; 205-source polysilicon layer; 206-photoresist layer; 207 a gate trench; 208 a-an isolation dielectric layer; 208 b-a gate oxide layer; 209-gate polysilicon layer; 210-well region; 210 a-a well region contact region; 211-a source region; 212-an interlayer film; 213-contact holes; 214-front side metal layer; 215-back side metal layer.
Detailed Description
The following describes a method for manufacturing a semiconductor device according to the present invention in further detail with reference to the accompanying drawings and specific embodiments. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. Further, the structures illustrated in the drawings are often part of actual structures. In particular, the drawings may have different emphasis points and may sometimes be scaled differently.
The present embodiment provides a method for manufacturing a semiconductor device, where the semiconductor device is used to form a shielded gate power device, as shown in fig. 3, the method for manufacturing the semiconductor device includes:
s1, providing a semiconductor substrate, and forming a deep groove in the semiconductor substrate;
s2, forming an oxide layer which covers the bottom wall and the side wall of the deep groove and extends to cover the top surface of the semiconductor substrate;
s3, filling the deep groove with a polysilicon material to form a source polysilicon layer, wherein the upper surface of the source polysilicon layer is higher than the top surface of the semiconductor substrate;
s4, forming a photoresist layer, wherein the photoresist layer covers a part of the source polysilicon layer and a part of the oxide layer, the region covered by the photoresist layer is a terminal region, and the region not covered by the photoresist layer is a primitive cell region;
s5, etching the source polycrystalline silicon layer at the primitive cell region until the upper surface of the source polycrystalline silicon layer is flush with the top surface of the semiconductor substrate;
s6, etching the oxide layer at the cell region to form a gate trench between the semiconductor substrate and the source polysilicon layer at the cell region;
s7, removing the photoresist layer;
s8, forming an isolation medium layer on the surface of the source polycrystalline silicon layer, and forming a gate oxide layer on the surface of the semiconductor substrate in the gate trench;
and S9, filling the gate trench with a polysilicon material to form a gate polysilicon layer, wherein the upper surface of the gate polysilicon layer is flush with the surface of the semiconductor substrate.
According to the manufacturing method of the semiconductor device, after the source polycrystalline silicon layer is filled and etched back in the deep groove on the semiconductor substrate, the top of the source polycrystalline silicon layer is higher than the surface of the semiconductor substrate, so that the height difference between the top of the source polycrystalline silicon layer and the top of the oxide layer is reduced, and the gate polycrystalline silicon can be completely etched in the subsequent etching of the gate polycrystalline silicon layer, and therefore the phenomenon of polycrystalline silicon residue in the transition region of the gate polycrystalline silicon and the source polycrystalline silicon is avoided, and the problem of saturated gate current failure caused by short circuit of a gate and a shielding gate is solved.
Further, in the method for manufacturing a semiconductor device provided in this embodiment, after forming the gate polysilicon layer, the method for manufacturing a semiconductor device further includes:
s10, forming a well region and a source region which are mutually overlapped on the top of the semiconductor substrate from bottom to top in sequence;
s11, forming an interlayer film covering the top surface of the semiconductor substrate, the gate oxide layer, the isolation dielectric layer, the gate polysilicon layer and the source polysilicon layer;
s12, forming a plurality of contact holes penetrating the interlayer film, filling metal in each of the contact holes to form a metal plug, and forming a source electrode and a gate electrode on the interlayer film, wherein a part of the metal plug connects the gate electrode and the gate polysilicon layer, and another part of the metal plug connects the source electrode and the source polysilicon layer, and the source electrode and the source region;
and S13, forming a drain region at the bottom of the semiconductor substrate, and forming a back metal layer on the bottom surface of the semiconductor substrate, wherein the back metal layer is a drain.
Hereinafter, the method for manufacturing the semiconductor device provided in this embodiment will be described in detail with reference to fig. 4A to 4P, and it should be noted that the following description is only a preferred implementation manner, and those skilled in the art should be able to easily derive other implementation manners without departing from the essence of this embodiment.
First, as shown in fig. 4A, a semiconductor substrate 201 is provided, and a patterned hard mask layer 202 is formed on a top surface of the semiconductor substrate 201. The semiconductor substrate 201 may be a silicon substrate, and the hard mask layer 202 may be an oxide layer or an oxide layer plus a nitride layer. Specifically, the hard mask layer 202 may be patterned by a photolithography process to define a gate formation region.
Then, as shown in fig. 4B, the semiconductor substrate 201 is etched by using the patterned hard mask layer 202 as a mask, so as to form a deep trench 203 in the semiconductor substrate 201.
After forming the deep trench, as shown in fig. 4C, the hard mask layer 202 is removed, and an oxide layer 204 is formed, wherein the oxide layer 204 covers the bottom wall and the sidewall of the deep trench 203 and extends to cover the top surface of the semiconductor substrate 201.
Next, the deep trench 203 is filled with a polysilicon material to form a source polysilicon layer 205, wherein an upper surface of the source polysilicon layer 205 is higher than a top surface of the semiconductor substrate 201. Specifically, as shown in fig. 4D, the deep trench 203 is filled with a polysilicon material and extends to cover the surface of the oxide layer 204, so as to form the source polysilicon layer 205; next, as shown in fig. 4E, the source polysilicon layer 205 is etched back to remove the source polysilicon layer 205 on the oxide layer 204, and the upper surface of the source polysilicon layer 205 is higher than the top surface of the semiconductor substrate 201.
Preferably, the height difference between the surface of the source polysilicon layer 205 and the surface of the oxide layer 204 is not more than 20% of the thickness of the oxide layer 204. In this way, the height difference between the surface of the source polysilicon layer 205 and the surface of the oxide layer 204 is not obvious, so that when polysilicon is filled to form gate polysilicon in the following, less polysilicon is deposited on the source polysilicon layer 205, and further, when the gate polysilicon layer is etched back, the polysilicon deposited on the source polysilicon layer 205 can be etched clean.
Preferably, the surface of the source polysilicon layer 205 is flush with the surface of the oxide layer 204. Therefore, the top surface height of the source polysilicon layer 205 is favorably controlled when the source polysilicon layer 205 is etched back, and the thickness of the polysilicon on the source polysilicon layer 205 is consistent with that of the polysilicon on the oxide layer 204 when the polysilicon is filled to form gate polysilicon, so that when the gate polysilicon is etched back, the polysilicon on the oxide layer 204 is etched cleanly while the polysilicon on the source polysilicon layer 205 is etched cleanly.
A chemical mechanical polishing process is usually used to remove the source polysilicon layer 205 on the surface of the oxide layer 204, and the upper surface of the source polysilicon layer 205 is made to be flush with the surface of the oxide layer 204. Through chemical mechanical polishing, the height of the top of the source polycrystalline silicon layer 205 is consistent with that of the top of the oxidation layer 204, and then when the gate polycrystalline silicon is etched back, the polycrystalline silicon on the oxidation layer 204 can be completely etched while the polycrystalline silicon on the source polycrystalline silicon layer 205 is completely etched, so that the phenomenon of polycrystalline silicon residue in a transition region of the gate polycrystalline silicon and the shield gate polycrystalline silicon is avoided, and the problem of saturated gate current failure caused by short circuit of a gate and the shield gate is solved.
Next, as shown in fig. 4F, a photoresist layer 206 is formed, the photoresist layer 206 covers a portion of the source polysilicon layer 205 and a portion of the oxide layer 204, a region covered by the photoresist layer 206 is a termination region, and a region not covered by the photoresist layer 206 is a cell region.
Hereinafter, the structures of the termination region and the cell region in each step will be shown and described in steps.
As shown in fig. 4G, the source polysilicon layer 205 at the cell region is etched until the upper surface of the source polysilicon layer 205 and the top surface of the semiconductor substrate 201 are leveled. The method for etching the source polysilicon layer 205 is dry etching.
Next, as shown in fig. 4H, the oxide layer 204 at the cell region is etched to form a gate trench 207 between the semiconductor substrate 201 and the source polysilicon layer 205 at the cell region. The gate trench 207 exposes a portion of the sidewall of the semiconductor substrate 201 and a portion of the sidewall of the source polysilicon layer 205. In this embodiment, the method for etching the oxide layer 204 is wet etching.
In the above step, the termination region is protected by the covering with the photoresist layer 206, and its structure is not changed. Thereafter, as shown in fig. 4I, the photoresist layer 206 is removed.
Then, as in the prior art. As shown in fig. 4J, an isolation dielectric layer 208a is formed on the surface of the source polysilicon layer 205, and a gate oxide layer 208b is formed on the surface of the semiconductor substrate 201 in the gate trench 207. In the present embodiment, the isolation dielectric layer 208a and the gate oxide layer 208b are simultaneously formed through a thermal oxidation process.
The thermal oxidation process has the advantage that the isolation dielectric layer 208a and the gate oxide layer 208b can be formed simultaneously, thereby saving the process steps and time. It should be noted that the isolation dielectric layer 208a, i.e., the inter-poly isolation silicon oxide, is formed by oxidizing the poly at the outer periphery of the source poly layer (i.e., the shield gate) 205; the gate oxide layer 208b is formed by oxidation of silicon in the silicon substrate 201 lateral to the deep trench 203.
Then, the gate trench 207 is filled with a polysilicon material to form a gate polysilicon layer 209, and an upper surface of the gate polysilicon layer 209 is flush with the surface of the semiconductor substrate 201. Specifically, as shown in fig. 4K, a polysilicon material is filled so that the gate polysilicon layer 209 fills the gate trench 207 and extends to cover the oxide layer 204 and the surface of the isolation dielectric layer 208 a; as shown in fig. 4L, the gate polysilicon layer 209 is etched back to remove the gate polysilicon layer 209 on the oxide layer 204 and the isolation dielectric layer 208a, and the upper surface of the gate polysilicon layer 209 is flush with the surface of the semiconductor substrate 201.
Because the top surface of the formed source polysilicon layer 205 is higher than the surface of the semiconductor substrate 201 when the source polysilicon layer 205 is formed, the height difference between the top of the source polysilicon layer 205 and the top of the oxide layer 204 is small, so that the thickness of the gate polysilicon layer 209 deposited on the source polysilicon layer 205 is small, and the gate polysilicon on the source polysilicon layer 205 is conveniently etched cleanly when the gate polysilicon layer 209 is etched back. Therefore, the method provided by the embodiment can etch the polysilicon deposited around the source polysilicon layer 205 clean when the gate polysilicon layer 209 is etched back, thereby avoiding the phenomenon of polysilicon residue in the transition region between the gate polysilicon and the shield gate polysilicon, and solving the problem of saturated gate current failure caused by short circuit between the gate and the shield gate.
Since the subsequent processes are mainly formed in the cell region, the cell region is illustrated. As shown in fig. 4M, a well region 210 and a source region 211 are formed on the top of the semiconductor substrate 201 in sequence from bottom to top. In this embodiment, the semiconductor substrate 201 is doped with a first conductivity type, and the top of the semiconductor substrate 201 is sequentially subjected to a second conductivity type ion implantation and a first conductivity type ion implantation from bottom to top to sequentially form a well region 210 and a source region 211 which are overlapped with each other.
Next, as shown in fig. 4O, forming an interlayer film 212, wherein the interlayer film 212 covers the top surface of the semiconductor substrate 201, the isolation dielectric layer 208a, the gate oxide layer 208b, the gate polysilicon layer 209 and the source polysilicon layer 205; thereafter, a plurality of contact holes penetrating the interlayer film 212 are formed, and metal is filled in each of the contact holes to form a metal plug 213, and a source electrode and a gate electrode are formed on the interlayer film 212, a portion of the metal plug 213 turning on the gate electrode and the gate polysilicon layer 209, another portion of the metal plug 213 turning on the source electrode and the source polysilicon layer 205, and the source electrode and the source region 211. In the present embodiment, the method of forming the source electrode and the gate electrode on the interlayer film 212 includes: forming a front metal layer 214, the front metal layer 214 covering the interlayer film 212; the front metal layer 214 is etched to form a source and a gate.
In this embodiment, before filling metal in each contact hole to form the metal plug 213, as shown in fig. 4N, ion implantation of second conductivity type heavy doping is performed on the source region 211 for conducting with the source to form the well region contact region 210 a.
Finally, as shown in fig. 4P, a drain region (not shown) is formed at the bottom of the semiconductor substrate 201, and a back metal layer 215 is formed on the bottom surface of the semiconductor substrate 201, where the back metal layer 215 is a drain. In this embodiment, the semiconductor substrate 201 is doped with a first conductivity type, and the method for forming the drain region at the bottom of the semiconductor substrate 201 includes: and carrying out heavily doped ion implantation of the first conductivity type on the bottom of the semiconductor substrate 201 to form a drain region.
It is noted that the semiconductor device may be an N-type device or a P-type device. When the semiconductor device is an N-type device, the first conduction type is an N type, the second conduction type is a P type, and the semiconductor substrate is doped with the N type; when the semiconductor device is a P-type device, the first conductivity type is P-type, the second conductivity type is N-type, and the semiconductor substrate is doped P-type.
In summary, the method for manufacturing a semiconductor device provided by the present invention includes providing a semiconductor substrate, forming a deep trench in the semiconductor substrate; forming an oxide layer covering the bottom wall and the side wall of the deep trench; filling the deep trench with a polysilicon material to form a source polysilicon layer, wherein the upper surface of the source polysilicon layer is higher than the top surface of the semiconductor substrate; forming a photoresist layer, wherein the photoresist layer covers a part of a source polycrystalline silicon layer and a part of an oxidation layer, a region covered by the photoresist layer is a terminal region, and a region not covered by the photoresist layer is a primitive cell region; etching the source polycrystalline silicon layer at the primitive cell region until the upper surface of the source polycrystalline silicon layer is flush with the top surface of the semiconductor substrate; etching the oxide layer at the cell region to form a gate trench between the semiconductor substrate and the source polysilicon layer at the cell region; removing the photoresist layer; forming an isolation medium layer on the surface of the source polycrystalline silicon layer, and forming a gate oxide layer on the surface of the semiconductor substrate in the gate trench; and filling the gate trench with a polysilicon material to form a gate polysilicon layer, wherein the upper surface of the gate polysilicon layer is flush with the surface of the semiconductor substrate. After the deep groove on the semiconductor substrate is filled with the source polycrystalline silicon, when the source polycrystalline silicon layer is etched back, the top of the source polycrystalline silicon is higher than the surface of the semiconductor substrate, so that the height difference between the top of the source polycrystalline silicon layer and the top of the oxide layer is reduced, and the gate polycrystalline silicon layer can be completely etched in the subsequent etching of the gate polycrystalline silicon layer, thereby avoiding the phenomenon of polycrystalline silicon residue in the transition region of the gate polycrystalline silicon and the source polycrystalline silicon, and solving the problem of saturated gate current failure caused by the short circuit of a gate and a shielding gate.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (10)
1. A method of manufacturing a semiconductor device for forming a shielded gate power device, the method comprising:
providing a semiconductor substrate, and forming a deep groove in the semiconductor substrate;
forming an oxide layer which covers the bottom wall and the side wall of the deep groove and extends to cover the top surface of the semiconductor substrate;
filling the deep trench with a polysilicon material to form a source polysilicon layer, wherein the upper surface of the source polysilicon layer is higher than the top surface of the semiconductor substrate;
forming a photoresist layer, wherein the photoresist layer covers a part of a source polycrystalline silicon layer and a part of an oxidation layer, a region covered by the photoresist layer is a terminal region, and a region not covered by the photoresist layer is a primitive cell region;
etching the source polycrystalline silicon layer at the primitive cell region until the upper surface of the source polycrystalline silicon layer is flush with the top surface of the semiconductor substrate;
etching the oxide layer at the cell region to form a gate trench between the semiconductor substrate and the source polysilicon layer at the cell region;
removing the photoresist layer;
forming an isolation medium layer on the surface of the source polycrystalline silicon layer, and forming a gate oxide layer on the surface of the semiconductor substrate in the gate trench;
and filling the gate trench with a polysilicon material to form a gate polysilicon layer, wherein the upper surface of the gate polysilicon layer is flush with the surface of the semiconductor substrate.
2. The method according to claim 1, wherein a difference in height between a surface of the source polysilicon layer and a surface of the oxide layer is not more than 20% of a thickness of the oxide layer.
3. The method for manufacturing a semiconductor device according to claim 2, wherein an upper surface of the source polysilicon layer is flush with a surface of the oxide layer.
4. The method of claim 3, wherein the filling the deep trench with a polysilicon material to form a source polysilicon layer comprises:
filling the deep groove with a polysilicon material and extending to cover the surface of the oxide layer;
and removing the source polycrystalline silicon layer on the surface of the oxidation layer by adopting a chemical mechanical polishing process, and keeping the upper surface of the source polycrystalline silicon layer flush with the surface of the oxidation layer.
5. The method of manufacturing a semiconductor device according to claim 1, wherein the method of forming the deep trench in the semiconductor substrate comprises:
forming a patterned hard mask layer on the top surface of the semiconductor substrate;
etching the semiconductor substrate by taking the patterned hard mask layer as a mask to form a deep groove;
and removing the hard mask layer.
6. The method of manufacturing a semiconductor device according to claim 1, wherein the gate oxide layer and the isolation dielectric layer are simultaneously formed by a thermal oxidation process.
7. The method of manufacturing a semiconductor device according to claim 1, wherein after forming the gate polysilicon layer, the method of manufacturing a semiconductor device further comprises:
forming a well region and a source region which are mutually overlapped from bottom to top on the top of the semiconductor substrate in sequence;
forming an interlayer film covering the top surface of the semiconductor substrate, the gate oxide layer, the isolation dielectric layer, the gate polysilicon layer and the source polysilicon layer;
forming a plurality of contact holes penetrating the interlayer film, filling metal in each of the contact holes to form a metal plug, and forming a source electrode and a gate electrode on the interlayer film, part of the metal plugs conducting the gate electrode and the gate polysilicon layer, the other part of the metal plugs conducting the source electrode and the source polysilicon layer, and the source electrode and the source region;
and forming a drain region at the bottom of the semiconductor substrate, and forming a back metal layer on the bottom surface of the semiconductor substrate, wherein the back metal layer is a drain.
8. The method of claim 7, wherein the semiconductor substrate is doped with the first conductivity type, and the step of sequentially forming the well region and the source region overlapping each other on the top of the semiconductor substrate from bottom to top comprises:
and sequentially performing second conductive type ion implantation and first conductive type ion implantation on the top of the semiconductor substrate from bottom to top so as to sequentially form a well region and a source region which are overlapped with each other.
9. The method of manufacturing a semiconductor device according to claim 7, wherein before the filling of metal in each of the contact holes to form a metal plug, the method further comprises: and carrying out second conductive type heavily doped ion implantation on the source region for conducting with the source electrode to form a well region contact region.
10. The method of manufacturing a semiconductor device according to claim 7, wherein the semiconductor substrate is doped with the first conductivity type, and the method of forming the drain region at the bottom of the semiconductor substrate comprises: and carrying out ion implantation of the first conductivity type on the bottom of the semiconductor substrate to form a drain region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010872442.0A CN111785641B (en) | 2020-08-26 | 2020-08-26 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010872442.0A CN111785641B (en) | 2020-08-26 | 2020-08-26 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111785641A true CN111785641A (en) | 2020-10-16 |
| CN111785641B CN111785641B (en) | 2024-02-02 |
Family
ID=72762916
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010872442.0A Active CN111785641B (en) | 2020-08-26 | 2020-08-26 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111785641B (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112233983A (en) * | 2020-10-27 | 2021-01-15 | 上海华虹宏力半导体制造有限公司 | Trench gate power device and preparation method thereof |
| CN112802751A (en) * | 2020-12-31 | 2021-05-14 | 广州粤芯半导体技术有限公司 | Preparation method of groove type power device |
| CN112928058A (en) * | 2021-01-20 | 2021-06-08 | 华虹半导体(无锡)有限公司 | Deep trench isolation forming method of CIS device and semiconductor device structure |
| CN116031153A (en) * | 2023-03-28 | 2023-04-28 | 江苏长晶科技股份有限公司 | Manufacturing method and structure of trench MOSFET device |
| CN117410173A (en) * | 2023-12-15 | 2024-01-16 | 中晶新源(上海)半导体有限公司 | Manufacturing method of trench semiconductor device with stepped dielectric layer |
| CN112908841B (en) * | 2021-03-24 | 2024-03-22 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing semiconductor device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102856182A (en) * | 2011-06-27 | 2013-01-02 | 半导体元件工业有限责任公司 | Method of making an insulated gate semiconductor device and structure |
| CN106876279A (en) * | 2017-03-31 | 2017-06-20 | 上海华虹宏力半导体制造有限公司 | Shield grid groove power device and its manufacture method |
| US20170263768A1 (en) * | 2016-03-11 | 2017-09-14 | Kabushiki Kaisha Toshiba | Semiconductor device |
| CN107799601A (en) * | 2017-09-29 | 2018-03-13 | 上海华虹宏力半导体制造有限公司 | Shield grid groove power MOSTET devices and its manufacture method |
| CN108039369A (en) * | 2017-11-30 | 2018-05-15 | 上海华虹宏力半导体制造有限公司 | Shield grid groove MOSFET and its manufacture method |
| CN108701715A (en) * | 2016-03-31 | 2018-10-23 | 新电元工业株式会社 | The manufacturing method and semiconductor device of semiconductor device |
-
2020
- 2020-08-26 CN CN202010872442.0A patent/CN111785641B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102856182A (en) * | 2011-06-27 | 2013-01-02 | 半导体元件工业有限责任公司 | Method of making an insulated gate semiconductor device and structure |
| US20170263768A1 (en) * | 2016-03-11 | 2017-09-14 | Kabushiki Kaisha Toshiba | Semiconductor device |
| CN108701715A (en) * | 2016-03-31 | 2018-10-23 | 新电元工业株式会社 | The manufacturing method and semiconductor device of semiconductor device |
| CN106876279A (en) * | 2017-03-31 | 2017-06-20 | 上海华虹宏力半导体制造有限公司 | Shield grid groove power device and its manufacture method |
| CN107799601A (en) * | 2017-09-29 | 2018-03-13 | 上海华虹宏力半导体制造有限公司 | Shield grid groove power MOSTET devices and its manufacture method |
| CN108039369A (en) * | 2017-11-30 | 2018-05-15 | 上海华虹宏力半导体制造有限公司 | Shield grid groove MOSFET and its manufacture method |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112233983A (en) * | 2020-10-27 | 2021-01-15 | 上海华虹宏力半导体制造有限公司 | Trench gate power device and preparation method thereof |
| CN112233983B (en) * | 2020-10-27 | 2024-02-20 | 上海华虹宏力半导体制造有限公司 | Trench gate power device and preparation method thereof |
| CN112802751A (en) * | 2020-12-31 | 2021-05-14 | 广州粤芯半导体技术有限公司 | Preparation method of groove type power device |
| CN112928058A (en) * | 2021-01-20 | 2021-06-08 | 华虹半导体(无锡)有限公司 | Deep trench isolation forming method of CIS device and semiconductor device structure |
| CN112908841B (en) * | 2021-03-24 | 2024-03-22 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing semiconductor device |
| CN116031153A (en) * | 2023-03-28 | 2023-04-28 | 江苏长晶科技股份有限公司 | Manufacturing method and structure of trench MOSFET device |
| CN117410173A (en) * | 2023-12-15 | 2024-01-16 | 中晶新源(上海)半导体有限公司 | Manufacturing method of trench semiconductor device with stepped dielectric layer |
| CN117410173B (en) * | 2023-12-15 | 2024-03-08 | 中晶新源(上海)半导体有限公司 | Manufacturing method of trench semiconductor device with stepped dielectric layer |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111785641B (en) | 2024-02-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111785641A (en) | Method for manufacturing semiconductor device | |
| KR100801063B1 (en) | Gate all around type semiconductor device and method of manufacturing the same | |
| KR100302189B1 (en) | semiconductor device having SOI structure and method for fabricating the same | |
| KR20110078021A (en) | Semiconductor device with vertical cell and mehtod for manufacturing the same | |
| CN110957318A (en) | Semiconductor structure and manufacturing method thereof | |
| CN111785642B (en) | Method for manufacturing semiconductor device | |
| KR100759215B1 (en) | Capacitor in the semiconductor device and method of fabricating the same | |
| TWI443778B (en) | Method of fabricating a cell contact and a digit line for a semiconductor device | |
| CN114242596A (en) | MOSFET device and manufacturing method thereof | |
| CN111883583A (en) | Shielded gate trench power device and method of making same | |
| KR100364798B1 (en) | Method for fabricating of semiconductor mwmory device | |
| CN114388616A (en) | Semiconductor structure and forming method thereof | |
| TW202147526A (en) | Semiconductor memory device having guard pillars and manufacturing method thereof | |
| US6682976B2 (en) | Method for manufacturing a nonvolatile semiconductor memory device | |
| KR100414730B1 (en) | Method for manufacturing capacitor of semiconductor device | |
| JP3685997B2 (en) | Substrate having recess suitable for integrated circuit device and method for manufacturing the same | |
| KR100336784B1 (en) | Fabricating method of semiconductor device | |
| CN113903660B (en) | Method for manufacturing semiconductor device | |
| KR100694996B1 (en) | Method for manufacturing capacitor in semiconductor device | |
| KR100213203B1 (en) | Semiconductor device with contact hole and process for fabricating the same | |
| KR100310543B1 (en) | Method of forming a semiconductor device | |
| KR100267773B1 (en) | Method for fabricating semiconductor device | |
| KR100325288B1 (en) | Capacitor and method for manufacturing the same | |
| KR100268918B1 (en) | Semiconductor device and method for fabricating the same | |
| CN112289861A (en) | Semiconductor structure and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |