CN105514022B - The method that portion surface forms field silica in the trench - Google Patents
The method that portion surface forms field silica in the trench Download PDFInfo
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- CN105514022B CN105514022B CN201511026455.1A CN201511026455A CN105514022B CN 105514022 B CN105514022 B CN 105514022B CN 201511026455 A CN201511026455 A CN 201511026455A CN 105514022 B CN105514022 B CN 105514022B
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- trench
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 title claims abstract description 241
- 239000000377 silicon dioxide Substances 0.000 title claims abstract description 116
- 238000000034 method Methods 0.000 title claims abstract description 57
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 36
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 36
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 29
- 230000008569 process Effects 0.000 claims abstract description 19
- 238000001039 wet etching Methods 0.000 claims abstract description 18
- 238000001259 photo etching Methods 0.000 claims abstract description 16
- 238000000576 coating method Methods 0.000 claims abstract description 7
- 239000011248 coating agent Substances 0.000 claims abstract description 5
- 239000010410 layer Substances 0.000 claims description 147
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 47
- 229910052710 silicon Inorganic materials 0.000 claims description 47
- 239000010703 silicon Substances 0.000 claims description 47
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 35
- 229920005591 polysilicon Polymers 0.000 claims description 33
- 238000005530 etching Methods 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 17
- 238000000407 epitaxy Methods 0.000 claims description 15
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 15
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 11
- 229910052760 oxygen Inorganic materials 0.000 claims description 11
- 239000001301 oxygen Substances 0.000 claims description 11
- 229910003978 SiClx Inorganic materials 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 7
- 239000000203 mixture Substances 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 239000011229 interlayer Substances 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 3
- 239000007943 implant Substances 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 claims description 3
- 238000006396 nitration reaction Methods 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 claims 1
- 230000005684 electric field Effects 0.000 abstract description 10
- 230000015556 catabolic process Effects 0.000 abstract description 7
- 230000006872 improvement Effects 0.000 description 10
- 238000010586 diagram Methods 0.000 description 8
- 238000002955 isolation Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
Abstract
The invention discloses a kind of method that surface of portion in the trench forms field silica, include the following steps：Form groove；First layer field silica is formed in the interior surface of groove；Form the second silicon nitride layer；Carry out photoresist coating and photoresist is placed only in channel bottom；Dry etch process is carried out to remove the second silicon nitride of the platform area outside groove；Remove photoresist and carrying out wet etching makes second layer field silica only remain in channel bottom；Remove the second silicon nitride layer；Second layer field silica is formed, so that the thickness of the field silica of channel bottom is more than the thickness of the field silica of side after first and two layers of field silica are superimposed.The present invention can form the field silica structure that bottom field silica is thick, lateral field silica is thin in the trench, it need not increase that extra photoetching process, cost are relatively low, when gate trench applied to the groove power MOS device with shield grid can increase the electric field strength of gate trench bottom, improve the breakdown voltage of device.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit manufacture method, is formed more particularly to a kind of portion surface in the trench
The method of field silica.
Background technology
As shown in Figure 1, it is the structure diagram of the existing trench-gate power devices with shield grid；The shape on silicon substrate 2
Into there is silicon epitaxy layer 4, formed with groove in silicon epitaxy layer 4.The source polysilicon 1 for being formed at channel bottom forms shield grid 1, screen
Cover grid 1 and be also referred to as separate gate.Channel bottom silica 3 is located between shield grid 1 and the silicon epitaxy layer 4 of bottom, trenched side-wall oxygen
Change layer 5 to be located between shield grid 1 and the silicon epitaxy layer 4 of groove side surface.At the top of groove formed with polysilicon gate 8, polysilicon
Grid 8 are also referred to as gate pole polysilicon.It is that separate gate isolation from oxygen SiClx 6 is also isolation from oxygen between grid between polysilicon gate 8 and shield grid 1
SiClx.Isolation has gate oxide 7 between polysilicon gate 8 and the silicon epitaxy layer of side 4.On the surface of silicon epitaxy layer 4 formed with body
Implanted layer 11 is tied, body knot implanted layer 11 is generally made of well region.Active area 12, Zhi Hou is formed on the surface of body knot implanted layer 11
Formed with interlayer film 13, contact hole 9 and front metal layer 14 on 4 surface of silicon epitaxy layer；Source electrode is drawn by front metal layer 14
And grid.Draw source region 12 contact hole 9 bottom formed with contact hole injecting layer, that is, well region contact zone 10, contact hole 9 by
Tungsten plug forms.Drain region is formed at the back side of silicon substrate 2, and is drawn and drained by back metal.
In additional backward voltage, separation gate polysilicon 1 is formed the existing trench-gate power devices with shield grid
Electric field first exhausts silicon epitaxy layer 4, electric so as to improve extension body junction breakdown equivalent to 4 doping concentration of silicon epitaxy layer is reduced
Pressure.But such a structure, since groove is deeper, the very strong breakdown of channel bottom electric field easily occurs to be the institute of mark 13 in Fig. 1 from bottom
Show and occur at position.
In existing process, channel bottom silica 3 and trenched side-wall oxide layer 5 on the inside of groove are all to use chemical gaseous phase
The mode of deposition or hot oxygen direct growth is formed, and is the field oxygen for the groove inner surface that existing method is formed as shown in Figure 4 A
The thickness schematic diagram of SiClx, and the process characteristic of itself of chemical vapor deposition or hot oxygen direct growth, determine to be formed
Silica always bottom is than top thin, i.e. thickness b in Fig. 4 A<Thickness a.The thickness b of channel bottom silica 3 is less than groove
The structure of the thickness a of sidewall oxide 5, can make the electric field strength of channel bottom increase, and make trench bottom more deeply plus gash depth
The shortcomings that electric field strength in portion is higher, two make the superposition of the increased effect of electric field strength greatly reduce the breakdown potential of device
Pressure.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of method that surface of portion in the trench forms field silica, energy
The field silica structure that bottom field silica is thick, lateral field silica is thin is formed in the trench, and need not increase extra photoetching
Technique, cost are relatively low, and when gate trench applied to the groove power MOS device with shield grid can increase gate trench bottom
The electric field strength in portion, the breakdown voltage for improving device.
In order to solve the above technical problems, the method that the surface of portion in the trench provided by the invention forms field silica is included such as
Lower step：
Step 1: groove is formed using lithographic etch process on a silicon substrate.
Step 2: form first layer field silica at the same time in the lower surface of the groove and side.
Step 3: forming the second silicon nitride layer, second silicon nitride layer is formed at the table of first layer field silica
Face simultaneously extends to the platform area outside the groove.
Step 4: photoresist coating is carried out, by controlling the thickness of the photoresist photoresist is placed only in institute
State channel bottom and the platform area outside the groove does not have the photoresist to cover.
Step 5: being performed etching using dry etch process to second silicon nitride layer, the dry etch process will
Second silicon nitride of platform area outside the groove removes, positioned at second silicon nitride of the trench bottom surfaces
Layer retains due to being covered by the photoresist, and second silicon nitride layer of the groove side surface also retains.
Step 6: remove the photoresist and wet etching is carried out to first layer field silica, by described second
Under the autoregistration definition of silicon nitride layer and the silicon of the groove side surface, the wet-etching technology is past along the top of the groove
Under first layer field silica is performed etching, in the channel bottom member-retaining portion institute after the completion of the wet-etching technology
State first layer field silica.
Step 7: remove second silicon nitride layer.
Step 8: remaining with the lower surface of the groove of the first layer silica in bottom and side is formed at the same time
Cause the channel bottom after second layer field silica, first layer field silica and the superposition of second layer field silica
The thickness of field silica is more than the thickness of the field silica of side.
A further improvement is that the groove is the gate trench of the groove power MOS device with shield grid.
A further improvement is that the depth of the groove is 2 microns~7 microns.
A further improvement is that described in channel bottom reservation after the completion of wet-etching technology described in step 6
The height of second layer field silica is
A further improvement is that institute is formed at formed with silicon epitaxy layer, the groove in step 1 in the surface of silicon
State in silicon epitaxy layer.
A further improvement is that the groove is formed in step 1 to be included as follows step by step：
Hard mask layers are formed in the surface of silicon.
The photoetching offset plate figure formed by photoetching process defines the forming region of groove.
The hard mask layers of the forming region of the groove are removed using etching technics.
The photoetching offset plate figure is removed, using forming region of the hard mask layers after etching as mask to the groove
Silicon perform etching to form the groove.
A further improvement is that further include following steps when there is the groove power MOS device of shield grid described in being formed：
Step 9: carrying out source polycrystalline silicon deposit and returning to carve, the source polysilicon of Hui Kehou, which is located at, forms the second layer
The bottom of the groove after the silica of field and composition shield grid.
Step 10: carry out third layer silicon oxide deposition, the third layer silica be covered in the shield grid surface and
The second layer field silica side at the top of the shield grid.
Step 11: the wet method for carrying out silica is returned and carved, wet method is returned after quarter by remaining in the oxygen at the top of the source polysilicon
Isolate silica between SiClx composition grid, second layer field silica and the third layer at the top of silica are isolated between the grid
Silica is all removed.
Step 12: the groove side surface isolated between the grid at the top of silica forms gate dielectric layer.
Step 13: carrying out the deposition of polysilicon gate or returning to carve, the polysilicon gate of Hui Kehou is filled in the groove
Top, between the polysilicon gate and the shield grid pass through between the grid isolate silica isolate.
Step 14: progress ion implanting and thermal annealing promote technique to form well region, the polycrystalline in the silicon substrate
Si-gate covers the well region from side and is used to form raceway groove by the well region surface of polysilicon gate side covering.
Step 15: the source for carrying out heavy doping, which is infused in the well region surface, forms source region.
Step 16: interlayer film, contact hole and front metal layer are formed in silicon substrate front, to the front metal
Layer carries out chemical wet etching formation source electrode and grid, the source electrode are connect by contact hole and the source region and the source polysilicon
Touch, the grid is contacted by contact hole and the polysilicon gate.
Step 12: the silicon substrate back side be thinned and forms the drain region of heavy doping, at the back side in the drain region
Metal layer on back is formed as drain electrode.
A further improvement is that gate dielectric layer described in step 12 is gate oxide.
A further improvement is that contact hole described in step 10 six opening formed after, it is metal filled before, be additionally included in and
The bottom for the contact hole that the source region is in contact carries out the step of heavily-doped implant forms well region contact zone.
A further improvement is that the hard mask layers are made of oxide layer or add nitration case to form by oxide layer.
The field oxide of grooved inner surface of the present invention is formed by two superimposed, shape again after silica is formed in first layer field
Into one layer of silicon nitride i.e. the second silicon nitride layer, then coating photoresist, deeper using the depth of groove, and works as during coating photoresist
Photoresist can flow to the relatively low channel bottom in position when photoresist is relatively thin, so as to form only covering groove bottom automatically
The photoetching offset plate figure structure in portion, so when subsequently carrying out dry etching to the second silicon nitride layer, the second of trench bottom surfaces
Silicon nitride layer can be photo-etched glue protection and be not etched, only by the second silicon nitride of surface of silicon, that is, platform area outside groove
Layer removes, and such second silicon nitride is placed only in side and the lower surface of the first layer field silica in groove, in first layer
Second silicon nitride layer of field silica top surface is all removed, thus self aligned to define follow-up progress first layer field oxygen
The wet etching region of SiClx so that carried out from the top of groove to bottom when carrying out wet etching to first layer field silica
Etching, is so easy to define the height of the first layer field silica retained in channel bottom by wet-etching technology；It
After remove the second silicon nitride layer and form second layer field silica, after first layer field silica and the superposition of second layer field silica
The thickness of field silica with regard to that can obtain channel bottom is more than the structure of the thickness of the field silica of side.Understand, energy of the present invention
The field silica structure that bottom field silica is thick, lateral field silica is thin is formed in the trench, and need not be increased in whole technique
Add extra photoetching process, cost relatively low, wherein photoresist mask graph when being etched to the second silicon nitride layer is to utilize photoresist
Coating process can be initially formed automatically defined in the characteristics of channel bottom and be to the mask of first layer field oxide etch using pair
The figure autoregistration definition formed after second silicon nitride layer etching, need not all increase photoetching process, so cost is relatively low.
And when the groove power for being applied to the field silica structure on the trench wall surface of the present invention there is shield grid
The electric field strength of gate trench bottom can be increased during the gate trench of MOS device, improve the breakdown voltage of device, can also be made
The field silicon oxide thickness of grid groove bottom is thickening, and gate trench bottom is reduced by the adding for thickness of the field silica at this
The electric field strength in portion, can offset electric field strength increase caused by the depth relatively depth of gate trench, so as to provide device
Breakdown voltage.
Brief description of the drawings
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments：
Fig. 1 is the existing trench-gate power devices structure diagram with shield grid；
Fig. 2 is present invention method flow chart；
Fig. 3 A- Fig. 3 O are the device architecture schematic diagrames in each step of present invention method；
Fig. 4 A are the thickness schematic diagrames of the field silica for the groove inner surface that existing method is formed；
Fig. 4 B are the thickness schematic diagrames of the field silica for the groove inner surface that present invention method is formed；
Embodiment
It is the device architecture schematic diagram in each step of present invention method as shown in Fig. 3 A to Fig. 3 O；It is of the invention real
The method that example is applied in 203 interior surface of groove formation field silica includes the following steps：
Step 1: groove 203 is formed on silicon substrate 101 using lithographic etch process.
Forming the groove 203 is included as follows step by step：
As shown in Figure 3A, there is provided described on 101 surface of silicon substrate formed with silicon epitaxy layer 102 with silicon substrate 101
Groove 203 is formed in the silicon epitaxy layer 102.
As shown in Figure 3B, hard mask layers 201 are formed on 101 surface of silicon substrate.The hard mask layers 201 are by oxygen
Change layer composition or add nitration case to form by oxide layer.
As shown in Figure 3B, the photoetching offset plate figure 202 formed by photoetching process defines the forming region of groove 203.
As shown in Figure 3B, the hard mask layers 201 of the forming region of the groove 203 are removed using etching technics.
As shown in Figure 3 C, remove the photoetching offset plate figure, with the hard mask layers 201 after etching for mask to described
The silicon of the forming region of groove 203 performs etching to form the groove 203.
The depth of the groove 203 is 2 microns~7 microns.
Step 2: as shown in Figure 3D, first layer field silica is formed at the same time in the lower surface of the groove 203 and side
103。
Step 3: as shown in FIGURE 3 E, the second silicon nitride layer 204 is formed, second silicon nitride layer 204 is formed at described the
The surface of one layer of field silica 103 simultaneously extends to the platform area outside the groove 203.
Step 4: as illustrated in Figure 3 F, carry out photoresist 205 and be coated with, it is described by controlling the thickness of the photoresist 205 to make
Photoresist is placed only in 203 bottom of groove and the platform area outside the groove 203 does not have the photoresist 205 to cover
Lid.Namely the present invention forms photoresist 205 and is placed only in the graphic structure of 203 bottom of groove and need not use photoetching work
Skill, the feature of relatively low 203 bottom of groove in position can be coated on using photoresist 205 to form photoetching first in coating process
The graphic structure of glue 205.
Step 5: as shown in Figure 3 G, second silicon nitride layer 204 is performed etching using dry etch process, it is described
Dry etch process removes second silicon nitride of the platform area outside the groove 203, positioned at 203 bottom of groove
Second silicon nitride layer 204 on surface retains due to being covered by the photoresist, and described the second of 203 side of groove
Silicon nitride layer 204 also retains.Since dry etch process is anisotropic etching, described positioned at 203 side of groove
Nitride silicon layer 204 will not be etched into so as to remain.
Step 6: as shown in figure 3h, remove the photoresist.
As shown in fig. 31, wet etching is carried out to first layer field silica 103, by second silicon nitride layer
204 and 203 side of the groove silicon autoregistration definition under, top of the wet-etching technology along the groove 203
Down first layer field silica 103 is performed etching, is protected after the completion of the wet-etching technology in 203 bottom of groove
Stay the part first layer field silica 103.Height h in Fig. 3 I is by the first layer field silica that retains after etching
103 height.Preferably, height h is
Step 7: as shown in figure 3j, remove second silicon nitride layer 204.
Step 8: as shown in Fig. 3 K, the lower surface of the groove 203 of the first layer silica is remained with bottom
Form second layer field silica 104, first layer field silica 103 and second layer field silica 104 at the same time with side
The thickness of the field silica of after superposition so that 203 bottom of groove is more than the thickness of the field silica of side.As shown in Figure 4 B,
Be present invention method formed groove inner surface field silica thickness schematic diagram, thickness c>Thickness d, Ye Jiben
What inventive embodiments method was formed.The thickness c of the field silica of the bottom of groove 203 is more than the thickness d of the field silica of side
Structure；The thickness relationship contrast formed with the existing method shown in Fig. 4 A.
In the embodiment of the present invention, the groove 203 is the grid of 203 gate power MOS device of groove with shield grid 105
Groove 203, further includes following steps：
Step 9: as shown in figure 3l, carry out source polysilicon 105 and deposit and return quarter, the source polysilicon 105 of Hui Kehou
The bottom of the groove 203 after second layer field silica 104 is formed and composition shield grid 105.
Step 10: as shown in fig.3m, carry out third layer silica 106 and deposit, the third layer silica 106 is covered in institute
State 104 side of second layer field silica at 105 surface of shield grid and the top of the shield grid 105.
Step 11: as shown in fig.3m, the wet method for carrying out silica is returned quarter, and wet method is returned after quarter by remaining in the source polycrystalline
Isolate silica 106 between the silica composition grid at the top of silicon 105, the second layer at the top of silica 106 is isolated between the grid
Field silica 104 and the third layer silica 106 are all removed.Second layer field silica 104 can also be first removed, it
Carrying out the deposition of third layer silica 106 and returning to carve to isolate silica 106 between grid so as to be formed afterwards.
Step 12: as shown in Fig. 3 N, 203 side of the groove that the top of silica 106 is isolated between the grid is formed
Gate dielectric layer 107.The gate dielectric layer 107 is gate oxide.
Step 13: as shown in Fig. 3 N, carry out the deposition of polysilicon gate 108 or return to carve, the polysilicon gate of Hui Kehou
108 are filled in the top of the groove 203, by isolating between the grid between the polysilicon gate 108 and the shield grid 105
Silica 106 is isolated.
Step 14: as shown in Fig. 3 O, carry out ion implanting and thermal annealing promotes technique to be formed in the silicon substrate 101
Well region 109, the polysilicon gate 108 cover the well region 109 and described in the covering of 108 side of polysilicon gate from side
109 surface of well region is used to form raceway groove.
Step 15: as shown in Fig. 3 O, the source for carrying out heavy doping is infused in 109 surface of the well region formation source region 110.
Step 16: as shown in Fig. 3 O, interlayer film 112, contact hole 113 and front are formed in the front of silicon substrate 101
Metal layer 114, carries out the front metal layer 114 chemical wet etching formation source electrode and grid, the source electrode pass through contact hole 113
Contacted with the source region 110 and the source polysilicon 105, the grid is connect by contact hole 113 and the polysilicon gate 108
Touch.
The opening of the contact hole 113 formed after, it is metal filled before, be additionally included in and connect with what the source region 110 was in contact
The bottom of contact hole 113 carries out the step of heavily-doped implant forms well region contact zone 111.
Step 12: as shown in Fig. 3 O, 101 back side of silicon substrate be thinned and forms the drain region of heavy doping,
The back side in the drain region forms metal layer on back as drain electrode.
The present invention is described in detail above by specific embodiment, but these not form the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these also should
It is considered as protection scope of the present invention.
Claims (10)
1. a kind of method that surface of portion in the trench forms field silica, it is characterised in that include the following steps：
Step 1: groove is formed using lithographic etch process on a silicon substrate；
Step 2: form first layer field silica at the same time in the lower surface of the groove and side；
Step 3: forming the second silicon nitride layer, second silicon nitride layer is formed at the surface of first layer field silica simultaneously
Extend to the platform area outside the groove；
Step 4: photoresist coating is carried out, by controlling the thickness of the photoresist photoresist is placed only in the ditch
Trench bottom and the platform area outside the groove do not have the photoresist to cover；
Step 5: being performed etching using dry etch process to second silicon nitride layer, the dry etch process is by described in
Second silicon nitride of platform area outside groove removes, positioned at the trench bottom surfaces second silicon nitride layer by
Retain in being covered by the photoresist, second silicon nitride layer of the groove side surface also retains；
Step 6: removing the photoresist and carrying out wet etching to first layer field silica, nitrogenized by described second
Under the autoregistration definition of silicon layer and the silicon of the groove side surface, the wet-etching technology is down right along the top of the groove
First layer field silica performs etching, described in the channel bottom member-retaining portion after the completion of the wet-etching technology
One layer of field silica；
Step 7: remove second silicon nitride layer；
Step 8: lower surface and side while the formation second of the groove of the first layer silica are remained with bottom
So that the field oxygen of the channel bottom after layer field silica, first layer field silica and the superposition of second layer field silica
The thickness of SiClx is more than the thickness of the field silica of side.
2. the method that portion surface forms field silica in the trench as claimed in claim 1, it is characterised in that：The groove is
The gate trench of groove power MOS device with shield grid.
3. the method that portion surface forms field silica in the trench as claimed in claim 1 or 2, it is characterised in that：The ditch
The depth of groove is 2 microns~7 microns.
4. the method that portion surface forms field silica in the trench as claimed in claim 1 or 2, it is characterised in that：Step 6
Described in the height of second layer field silica that retains in the channel bottom after the completion of wet-etching technology be
5. the method that portion surface forms field silica in the trench as claimed in claim 1 or 2, it is characterised in that：Step 1
In be formed in the surface of silicon formed with silicon epitaxy layer, the groove in the silicon epitaxy layer.
6. the method that portion surface forms field silica in the trench as claimed in claim 1 or 2, it is characterised in that：Step 1
The middle formation groove is included as follows step by step：
Hard mask layers are formed in the surface of silicon；
The photoetching offset plate figure formed by photoetching process defines the forming region of groove；
The hard mask layers of the forming region of the groove are removed using etching technics；
The photoetching offset plate figure is removed, using silicon of the hard mask layers after etching as mask to the forming region of the groove
Perform etching to form the groove.
7. the method that portion surface forms field silica in the trench as claimed in claim 2, it is characterised in that：Form the tool
Following steps are further included when having the groove power MOS device of shield grid：
Step 9: carrying out source polycrystalline silicon deposit and returning to carve, the source polysilicon of Hui Kehou, which is located at, forms second layer field oxygen
The bottom of the groove after SiClx and composition shield grid；
Step 10: carrying out third layer silicon oxide deposition, the third layer silica is covered in the shield grid surface and described
The second layer field silica side at the top of shield grid；
Step 11: the wet method for carrying out silica is returned and carved, wet method is returned after quarter by remaining in the silica at the top of the source polysilicon
Isolate silica between composition grid, the second layer field silica at the top of silica and third layer oxidation are isolated between the grid
Silicon is all removed；
Step 12: the groove side surface isolated between the grid at the top of silica forms gate dielectric layer；
Step 13: carrying out the deposition of polysilicon gate or returning to carve, the polysilicon gate of Hui Kehou is filled in the top of the groove
Portion, is isolated between the polysilicon gate and the shield grid by isolating silica between the grid；
Step 14: progress ion implanting and thermal annealing promote technique to form well region, the polysilicon gate in the silicon substrate
The well region is covered from side and is used to form raceway groove by the well region surface of polysilicon gate side covering；
Step 15: the source for carrying out heavy doping, which is infused in the well region surface, forms source region；
Step 16: form interlayer film, contact hole and front metal layer in silicon substrate front, to the front metal layer into
Row chemical wet etching forms source electrode and grid, the source electrode pass through contact hole and the source region and the source polysilicon contact, institute
Grid is stated to contact by contact hole and the polysilicon gate；
Step 17: to the silicon substrate back side be thinned and forming the drain region of heavy doping, formed at the back side in the drain region
Metal layer on back is as drain electrode.
8. the method that portion surface forms field silica in the trench as claimed in claim 7, it is characterised in that：In step 12
The gate dielectric layer is gate oxide.
9. the method that portion surface forms field silica in the trench as claimed in claim 7, it is characterised in that：In step 10 six
The opening of the contact hole formed after, it is metal filled before, the bottom for being additionally included in the contact hole being in contact with the source region carries out
Heavily-doped implant forms the step of well region contact zone.
10. the method that portion surface forms field silica in the trench as claimed in claim 6, it is characterised in that：The hard
Mask layer is made of oxide layer or adds nitration case to form by oxide layer.
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| CN105957811A (en) * | 2016-04-27 | 2016-09-21 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing trench gate power devices with shielded gate |
| CN105895516B (en) * | 2016-04-29 | 2018-08-31 | 深圳尚阳通科技有限公司 | The manufacturing method of trench gate mosfet with shield grid |
| CN105914234A (en) * | 2016-06-28 | 2016-08-31 | 上海华虹宏力半导体制造有限公司 | Separating gate power MOS transistor structure and manufacturing method therefor |
| CN111370487B (en) * | 2018-12-26 | 2023-01-06 | 深圳尚阳通科技有限公司 | Trench gate MOSFET device and manufacturing method thereof |
| CN110034182A (en) * | 2019-03-13 | 2019-07-19 | 上海华虹宏力半导体制造有限公司 | The manufacturing method of trench-gate device with shield grid |
| CN111128706B (en) * | 2019-12-27 | 2022-06-03 | 华虹半导体(无锡)有限公司 | Manufacturing method of field oxide with gradually-changed thickness in groove and manufacturing method of SGT (super-stable Gate Bipolar transistor) device |
| CN111489961A (en) * | 2020-04-17 | 2020-08-04 | 重庆伟特森电子科技有限公司 | Preparation method of SiC-MOSFET gate with gate oxide at corner of trench and high field strength bearing capacity |
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| CN1360735A (en) * | 1999-05-25 | 2002-07-24 | 理查德·K·威廉斯 | Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating same |
| CN1610089A (en) * | 2003-10-21 | 2005-04-27 | 上海宏力半导体制造有限公司 | Method for producing shallow ridge isolation structure to improve smiling effect |
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| CN1360735A (en) * | 1999-05-25 | 2002-07-24 | 理查德·K·威廉斯 | Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating same |
| CN1610089A (en) * | 2003-10-21 | 2005-04-27 | 上海宏力半导体制造有限公司 | Method for producing shallow ridge isolation structure to improve smiling effect |
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