CN107507765A - Shield grid groove power device and its manufacture method - Google Patents
Shield grid groove power device and its manufacture method Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 52
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 252
- 229920005591 polysilicon Polymers 0.000 claims abstract description 241
- 230000003071 parasitic effect Effects 0.000 claims abstract description 20
- 239000010410 layer Substances 0.000 claims description 237
- 239000000758 substrate Substances 0.000 claims description 74
- 239000004065 semiconductor Substances 0.000 claims description 62
- 239000002184 metal Substances 0.000 claims description 26
- 229910052751 metal Inorganic materials 0.000 claims description 26
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 22
- 238000005516 engineering process Methods 0.000 claims description 21
- 229910052710 silicon Inorganic materials 0.000 claims description 21
- 239000010703 silicon Substances 0.000 claims description 21
- 230000003647 oxidation Effects 0.000 claims description 19
- 238000007254 oxidation reaction Methods 0.000 claims description 19
- 238000001259 photo etching Methods 0.000 claims description 12
- 239000013078 crystal Substances 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 239000011229 interlayer Substances 0.000 claims description 7
- 239000000126 substance Substances 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- 239000000203 mixture Substances 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 3
- 239000007943 implant Substances 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims 1
- 238000005530 etching Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000010276 construction Methods 0.000 description 5
- 238000002955 isolation Methods 0.000 description 4
- 230000001413 cellular effect Effects 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 230000005611 electricity Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical group [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000006396 nitration reaction Methods 0.000 description 1
- 230000024241 parasitism Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
Abstract
The invention discloses a kind of shield grid groove power device, the grid structure in device cell area includes：First deep trench and the bottom dielectric layer on surface on its inside；Bottom dielectric layer surrounds 2 times of interstitial area of the width less than or equal to the thickness of gate oxide in the first deep trench middle section；The first polysilicon layer is filled in interstitial area；The bottom dielectric layer of the two sides of first deep trench top area is removed to form top channel, formed with gate oxide and polysilicon gate in top channel；The source polysilicon that the first polysilicon layer between top channel is fully oxidized while gate oxide is formed and makes to be made up of unoxidized first polysilicon layer by aoxidizing the second oxide layer formed is located at polysilicon gate bottom, can reduce the parasitic capacitance between source polysilicon and polysilicon gate.The invention also discloses a kind of manufacture method of shield grid groove power device.The present invention can reduce the gate-source parasitic capacitance of device, improve the input capacitance of device and improve the performance of device.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit manufacture method, more particularly to a kind of shield grid (Shield Gate
Trench, SGT) groove power device；The invention further relates to a kind of manufacture method of shield grid groove power device.
Background technology
As shown in Figure 1A to Fig. 1 N, be existing shield grid groove power device each step of manufacture method in device architecture
Schematic diagram；This method is to form the first deep trench separation side grid structure with shield grid, bag using bottom-to-top method
Include following steps：
Step 1: as shown in Figure 1A, there is provided semi-conductive substrate such as silicon substrate 101；In the surface shape of Semiconductor substrate 101
Into hard mask layers 102, hard mask layers 102 can use oxide layer, or add nitration case using oxide layer.
As shown in Figure 1B, hard mask layers 102 are performed etching using photoetching process afterwards and define grid forming region,
Again Semiconductor substrate 101 is performed etching to form the first deep trench 103 for mask with hard mask layers 102 afterwards.
Step 2: as shown in Figure 1 C, oxide layer 104 is formed in the side of the first deep trench 103 and lower surface.
Step 3: as shown in figure iD, source polysilicon 105, the source polysilicon are filled in first deep trench 103
105 be source polysilicon, and source polysilicon 105 is typically connected with source electrode, for forming shield grid.
Step 4: as referring to figure 1E, source polysilicon 105 carve, this time is carved the source outside the first deep trench 103
Pole polysilicon 105 all removes, and the top of source polysilicon 105 in the first deep trench 103 is equal with Semiconductor substrate 101.
As shown in fig. 1F, the oxide layer 104 of the top area of the first deep trench 103 is removed.
Step 5: as shown in Figure 1 G, carry out thermal oxidation technology and form gate oxide 106a and inter polysilicon isolation Jie simultaneously
Matter layer 106b.
As shown in fig. 1H, polysilicon gate 107 is formed, polysilicon gate 107 is the first deep trench grid.
As shown in Figure 1 I, polysilicon gate 107 carve, Hui Kehou polysilicon gate 107 is only located at the first deep trench
The both sides of source polysilicon 105 at 103 tops；It follows that the polysilicon gate between the two sides of same first deep trench 103
107 be in isolating construction, for the first deep trench grid phase region formed with the polysilicon gate being filled up completely with the top of the first deep trench
Not, this first deep trench grid with separate structure for being formed at the first zanjon groove sidewall are referred to as the separation of the first deep trench
Side grid.
Step 6: as shown in Figure 1 I, form well region 108, source region 109.
As shown in figure iJ, interlayer film 110 is formed, contact hole, marks the contact hole corresponding to 111a to correspond to and is not filled by gold
Structure before category.Preferably, after etching forms contact hole 111a, it is also necessary in the contact corresponding to the top of source region 109
Well region contact zone is formed on hole 111a bottom.
As shown in figure iK, metal is filled in contact hole 111a afterwards, the contact hole mark 111 after metal is filled and marks
Show.
As can be seen in 1L, front metal layer 112 is formed.
As depicted in figure iM, front metal layer 112 is patterned using lithographic etch process and forms source electrode and grid respectively
Pole, wherein source electrode are contacted by the source region 109 of contact hole and bottom, well region contact zone 109 and source polysilicon 105, grid
Contacted by contact hole and polysilicon gate 107.
As shown in Fig. 1 N, formed form drain region and metal layer on back 113 at the back side of Semiconductor substrate 101 afterwards, by carrying on the back
The composition drain electrode of face metal level 113.
In existing method, a side of polysilicon gate 107 is isolated by gate oxide 106a and well region 108, well region 108
By the side of polysilicon gate 107 covering surface be used for form raceway groove.Shown in Fig. 1 N, above-mentioned existing method is formed more
Crystal silicon grid 107 are only located at the side wall at the top of the first deep trench, and this vertical devices with sidewall polycrystalline silicon structure can increase
Operating current；Source polysilicon 105 is filled in whole first deep trench simultaneously, and source polysilicon 105 can form good screen
Cover, there is less bottom capacitor, so as to reduce the input capacitance of source and drain or grid leak, improve frequency characteristic.
But the existing device architecture as shown in Fig. 1 N, the device have larger gate-source parasitic capacitance (Cgs), Cgs master
To be made up of two parts, i.e. Cgs2, Cgs1 and Cgs2 corresponding to Cgs1 corresponding to dotted line circle 114 and dotted line circle 115 be simultaneously in Fig. 1 N
Connection forms Cgs.Wherein, Cgs1 is the polysilicon gate 107 and the well region 108 by the gate oxide 106a and connection source electrode
The gate-source parasitic capacitance formed with source region 109 is Part I gate-source parasitic capacitance；Cgs2 is the polysilicon gate 107 and passed through
The gate-source parasitic capacitance that the source polysilicon 105 of the inter polysilicon isolation dielectric layer 106b and connection source electrode are formed is second
Divide gate-source parasitic capacitance；Shown in Fig. 1 N, the inter polysilicon isolation dielectric layer 106b and gate oxide 106a is same
When formed, former capital has relatively thin thickness；Meanwhile the overlapping region of the polysilicon gate 107 and the source polysilicon 105 compared with
Greatly, the overlapping region and the polysilicon gate 107 are suitable with the overlapping region of source region 109 with well region 108, substantially described polycrystalline
The first side of Si-gate 107 all with the second side of overlapping, the described polysilicon gate 107 of well region 108 and source region 109 all with it is described
Source polysilicon 105 overlaps；Relatively thin inter polysilicon isolation dielectric layer 106b and gate oxide 106a thickness
And larger overlapping area so that Cgs1 and Cgs2 has larger value, and both Cgs in parallel value is Cgs1 and Cgs2
Sum, therefore Cgs value is also larger, therefore how to reduce the problem of Cgs is the application concern.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of shield grid groove power device, can reduce the grid source of device
Parasitic capacitance, from the input capacitance for improving device and improve the performance of device.Therefore, the present invention also provides a kind of shielding gate groove
The manufacture method of power device.
In order to solve the above technical problems, the grid knot in the device cell area of shield grid groove power device provided by the invention
Structure includes：
The first deep trench being formed in Semiconductor substrate, first deep trench lower surface and side formed with
Bottom dielectric layer.
First deep trench is not filled up completely with and in the middle section of first deep trench by the bottom dielectric layer
Formed with interstitial area, the width of the interstitial area is less than or equal to 2 times of the thickness of gate oxide；Is filled in the interstitial area
One polysilicon layer.
The bottom dielectric layer positioned at the side of the first deep trench top area is removed and in the described first depth
The both sides of first polysilicon layer of the top area of groove are formed with top channel.
Gate oxide be formed at the top channel on the side of the Semiconductor substrate side, the top ditch
First polysilicon layer between groove is fully oxidized to form the second oxide layer while the gate oxide is formed.
Polysilicon is filled with side is formed with the top channel of the gate oxide and second oxide layer
Grid.
Source polysilicon is formed by first polysilicon layer of the second oxide layer bottom；Second oxide layer makes
The source polysilicon is located at the bottom of the polysilicon gate in the vertical, so as to reduce the source polysilicon and the polycrystalline
Parasitic capacitance between Si-gate.
Further improve is that the Semiconductor substrate is adulterated for the first conduction type, in the semiconductor substrate surface
Well region formed with the second conduction type, the polysilicon gate pass through the well region, the institute covered by the polysilicon gate side
Well region surface is stated to be used to form raceway groove.
In source region of the well region surface formed with the first conduction type heavy doping.
Be also formed with interlayer film, contact hole and front metal layer in the front of the Semiconductor substrate, source electrode and grid by
Chemical wet etching is carried out to the front metal layer to be formed, the source electrode is led to by contact hole and the source contact, the grid
Cross contact hole and polysilicon gate contact.
Drain region is formed from the first conduction type heavily doped region composition at the Semiconductor substrate back side after being thinned, in institute
The back side for stating drain region forms metal layer on back as drain electrode.
Further improve is source polysilicon draw-out area to be externally formed with the device cell area, in the source
Formed and be connected simultaneously with first deep trench formed with the second deep trench, second deep trench in the polysilicon draw-out area of pole
The width of logical and described second deep trench is more than the width of first deep trench, in the side and bottom of second deep trench
Surface is formed with the bottom dielectric layer with same process condition in first deep trench, in the institute of second deep trench
State and the first polysilicon layer is also filled with the interstitial area between bottom dielectric layer, the first polysilicon layer in second deep trench
Width be more than first deep trench in the first polysilicon layer width；Bottom dielectric layer in second deep trench is also
Extend to the both sides outer surface of second deep trench, bottom dielectric layer and the first polysilicon layer in second deep trench
Top it is concordant；The first polysilicon layer in second deep trench is as source polysilicon simultaneously and in first deep trench
Source polysilicon contacts with each other connection, formed with contact hole and is connected at the top of the source polysilicon of second deep trench
The source electrode.
Further improve is that the bottom dielectric layer is oxide layer.
Further improve is, heavily doped formed with the second conduction type in the bottom for the contact hole being in contact with the source region
Miscellaneous well region contact zone.
Further improve is that shield grid groove power device is N-type device, and the first conduction type is N-type, and second is conductive
Type is p-type, and the Semiconductor substrate is n-type doping；Or shield grid groove power device is P-type device, the first conductive-type
Type is p-type, and the second conduction type is N-type, and the Semiconductor substrate is adulterated for p-type.
Further improve is that the Semiconductor substrate is silicon substrate.
In order to solve the above technical problems, the device cell of the manufacture method of shield grid groove power device provided by the invention
The grid structure in area is formed using following steps：
Step 1: providing semi-conductive substrate, first is formed deeply in the Semiconductor substrate using lithographic etch process
Groove.
Step 2: form bottom dielectric layer in the lower surface of first deep trench and side；The bottom dielectric layer
Not by first deep trench be filled up completely with and first deep trench middle section formed with interstitial area, the interstitial area
Width be less than or equal to 2 times of the thickness of gate oxide being subsequently formed.
The interstitial area is filled up completely with Step 3: carrying out polycrystalline silicon deposit and forming the first polysilicon layer.
Step 4: using first polysilicon layer as mask to the bottom dielectric layer carry out autoregistration return carve, it is described from
The bottom dielectric layer for the side being aligned back after carving positioned at the first deep trench top area is removed and described first
The both sides of first polysilicon layer of the top area of deep trench form top channel.
Step 5: carrying out thermal oxide, served as a contrast by the thermal oxidation technology in the top channel positioned at the semiconductor
Gate oxide is formed on the side of bottom side, the thermal oxidation technology is simultaneously by first polycrystalline between the top channel
Silicon layer complete oxidation simultaneously forms the second oxide layer；It is more that source electrode is formed by first polysilicon layer of the second oxide layer bottom
Crystal silicon.
It is deposited on filling polysilicon in the top channel Step 6: carrying out polysilicon and forms polysilicon gate；Described
Dioxide layer makes bottom of the source polysilicon in the vertical positioned at the polysilicon gate, so as to reduce the source polysilicon
Parasitic capacitance between the polysilicon gate.
Further improve is that the Semiconductor substrate is adulterated for the first conduction type, after grid structure is formed, is also wrapped
Include following steps：
Step 7: carry out the well region that ion implanting forms the second conduction type in the Semiconductor substrate；Carry out first
The source of conduction type heavy doping is infused in the well region surface and forms source region；Thermal annealing is carried out to the well region and the source region to push away
Enter technique；It is used to form raceway groove by the well region surface of polysilicon gate side covering.
Step 8: interlayer film, contact hole and front metal layer are formed in Semiconductor substrate front, to the front gold
Category layer carries out chemical wet etching formation source electrode and grid, the source electrode are passed through by contact hole and the source contact, the grid
Contact hole and polysilicon gate contact.
Step 9: the Semiconductor substrate back side be thinned and forms the drain region of the first conduction type heavy doping,
The back side in the drain region forms metal layer on back as drain electrode.
Further improve is source polysilicon draw-out area to be externally formed with the device cell area, in the source
Formed with the second deep trench, second deep trench and first deep trench while in step 1 in the polysilicon draw-out area of pole
Formed and be connected and the width of second deep trench be more than first deep trench width.
In the side of second deep trench and lower surface formed with identical with first deep trench in step 2
The bottom dielectric layer of process conditions；The bottom dielectric layer also extends into first deep trench and second deep trench
Outer surface.
It is also filled with interstitial area in step 3 between the bottom dielectric layer of second deep trench more than first
Crystal silicon layer, the width of the first polysilicon layer in second deep trench are more than the first polysilicon layer in first deep trench
Width；First polysilicon layer also extends into first deep trench and described after the polycrystalline silicon deposit of step 3 is completed
The outer surface of second deep trench.
Also include polysilicon after the polycrystalline silicon deposit of step 3 and return carving technology, the polysilicon returns carving technology by the device
First polysilicon layer in cellular zone returns that to be carved into surface equal with the surface of first deep trench and by the source electrode
First polysilicon layer in polysilicon draw-out area returns the bottom dielectric layer being carved into outside surface and second deep trench
Surface it is equal；The first polysilicon layer in second deep trench is as source polysilicon simultaneously and in first deep trench
Source polysilicon contacts with each other connection.
The autoregistration of step 4 is returned after the completion of carving technology, outside first deep trench in the device cell area
The bottom dielectric layer is all removed；The bottom dielectric layer in the source polysilicon draw-out area can be to second zanjon
Groove is extended a distance into outside, and elongated area is defined by photoetching process, and the bottom dielectric layer outside elongated area is all removed.
Contact hole is formed in step 8 at the top of the source polysilicon of second deep trench simultaneously and passes through the contact
Hole is connected to the source electrode.
Further improve be, the opening of contact hole described in step 8 formed after, it is metal filled before, be additionally included in and institute
The bottom for stating the contact hole that source region is in contact carries out the step of the second conduction type heavily-doped implant forms well region contact zone.
Further improve is that the bottom dielectric layer is oxide layer.
Further improve is that shield grid groove power device is N-type device, and the first conduction type is N-type, and second is conductive
Type is p-type, and the Semiconductor substrate is n-type doping；Or shield grid groove power device is P-type device, the first conductive-type
Type is p-type, and the second conduction type is N-type, and the Semiconductor substrate is adulterated for p-type.
Further improve be, in the semiconductor substrate surface formed with the first conductive type epitaxial layer, described first
Deep trench and second deep trench are formed in first conductive type epitaxial layer.
Further improve is that the Semiconductor substrate is silicon substrate.
Shield grid groove power device of the present invention is specifically designed to grid structure, and polysilicon gate uses separation side grid knot
The deep trench of structure, i.e. grid structure be the first deep trench include the side of two tops for being formed at the first deep trench and
The polysilicon gate being mutually isolated out, in of the invention, the lower surface of the first deep trench and side lead to formed with bottom dielectric layer
Cross the thickness of bottom dielectric layer has been carried out it is special set so that bottom dielectric layer formed after the first deep trench middle section
Formed with width be less than or equal to gate oxide thickness 2 times of interstitial area, so interstitial area fill the first polysilicon layer it
Afterwards, Self-aligned etching can be carried out in the first deep trench top area to bottom dielectric layer using the first polysilicon layer as self-aligned mask
The first polysilicon layer both sides formed bottom dielectric layer be removed after top channel, shape of the top channel as polysilicon gate
Into region；The first polysilicon layer between top channel complete oxidation can be the oxidation of oxide layer second when forming gate oxide
Layer, the first polysilicon layer between top channel is completely oxidized into the second oxide layer needs to combine above to the width of interstitial area
Setting, i.e., by the width of interstitial area be set smaller than equal to gate oxide thickness 2 times of interstitial area；So, the second oxygen
First polysilicon layer of change layer bottom is just automatically composed the source polysilicon in the first deep trench, so so that source polysilicon
It is located at the bottom of polysilicon gate in the vertical, so as to reduce the parasitic capacitance between source polysilicon and polysilicon gate, this is posted
Cgs2 corresponding to raw electric capacity and Fig. 1 N of the prior art dotted line circle 115 is corresponding, so the present invention can reduce Cgs2.By
Upper to understand, the present invention can reduce the gate-source parasitic capacitance of device, from the input capacitance for improving device and improve the performance of device.
Further, since the present invention the second oxide layer and need not be formed using extra technique, be in gate oxide
Thermal oxide simultaneously is carried out in thermal oxidation technology to the first polysilicon layer at the top of the first deep trench to be formed, this thermal oxidation technology is not
It is only capable of source polysilicon is self aligned positioned at the bottom of polysilicon gate, and has due to extra technique need not be increased
Relatively low process costs.
Brief description of the drawings
The present invention is further detailed explanation with reference to the accompanying drawings and detailed description：
Figure 1A-Fig. 1 N are the device architecture schematic diagrames in each step of manufacture method of existing shield grid groove power device；
Fig. 2 is shield grid trench power device structure schematic diagram of the embodiment of the present invention；
Fig. 3 A- Fig. 3 I are the device architecture schematic diagrames in each step of present invention method.
Embodiment
As shown in Fig. 2 it is shield grid trench power device structure schematic diagram of the embodiment of the present invention；The embodiment of the present invention shields
The grid structure in the device cell area of gate groove power device includes：
The first deep trench 201 being formed in Semiconductor substrate 1, lower surface and side in first deep trench 201
Face is formed with bottom dielectric layer 2.Generally, on the surface of Semiconductor substrate 1 formed with the first conductive type epitaxial layer, described
One deep trench 201 and the second deep trench 201a described below are formed in first conductive type epitaxial layer.Preferably,
The Semiconductor substrate 1 is silicon substrate.First deep trench 201 is only illustrated in Fig. 2, actually shields gate groove
Power device can be formed in parallel by multiple device cells, and a device cell will be formed at first deep trench 201,
Then need to form multiple first deep trench 201 during with multiple device cells, because device unit construction is repetition
Structure, therefore use first deep trench 201 to illustrate, other devices cellular construction is all identical.And described second is deep
Groove 201a then uses one, at this moment first zanjon of the second deep trench 201a requirements with all device cells
Groove 201 is connected.
First deep trench 201 is not filled up completely with and in first deep trench 201 by the bottom dielectric layer 2
Centre region is less than or equal to gate oxide 4 formed with interstitial area 202 (mark 202 is see accompanying drawing 3B), the width of the interstitial area 202
2 times of thickness；The first polysilicon layer 3 is filled in the interstitial area 202.Preferably, the bottom dielectric layer 2 is oxidation
Layer.
The bottom dielectric layer 2 positioned at the side of the top area of the first deep trench 201 is removed and described
Formed with top channel 203, (mark 203 is see attached for the both sides of first polysilicon layer 3 of the top area of one deep trench 201
Fig. 3 E).
Gate oxide 4 be formed at the top channel 203 on the side of the side of Semiconductor substrate 1, it is described
First polysilicon layer 3 between top channel 203 is fully oxidized to form second while gate oxide 4 are formed
Oxide layer 5.
Filled with more in side is formed with the top channel 203 of the gate oxide 4 and second oxide layer 5
Crystal silicon grid 6.
Source polysilicon 3 is formed by first polysilicon layer 3 of the bottom of the second oxide layer 5；Second oxidation
Layer 5 makes bottom of the source polysilicon 3 in the vertical positioned at the polysilicon gate 6, so as to reduce the He of source polysilicon 3
Parasitic capacitance between the polysilicon gate 6.Compare Fig. 1 N corresponding to Fig. 2 and prior art to understand, the institute of the embodiment of the present invention
State polysilicon gate 6 and the source polysilicon 3 side pass on it is folded, the polysilicon gate 6 and the source polysilicon 3 it
Between parasitic capacitance as shown in the dotted line circle 301 in Fig. 2, so the Cgs2 of the embodiment of the present invention is the He of source polysilicon 3
Parasitic capacitance between the polysilicon gate 6 can be smaller.
Shield grid of embodiment of the present invention groove power device is MOSFET element, and the Semiconductor substrate 1 is first conductive
Type is adulterated, and in well region 7 of the surface of Semiconductor substrate 1 formed with the second conduction type, the polysilicon gate 6 is described in
Well region 7, it is used to form raceway groove by the surface of the well region 7 of the side of polysilicon gate 6 covering.
In source region 8 of the surface of well region 7 formed with the first conduction type heavy doping.
Be also formed with interlayer film 9, contact hole 10 and front metal layer 11 in the front of the Semiconductor substrate 1, source electrode and
Grid is formed by carrying out chemical wet etching to the front metal layer 11, and the source electrode is contacted by contact hole 10 and the source region 8,
The grid is contacted by contact hole 10 and the polysilicon gate 6.
Drain region is formed from the first conduction type heavily doped region composition at the back side of the Semiconductor substrate 1 after being thinned,
The back side in the drain region forms metal layer on back 12 as drain electrode.
In the embodiment of the present invention, source polysilicon draw-out area is externally formed with the device cell area, in the source
It is same formed with the second deep trench 201a, the second deep trench 201a and first deep trench 201 in the polysilicon draw-out area of pole
When formed and be connected and the width of the second deep trench 201a is more than the width of first deep trench 201, described the
Two deep trench 201a side and lower surface are formed with the bottom with same process condition in first deep trench 201
Dielectric layer 2, it is also filled with more than first in the interstitial area 202 between the bottom dielectric layer 2 of the second deep trench 201a
Crystal silicon layer 3, the width of the first polysilicon layer 3 in the second deep trench 201a are more than the in first deep trench 201
The width of one polysilicon layer 3, it is in order that being formed within more than the first of portion that the width of the second deep trench 201a, which is widened,
The width increase of crystal silicon layer 3 is so as to convenient in its Base top contact contact hole 10；Bottom dielectric in the second deep trench 201a
The both sides outer surface that layer 2 also extends into the second deep trench 201a, the bottom dielectric layer 2 in the second deep trench 201a
It is concordant with the top of the first polysilicon layer 3；The first polysilicon layer 3 in the second deep trench 201a is used as source polysilicon 3
And connection is contacted with each other with the source polysilicon 3 in first deep trench 201, it is more in the source electrode of the second deep trench 201a
The top of crystal silicon 3 is formed with contact hole 10 and is connected to the source electrode.
In well region contact of the bottom for the contact hole 10 being in contact with the source region 8 formed with the second conduction type heavy doping
Area.
In the embodiment of the present invention, shield grid groove power device is N-type device, and the first conduction type is N-type, and second is conductive
Type is p-type, and the Semiconductor substrate 1 is n-type doping.Also can be in other embodiments：Shield grid groove power device is P
Type device, the first conduction type are p-type, and the second conduction type is N-type, and the Semiconductor substrate 1 is adulterated for p-type.
Shield grid groove power device of the embodiment of the present invention is specifically designed to grid structure, and polysilicon gate 6, which uses, to be divided
From side grid structure, i.e. the deep trench of grid structure is that the first deep trench 201 includes two and is formed at the first deep trench 201
The polysilicon gate 6 that is side and being mutually isolated out at top, in the embodiment of the present invention, the lower surface of the first deep trench 201 and
Side formed with bottom dielectric layer 2, and by the thickness of bottom dielectric layer 2 has been carried out it is special setting bottom dielectric layer 2
After formation the first deep trench 201 middle section formed with width be less than or equal to gate oxide 4 thickness 2 times of interstitial area
202, so interstitial area 202 fill the first polysilicon layer 3 after, can with the first polysilicon layer 3 be self-aligned mask to bottom
Dielectric layer 2 carries out Self-aligned etching and forms bottom dielectric in the both sides of the first polysilicon layer 3 of the top area of the first deep trench 201
Layer 2 be removed after top channel 203, forming region of the top channel 203 as polysilicon gate 6；Between top channel 203
First polysilicon layer 3 can when forming gate oxide 4 complete oxidation be the second oxide layer of oxide layer 5, by top channel 203 it
Between the first polysilicon layer 3 be completely oxidized to the second oxide layer 5 and need to combine the above setting to the width of interstitial area 202, i.e.,
The width of interstitial area 202 is set smaller than to 2 times of interstitial area 202 of the thickness equal to gate oxide 4；So, the second oxidation
First polysilicon layer 3 of 5 bottom of layer is just automatically composed the source polysilicon 3 in the first deep trench 201, so so that source electrode is more
Crystal silicon 3 is located at the bottom of polysilicon gate 6 in the vertical, so as to reduce the parasitism electricity between source polysilicon 3 and polysilicon gate 6
Hold as shown in the dotted line circle 301 in Fig. 2, the dotted line circle 115 of parasitic capacitance and Fig. 1 N of the prior art shown in dotted line circle 301
Corresponding Cgs2 is corresponding, so the present invention can reduce Cgs2.From the foregoing, it will be observed that the present invention can reduce the parasitic electricity in grid source of device
Hold, from the input capacitance for improving device and improve the performance of device.
Further, since the present invention the second oxide layer 5 and need not be formed using extra technique, be in gate oxide 4
Thermal oxidation technology in thermal oxide simultaneously carried out to first polysilicon layer 3 at the top of the first deep trench 201 formed, this thermal oxide
Technique can not only be self aligned positioned at the bottom of polysilicon gate 6 by source polysilicon 3, and due to extra work need not be increased
Skill and there are relatively low process costs.
It is the device architecture schematic diagram in each step of present invention method as shown in Fig. 3 A to Fig. 3 I, Fig. 3 A extremely scheme
3I illustrates the structural representation of device cell area and source polysilicon draw-out area, shielding gate groove of the embodiment of the present invention simultaneously
The grid structure in the device cell area of the manufacture method of power device is formed using following steps：
Step 1: as shown in Figure 3A, there is provided semi-conductive substrate 1, using lithographic etch process in the Semiconductor substrate 1
The first deep trench 201 of middle formation.The second deep trench 201a, second deep trench are formed simultaneously in source polysilicon draw-out area
201a is connected with first deep trench 201 and the width of the second deep trench 201a is more than first deep trench 201
Width.First deep trench 201 is only illustrated in Fig. 3 A, actually shield grid groove power device can be by multiple
Device cell is formed in parallel, and a device cell will be formed at first deep trench 201, has multiple devices
Then need to form multiple first deep trench 201 during unit, because device unit construction is repetitive structure, therefore use an institute
The signal of the first deep trench 201 is stated, other devices cellular construction is all identical.And the second deep trench 201a then uses one
, at this moment the second deep trench 201a requirement is connected with first deep trench 201 of all device cells.
In the embodiment of the present invention, on the surface of Semiconductor substrate 1 formed with the first conductive type epitaxial layer, described first
Deep trench 201 and the second deep trench 201a are formed in first conductive type epitaxial layer.Preferably, it is described partly to lead
Body substrate 1 is silicon substrate, and the first conductive type epitaxial layer is silicon epitaxy layer.
In present invention method, hard mask layers 204 are employed, form institute on the surface of Semiconductor substrate 1 first
Hard mask layers 204 are stated, the first deep trench 201 and the second deep trench 201a forming region are opened in photoetching afterwards；Draw afterwards
By the first deep trench 201 and the hard mask layers 204 and the Semiconductor substrate 1 of the second deep trench 201a forming region
Etching forms first deep trench 201 and the second deep trench 201a.
Step 2: as shown in Figure 3 B, the hard mask layers 204 are removed first, then, in first deep trench 201
Lower surface and side form bottom dielectric layer 2, shown in Fig. 3 B, the bottom dielectric layer 2 also extends into described the
The outside of one deep trench 201 bottom dielectric layer 2 not by first deep trench 201 be filled up completely with and in first deep trench
For 201 middle section formed with interstitial area 202, the width of the interstitial area 202 is less than or equal to the gate oxide 4 being subsequently formed
2 times of thickness.Preferably, the bottom dielectric layer 2 is oxide layer.
The bottom dielectric layer 2 also is formed simultaneously in source polysilicon draw-out area, the bottom dielectric layer 2 can also extend to
The outer surface of the second deep trench 201a.Interstitial area between the bottom dielectric layer 2 of the second deep trench 201a
202 width can be bigger, is not limited by 2 times of the thickness less than or equal to the gate oxide 4 being subsequently formed, width needs to meet
Contact hole 10 is formed at the top of it.
Step 3: as shown in Figure 3 C, carry out polycrystalline silicon deposit the first polysilicon layer 3 of formation the interstitial area 202 is complete
Filling.
In source polysilicon draw-out area, the interstitial area between the bottom dielectric layer 2 of the second deep trench 201a
It is also filled with the first polysilicon layer 3 in 202, the width of the first polysilicon layer 3 in the second deep trench 201a is more than described
The width of the first polysilicon layer 3 in first deep trench 201；First polysilicon after the polycrystalline silicon deposit of step 3 is completed
Layer 3 also extends into first deep trench 201 and the second deep trench 201a outer surface.
As shown in Figure 3 D, polysilicon is also included after polycrystalline silicon deposit and returns carving technology, the polysilicon returns carving technology by described in
First polysilicon layer 3 in device cell area return be carved into surface it is equal with the surface of first deep trench 201 and will
First polysilicon layer 3 in the source polysilicon draw-out area goes back to the institute being carved into outside surface and the second deep trench 201a
The surface for stating bottom dielectric layer 2 is equal.In present invention method, returned in polysilicon in carving technology, when first polycrystalline
Silicon layer 3 return be carved into it is equal with the surface of the bottom dielectric layer 2 after, carry out photoetching process formed photoetching offset plate figure 205 will described in
Source polysilicon draw-out area is protected, and is continued polysilicon afterwards and is returned quarter, so follow-up polysilicon returns quarter will not be again to described
First polysilicon layer 3 in source polysilicon draw-out area performs etching.Polysilicon is returned after the completion of carving technology, and described second is deep
Source polysilicon 3 of first polysilicon layer 3 as source polysilicon 3 simultaneously and in first deep trench 201 in groove 201a
Contact with each other connection.The photoetching offset plate figure 205 is removed afterwards.
Step 4: it is that mask is carried out from right to the bottom dielectric layer 2 with first polysilicon layer 3 as shown in FIGURE 3 E
Standard, which is returned, carves, positioned at the quilt of the bottom dielectric layer 2 of the side of the top area of the first deep trench 201 after the autoregistration time quarter
Remove and first deep trench 201 top area first polysilicon layer 3 both sides formed top channel 203.
In present invention method, carry out the autoregistration and return before quarter first using photoetching process formation photoresist figure
Shape 206 protects the source polysilicon draw-out area, carries out the autoregistration afterwards and returns quarter, so by the photoetching offset plate figure
The bottom dielectric layer 2 in the region of 206 coverings is not etched；The autoregistration was returned after the completion of quarter, and the source polysilicon draws
The bottom dielectric layer 2 gone out in area can extend a distance into outside the second deep trench 201a, and elongated area is by photoetching work
The photoetching offset plate figure 206 that skill is formed is defined, and the bottom dielectric layer 2 outside elongated area is all removed.Institute is removed afterwards
State photoetching offset plate figure 206.
Step 5: as illustrated in Figure 3 F, thermal oxide is carried out, by the thermal oxidation technology in the position of the top channel 203
In forming gate oxide 4 on the side of the side of Semiconductor substrate 1, the thermal oxidation technology is simultaneously by the top channel
The complete oxidation of the first polysilicon layer 3 and the second oxide layer 5 of formation between 203；By the institute of the bottom of the second oxide layer 5
State the first polysilicon layer 3 composition source polysilicon 3.
Step 6: as shown in Figure 3 G, carry out polysilicon and be deposited on filling polysilicon in the top channel 203 and formed more
Crystal silicon grid 6；Second oxide layer 5 makes bottom of the source polysilicon 3 in the vertical positioned at the polysilicon gate 6, so as to
Reduce the parasitic capacitance between the source polysilicon 3 and the polysilicon gate 6.
The Semiconductor substrate 1 is adulterated for the first conduction type, after grid structure is formed, also comprises the following steps：
Step 7: as shown in figure 3h, carry out the trap that ion implanting forms the second conduction type in the Semiconductor substrate 1
Area 7；The source for carrying out the first conduction type heavy doping is infused in the surface of the well region 7 formation source region 8；To the well region 7 and described
Source region 8 carries out thermal annealing and promotes technique；It is used to form raceway groove by the surface of the well region 7 of the side of polysilicon gate 6 covering.
Step 8: as shown in fig. 31, interlayer film 9, contact hole 10 and front metal are formed in the front of Semiconductor substrate 1
Layer 11, chemical wet etching is carried out to the front metal layer 11 and forms source electrode and grid, the source electrode passes through contact hole 10 and described
Source region 8 is contacted, and the grid is contacted by contact hole 10 and the polysilicon gate 6.
Formed simultaneously at the top of the source polysilicon 3 of the second deep trench 201a in the source polysilicon draw-out area
Contact hole 10 is simultaneously connected to the source electrode by the contact hole 10.
The contact hole 10 opening formed after, it is metal filled before, be additionally included in the contact being in contact with the source region 8
The bottom in hole 10 carries out the step of the second conduction type heavily-doped implant forms well region contact zone.
Step 9: as shown in Fig. 2 the back side of Semiconductor substrate 1 be thinned and to form the first conduction type heavily doped
Miscellaneous drain region, metal layer on back 12 is formed at the back side in the drain region as drain electrode.
In present invention method, shield grid groove power device is N-type device, and the first conduction type is N-type, second
Conduction type is p-type, and the Semiconductor substrate 1 is n-type doping.Also can be in other embodiments method：Shield gate groove work(
Rate device is P-type device, and the first conduction type is p-type, and the second conduction type is N-type, and the Semiconductor substrate 1 is adulterated for p-type.
The present invention is described in detail above by specific embodiment, but these not form the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, and these also should
It is considered as protection scope of the present invention.
Claims (15)
1. a kind of shield grid groove power device, it is characterised in that the grid structure in device cell area includes：
The first deep trench being formed in Semiconductor substrate, in the lower surface of first deep trench and side formed with bottom
Dielectric layer；
First deep trench is not filled up completely with by the bottom dielectric layer and the middle section in first deep trench is formed
There is interstitial area, the width of the interstitial area is less than or equal to 2 times of the thickness of gate oxide；More than first are filled in the interstitial area
Crystal silicon layer；
The bottom dielectric layer positioned at the side of the first deep trench top area is removed and in first deep trench
Top area first polysilicon layer both sides formed with top channel；
Gate oxide be formed at the top channel on the side of the Semiconductor substrate side, the top channel it
Between first polysilicon layer be fully oxidized to form the second oxide layer while the gate oxide is formed；
Polysilicon gate is filled with side is formed with the top channel of the gate oxide and second oxide layer；
Source polysilicon is formed by first polysilicon layer of the second oxide layer bottom；Second oxide layer makes described
Source polysilicon is located at the bottom of the polysilicon gate in the vertical, so as to reduce the source polysilicon and the polysilicon gate
Between parasitic capacitance.
2. shield grid groove power device as claimed in claim 1, it is characterised in that：The Semiconductor substrate is first conductive
Type is adulterated, and in well region of the semiconductor substrate surface formed with the second conduction type, the polysilicon gate passes through the trap
Area, it is used to form raceway groove by the well region surface of polysilicon gate side covering；
In source region of the well region surface formed with the first conduction type heavy doping；
Interlayer film, contact hole and front metal layer are also formed with the front of the Semiconductor substrate, source electrode and grid are by institute
State front metal layer progress chemical wet etching to be formed, the source electrode is by contact hole and the source contact, and the grid is by connecing
Contact hole and polysilicon gate contact；
Drain region is formed from the first conduction type heavily doped region composition at the Semiconductor substrate back side after being thinned, in the leakage
The back side in area forms metal layer on back as drain electrode.
3. shield grid groove power device as claimed in claim 2, it is characterised in that：Outside shape in the device cell area
Into there is source polysilicon draw-out area, formed with the second deep trench, second deep trench in the source polysilicon draw-out area
With first deep trench simultaneously formed and be connected and the width of second deep trench be more than first deep trench width
Degree, the side of second deep trench and lower surface formed with described in same process condition in first deep trench
Bottom dielectric layer, the first polysilicon is also filled with the interstitial area between the bottom dielectric layer of second deep trench
Layer, the width of the first polysilicon layer in second deep trench is more than the width of the first polysilicon layer in first deep trench
Degree；Bottom dielectric layer in second deep trench also extends into the both sides outer surface of second deep trench, and described second
The top of bottom dielectric layer and the first polysilicon layer in deep trench is concordant；The first polysilicon layer in second deep trench is made
Connection is contacted with each other for source polysilicon and with the source polysilicon in first deep trench, in the source of second deep trench
The top of pole polysilicon is formed with contact hole and is connected to the source electrode.
4. shield grid groove power device as claimed in claim 1, it is characterised in that：The bottom dielectric layer is oxide layer.
5. shield grid groove power device as claimed in claim 2, it is characterised in that：In the contact being in contact with the source region
Well region contact zone of the bottom in hole formed with the second conduction type heavy doping.
6. the manufacture method of shield grid groove power device as claimed in claim 2, it is characterised in that：Shield grid groove power
Device is N-type device, and the first conduction type is N-type, and the second conduction type is p-type, and the Semiconductor substrate is n-type doping；Or
Person, shield grid groove power device are P-type device, and the first conduction type is p-type, and the second conduction type is N-type, the semiconductor
Substrate adulterates for p-type.
7. the shield grid groove power device as described in any claim in claim 1 to 6, it is characterised in that：Described half
Conductor substrate is silicon substrate.
8. a kind of manufacture method of shield grid groove power device, it is characterised in that the grid structure in device cell area is using such as
Lower step is formed：
Step 1: providing semi-conductive substrate, the first deep trench is formed in the Semiconductor substrate using lithographic etch process；
Step 2: form bottom dielectric layer in the lower surface of first deep trench and side；The bottom dielectric layer will not
First deep trench be filled up completely with and first deep trench middle section formed with interstitial area, the width of the interstitial area
Degree is less than or equal to 2 times of the thickness for the gate oxide being subsequently formed；
The interstitial area is filled up completely with Step 3: carrying out polycrystalline silicon deposit and forming the first polysilicon layer；
Carved Step 4: carrying out autoregistration to the bottom dielectric layer using first polysilicon layer as mask and returning, the autoregistration
The bottom dielectric layer that Hui Kehou is located at the side of the first deep trench top area is removed and in first zanjon
The both sides of first polysilicon layer of the top area of groove form top channel；
Step 5: carrying out thermal oxide, the Semiconductor substrate one is located in the top channel by the thermal oxidation technology
Gate oxide is formed on the side of side, the thermal oxidation technology is simultaneously by first polysilicon layer between the top channel
Complete oxidation simultaneously forms the second oxide layer；Source electrode polycrystalline is formed by first polysilicon layer of the second oxide layer bottom
Silicon；
It is deposited on filling polysilicon in the top channel Step 6: carrying out polysilicon and forms polysilicon gate；Second oxygen
Change the bottom that layer makes the source polysilicon be located at the polysilicon gate in the vertical, so as to reduce the source polysilicon and institute
State the parasitic capacitance between polysilicon gate.
9. the manufacture method of shield grid groove power device as claimed in claim 8, it is characterised in that：The Semiconductor substrate
Adulterate for the first conduction type, after grid structure is formed, also comprise the following steps：
Step 7: carry out the well region that ion implanting forms the second conduction type in the Semiconductor substrate；It is conductive to carry out first
The source of type heavy doping is infused in the well region surface and forms source region；Thermal annealing is carried out to the well region and the source region and promotes work
Skill；It is used to form raceway groove by the well region surface of polysilicon gate side covering；
Step 8: interlayer film, contact hole and front metal layer are formed in Semiconductor substrate front, to the front metal layer
Carry out chemical wet etching formation source electrode and grid, the source electrode pass through contact by contact hole and the source contact, the grid
Hole and polysilicon gate contact；
Step 9: the Semiconductor substrate back side be thinned and forms the drain region of the first conduction type heavy doping, described
The back side in drain region forms metal layer on back as drain electrode.
10. the manufacture method of shield grid groove power device as claimed in claim 9, it is characterised in that：In the device list
First area is externally formed with source polysilicon draw-out area, formed with the second deep trench, institute in the source polysilicon draw-out area
State the second deep trench and first deep trench while formed and be connected and the width of second deep trench in step 1
More than the width of first deep trench；
In step 2 the side of second deep trench and lower surface formed with same process in first deep trench
The bottom dielectric layer of condition；The bottom dielectric layer also extends into the outer of first deep trench and second deep trench
Portion surface；
The first polysilicon is also filled with interstitial area in step 3 between the bottom dielectric layer of second deep trench
Layer, the width of the first polysilicon layer in second deep trench is more than the width of the first polysilicon layer in first deep trench
Degree；First polysilicon layer also extends into first deep trench and described second after the polycrystalline silicon deposit of step 3 is completed
The outer surface of deep trench；
Also include polysilicon after the polycrystalline silicon deposit of step 3 and return carving technology, the polysilicon returns carving technology by the device cell
First polysilicon layer in area returns that to be carved into surface equal with the surface of first deep trench and by the source electrode polycrystalline
First polysilicon layer in silicon draw-out area returns the table for being carved into surface and the bottom dielectric layer outside second deep trench
Face is equal；Source electrode of first polysilicon layer as source polysilicon simultaneously and in first deep trench in second deep trench
Polysilicon contacts with each other connection；
The autoregistration of step 4 is returned after the completion of carving technology, described outside first deep trench in the device cell area
Bottom dielectric layer is all removed；The bottom dielectric layer in the source polysilicon draw-out area can be to outside second deep trench
Extend a distance into, elongated area is defined by photoetching process, and the bottom dielectric layer outside elongated area is all removed；
Contact hole is formed in step 8 at the top of the source polysilicon of second deep trench simultaneously and is connected by the contact hole
It is connected to the source electrode.
11. the manufacture method of shield grid groove power device as claimed in claim 10, it is characterised in that：Described in step 8
The opening of contact hole formed after, it is metal filled before, the bottom for being additionally included in the contact hole being in contact with the source region carries out second
Conduction type heavily-doped implant forms the step of well region contact zone.
12. the manufacture method of shield grid groove power device as claimed in claim 10, it is characterised in that：The bottom dielectric
Layer is oxide layer.
13. the manufacture method of shield grid groove power device as claimed in claim 10, it is characterised in that：Shield gate groove work(
Rate device is N-type device, and the first conduction type is N-type, and the second conduction type is p-type, and the Semiconductor substrate is n-type doping；
Or shield grid groove power device is P-type device, the first conduction type is p-type, and the second conduction type is N-type, described partly to lead
Body substrate adulterates for p-type.
14. the manufacture method of shield grid groove power device as claimed in claim 10, it is characterised in that：In the semiconductor
Substrate surface is formed in described formed with the first conductive type epitaxial layer, first deep trench and second deep trench
In one conductive type epitaxial layer.
15. the manufacture method of the shield grid groove power device as described in any claim in claim 8 to 14, its feature
It is：The Semiconductor substrate is silicon substrate.
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| CN112864248A (en) * | 2019-11-28 | 2021-05-28 | 南通尚阳通集成电路有限公司 | SGTMOSFET device and manufacturing method |
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