CN112242305A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN112242305A CN112242305A CN202011166437.4A CN202011166437A CN112242305A CN 112242305 A CN112242305 A CN 112242305A CN 202011166437 A CN202011166437 A CN 202011166437A CN 112242305 A CN112242305 A CN 112242305A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 55
- 238000000034 method Methods 0.000 title claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 108
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 230000003647 oxidation Effects 0.000 claims abstract description 47
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 47
- 238000002955 isolation Methods 0.000 claims abstract description 41
- 238000005468 ion implantation Methods 0.000 claims abstract description 19
- 229920005591 polysilicon Polymers 0.000 claims description 67
- 239000002184 metal Substances 0.000 claims description 25
- 238000005530 etching Methods 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 12
- 230000005669 field effect Effects 0.000 claims description 3
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 125000006850 spacer group Chemical group 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract description 7
- 150000002500 ions Chemical class 0.000 description 11
- 230000015556 catabolic process Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
Abstract
The invention provides a semiconductor device and a manufacturing method thereof, comprising the following steps: a substrate; a plurality of trenches formed in the substrate; the grid structure is positioned in each groove and comprises a shielding grid polycrystalline silicon layer, a first oxidation layer, a second oxidation layer and an isolation side wall, wherein the first oxidation layer covers the inner wall of the groove, the shielding grid polycrystalline silicon layer is positioned on the first oxidation layer and fills the groove, the top of the first oxidation layer is lower than the top of the groove, so that a first opening is formed between the side wall of the groove and the shielding grid polycrystalline silicon layer, the second oxidation layer covers the surface of the substrate and the inner wall of the first opening and exposes the top of the first oxidation layer, the grid polycrystalline silicon layer is positioned on the first oxidation layer and fills the partial depth of the first opening, and the isolation side wall is positioned on the grid polycrystalline silicon layer and covers the second oxidation layer on the side wall of the. The invention improves the defects of the grid oxide layer and the problem of threshold voltage reduction of the semiconductor device caused by the ion implantation process.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a manufacturing method thereof.
Background
In a trench type semiconductor device, a gate is usually formed in a trench, and a source is formed at a side of the gate, the gate and the source are isolated by a gate oxide layer, the quality of the gate oxide layer determines a Threshold Voltage (Threshold Voltage) and related characteristics of the device, and the stability of the device is finally affected.
However, in the etching of the gate polysilicon layer, the etching degree of the gate polysilicon layer is inconsistent due to the etching process, and when the etching of the gate polysilicon layer is serious, the top of the gate polysilicon layer is further close to the well region, namely closer to the channel; subsequent gate oxide etching can also over etch the corner between the top of the gate polysilicon layer and the gate oxide.
In the subsequent ion implantation process, the gate oxide layer is further damaged, so that the gate oxide layer generates defects, and because the top of the gate polysilicon layer is closer to the channel, the implanted ions are easy to scatter into the channel through the gate oxide layer, and finally the threshold voltage of the semiconductor device is reduced. There is therefore a need for a device and method that can ameliorate the threshold voltage drop problem of semiconductor devices due to gate oxide defects and ion implantation processes.
Disclosure of Invention
The invention aims to provide a semiconductor device and a manufacturing method thereof, which are used for solving the problem of threshold voltage reduction of the semiconductor device caused by defects of a grid oxide layer and an ion implantation process.
In order to achieve the above object, the present invention provides a semiconductor device comprising:
a substrate;
a plurality of trenches formed in the substrate;
the grid structure is positioned in each groove and comprises a shielding grid polycrystalline silicon layer, a first oxidation layer, a second oxidation layer and an isolation side wall, wherein the first oxidation layer covers the inner wall of the groove, the shielding grid polycrystalline silicon layer is positioned on the first oxidation layer and fills the groove, the top of the first oxidation layer is lower than the top of the groove, so that a first opening is formed between the side wall of the groove and the shielding grid polycrystalline silicon layer, the second oxidation layer covers the surface of the substrate and the inner wall of the first opening and exposes the top of the first oxidation layer, the grid polycrystalline silicon layer is positioned on the first oxidation layer and fills the partial depth of the first opening, and the isolation side wall is positioned on the grid polycrystalline silicon layer and covers the second oxidation layer on the side wall of the first opening.
Optionally, the substrate includes a substrate and an epitaxial layer on the substrate, the trench is located in the epitaxial layer, a source region and a well region are formed in the epitaxial layer on both sides of the gate structure, the source region is located above the surface of the well region, and a drain region is formed on the back surface of the substrate.
Optionally, a third oxide layer is further formed on the second oxide layer, the third oxide layer has a second opening, a third opening and a fourth opening, the second opening exposes at least a portion of the top surface of the gate polysilicon layer, the third opening exposes at least a portion of the top surface of the shield gate polysilicon layer, and the fourth opening extends into the well region;
a front metal layer is formed on the third oxide layer, covers the third oxide layer and fills the second opening, the third opening and the fourth opening so as to be electrically connected with the gate polysilicon layer, the shielding gate polysilicon layer, the source region and the well region;
and a back metal layer is formed on the back of the drain region and is electrically connected with the drain region.
Optionally, the depth and the width of the plurality of grooves are the same and extend along the same direction.
Optionally, the top of the shield gate polysilicon layer is flush with the top of the trench.
Optionally, the isolation spacer is made of a nitride or an oxide.
Optionally, the semiconductor device is a trench field effect transistor.
The present invention also provides a method for manufacturing a semiconductor device, comprising:
providing a substrate, wherein a plurality of grooves are formed in the substrate;
forming a grid structure in each groove, wherein the grid structure comprises a shielding grid polycrystalline silicon layer, a first oxidation layer, a second oxidation layer and an isolation side wall, the first oxide layer covers the inner wall of the groove, the shielding grid polycrystalline silicon layer is positioned on the first oxide layer and fills the groove, the top of the first oxide layer is lower than the top of the groove, so that a first opening is formed between the side wall of the trench and the shield grid polycrystalline silicon layer, the second oxide layer covers the surface of the substrate and the inner wall of the first opening and exposes the top of the first oxide layer, the gate polysilicon layer is located on the first oxide layer and fills a partial depth of the first opening, the isolation side wall is positioned on the grid polycrystalline silicon layer and covers the second oxidation layer on the side wall of the first opening.
Optionally, the step of forming the gate structure includes:
forming the first oxidation layer on the inner wall of the groove, wherein the first oxidation layer covers the surface of the substrate and the inner wall of the groove;
forming the shielding grid polycrystalline silicon layer on the first oxide layer, wherein the shielding grid polycrystalline silicon layer fills the groove;
etching the shielding gate polycrystalline silicon layer to enable the top of the shielding gate polycrystalline silicon layer to be flush with the top of the groove;
etching the first oxidation layer to enable the first oxidation layer to be lower than the top of the groove, and forming the first opening;
forming the second oxide layer on the inner wall of the first opening, wherein the second oxide layer covers the surface of the substrate and the inner wall of the first opening and exposes the bottom of the first oxide layer;
forming the grid polycrystalline silicon layer on the first oxidation layer, wherein the grid polycrystalline silicon layer covers the first oxidation layer and the second oxidation layer and fills the first opening;
and etching the grid polycrystalline silicon layer to enable the grid polycrystalline silicon layer to be lower than the top of the first opening.
Optionally, after the etching the gate polysilicon layer, the step of forming the gate structure further includes:
forming an isolation material layer on the substrate, wherein the isolation material layer covers the inner wall of the first opening and extends to cover the substrate;
and etching to remove the isolation material layer on the surface of the substrate and on the bottom wall of the first opening, wherein the isolation material layer on the side wall of the first opening forms the isolation side wall.
Optionally, after the gate structure is manufactured, the method further includes:
and carrying out ion implantation on the substrate outside the grid polycrystalline silicon layer to form a well region and a source region, wherein the source region is positioned above the surface of the well region.
Optionally, after the ion implantation, the method further includes:
forming a third oxide layer on the second oxide layer, wherein the third oxide layer covers the surface of the substrate and fills the first opening;
etching the third oxide layer to form a second opening, a third opening and a fourth opening, wherein the second opening exposes at least part of the top surface of the gate polysilicon layer, the third opening exposes at least part of the top surface of the shield gate polysilicon layer, and the fourth opening extends to the well region;
forming a front metal layer on the third oxide layer, wherein the front metal layer covers the third oxide layer and fills the second opening, the third opening and the fourth opening to be electrically connected with the gate polysilicon layer, the shielding gate polysilicon layer, the source region and the well region;
and forming a drain region on the back surface of the substrate, forming a back metal layer on the back surface of the drain region, and electrically connecting the back metal layer with the drain region.
According to the semiconductor device and the manufacturing method thereof provided by the invention, the isolation side wall is formed on the side wall of the second oxide layer, the second oxide layer is the grid oxide layer, the isolation side wall can prevent the second oxide layer from being damaged in the subsequent ion implantation process, and injected ions are prevented from entering a channel through scattering of the second oxide layer, so that the threshold voltage of the semiconductor device is prevented from being reduced, and the electrical property of the semiconductor device is finally improved.
Drawings
Fig. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention;
FIGS. 2A-2E are schematic cross-sectional views illustrating steps of a method for fabricating a semiconductor device according to an embodiment of the present invention;
wherein the reference numerals are:
1-a substrate; 2-a groove; 3-a gate structure; 101-a substrate; 102-an epitaxial layer; 301-a first oxide layer; 302-shield gate polysilicon layer; 303 — second oxide layer; 304-a gate polysilicon layer; 305-isolation side walls; 306 — a first opening; 401-well region; 402-a source region; 501-a third oxide layer; 502-a gate; 503-a source electrode; 504-drain; 505 — a second opening; 506-a third opening; 507-fourth opening.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Fig. 1 is a schematic cross-sectional view of a semiconductor device provided in this embodiment, and fig. 2A to 2E are schematic cross-sectional views of steps of a method for manufacturing the semiconductor device provided in this embodiment. The invention provides a semiconductor device, which is used for improving the problem of threshold voltage reduction of the semiconductor device caused by defects of a grid oxide layer and an ion implantation process. Referring to fig. 1, a substrate 1 includes a substrate 101 and an epitaxial layer 102 on the substrate 101, a plurality of trenches 2 are formed in the substrate 1, specifically, the plurality of trenches 2 are located in the epitaxial layer 102, the depth and width of the plurality of trenches 2 are the same and extend along the same direction, and only two trenches 2 are shown in the present embodiment.
The gate structure 3 is located in each trench 2, the gate structure 3 includes a shield gate polysilicon layer 302, a gate polysilicon layer 304, a first oxide layer 301, a second oxide layer 303 and isolation side walls 305, wherein the first oxide layer 301 covers the inner wall of the trench 2, the shield gate polysilicon layer 302 is located on the first oxide layer 301 and fills the trench 2, the top of the first oxide layer 301 is lower than the top of the trench 2, so that a first opening is formed between the side wall of the trench 2 and the shield gate polysilicon layer 302, and the top of the shield gate polysilicon layer 302 is flush with the top of the trench 2.
The second oxide layer 303 covers the surface of the epitaxial layer 102 and the inner wall of the first opening and exposes the top of the first oxide layer 301, the gate polysilicon layer 304 is located on the first oxide layer 301 and fills a partial depth of the first opening, and the second oxide layer 303 is a gate oxide layer; the isolation side wall 305 is located on the gate polysilicon layer 304 and covers the second oxide layer 303 on the side wall of the first opening, the isolation side wall 305 is made of nitride or oxide, the isolation side wall 305 is used for protecting the second oxide layer 303, and is prevented from damaging the second oxide layer 303 in the manufacturing process of a semiconductor device, the breakdown voltage of the semiconductor device is reduced due to the damage of the second oxide layer 303, the gate leakage capacity is enhanced, the performance of the semiconductor device is reduced, therefore, the threshold voltage of the semiconductor device can be prevented from being reduced due to the formation of the isolation side wall 305, and finally, the electrical performance of the semiconductor device is improved. A well region 401 and a source region 402 are formed in the epitaxial layer 102 on both sides of the gate structure 3, and the source region 402 is located above the surface of the well region 401.
Further, a third oxide layer 501 is formed on the substrate 1, specifically, the third oxide layer 501 is formed on the second oxide layer 303, the third oxide layer 501 has a second opening, a third opening and a fourth opening, the second opening exposes at least a portion of the top surface of the gate polysilicon layer 304, the third opening exposes at least a portion of the top surface of the shielding gate polysilicon layer 302, and the fourth opening extends into the well region 402; a front metal layer is formed on the third oxide layer 501, and the front metal layer covers the third oxide layer 501 and fills the second opening, the third opening, and the fourth opening to electrically connect the gate polysilicon layer 304, the shield gate polysilicon layer 302, the well region 401, and the source region 402; the front metal layer is patterned by a photolithography etching process to form a gate 502 and a source 503, the gate 502 is electrically connected to the gate polysilicon layer 304 through the second opening, the source 503 is electrically connected to the shield gate polysilicon layer 302 through the third opening, and the source 503 is also electrically connected to the source region 402 and the well region 401 through the fourth opening.
A drain region is formed on the back surface of the substrate 101, a back metal layer is formed on the back surface of the drain region, the back metal layer is electrically connected to the drain region, and the back metal layer serves as the drain 504. In the present embodiment, the semiconductor device is a trench type field effect transistor.
The present invention also provides a method for manufacturing a semiconductor device, which is used to improve the problem of threshold voltage drop of the semiconductor device caused by gate oxide defects and ion implantation processes, and referring to fig. 1 again, the method includes: providing a substrate 1, forming a plurality of trenches 2 in the substrate 1, wherein the substrate 1 comprises a substrate 101 and an epitaxial layer 102, and specifically forming a plurality of trenches 2 in the epitaxial layer 102.
Forming a gate structure 3 in the trench 2, the gate structure 3 being located in each trench 2, the gate structure 3 including a shield gate polysilicon layer 302, a gate polysilicon layer 304, a first oxide layer 301, a second oxide layer 303 and isolation sidewalls 305, the first oxide layer 301 covering the inner wall of the trench 2, the shield gate polysilicon layer 302 being located on the first oxide layer 301 and filling the trench 2, the top of the first oxide layer 301 being lower than the top of the trench 2, so that a first opening 306 is formed between the sidewall of the trench 2 and the shield gate polysilicon layer 302, the second oxide layer 303 covers the surface of the epitaxial layer 102 and the inner wall of the first opening and exposes the top of the first oxide layer 301, the gate polysilicon layer 304 is located on the first oxide layer 301 and fills a partial depth of the first opening 306, and the isolation sidewall 305 is located on the gate polysilicon layer 304 and covers the second oxide layer 303 on the sidewall of the first opening 306.
The specific steps for forming the gate structure include: referring to fig. 2A, a first oxide layer 301 is formed on the inner wall of the trench 2, wherein the first oxide layer 301 covers the surface of the epitaxial layer 102 and the inner wall of the trench 2; a shield gate polysilicon layer 302 is formed on the first oxide layer 301, and the shield gate polysilicon layer 302 fills the trench 2.
Referring to fig. 2B, the shield gate polysilicon layer 302 is dry etched so that the top of the shield gate polysilicon layer 302 is flush with the top of the trench 2; the first oxide layer 301 is etched such that the first oxide layer 301 is below the top of the trench 2 and such that a first opening 306 is formed between the sidewalls of the trench 2 and the shield gate polysilicon layer 302.
Referring to fig. 2C, a second oxide layer 303 is formed on the inner wall of the first opening 306, the second oxide layer 303 covers the surface of the epitaxial layer 102 and the inner wall of the first opening and exposes the top of the first oxide layer 301, the second oxide layer 303 is a gate oxide layer, in this embodiment, the second oxide layer 303 adopts a thermal oxide growth method, the second oxide layer 303 is grown only on the surface of the epitaxial layer 102 and the inner wall of the first opening, the second oxide layer 303 is not grown on the bottom of the first opening, that is, on the top of the first oxide layer 301, and other methods can be used to form the second oxide layer 303. A gate polysilicon layer 304 is formed on the first oxide layer 301, the gate polysilicon layer 304 filling the first opening 306 and covering the top of the first oxide layer 301 and the second oxide layer 303. The gate polysilicon layer 304 is dry etched so that the top of the gate polysilicon layer 304 is lower than the top of the first opening 306, and when the gate polysilicon layer 304 is etched, the second oxide layer 303 is prone to generate defects due to the etching process, and finally the threshold voltage of the semiconductor device is reduced. In this embodiment, the second oxide layer 303 may be subjected to a subsequent ion implantation process without being removed, or the second oxide layer 303 may be etched to thin the second oxide layer 303 for facilitating the subsequent ion implantation.
Referring to fig. 2D, after etching the gate polysilicon layer 304, the step of forming the gate structure 3 further includes: forming a layer of isolation material on the epitaxial layer 102, the layer of isolation material covering the inner wall of the first opening 306 and extending to cover the surface of the epitaxial layer 102; the isolation material layer on the surface of the epitaxial layer 102 and on the bottom wall of the first opening 306 is removed by etching, and the isolation material layer on the sidewall of the first opening 306 is remained to form the isolation sidewall spacers 305.
Further, after forming the gate structure 3, the method further includes: the epitaxial layer 102 outside the gate polysilicon layer 304 is ion implanted to form a well region 401 and a source region 402, and the source region 402 is located above the surface of the well region 401, specifically, the well region 401 and the source region 402 are formed by two times of implantation of different types of ions. In fig. 2D, the direction indicated by the arrow is the direction of ion implantation, and the region indicated by the arrow is the region of ion implantation. In the present embodiment, if the ion type of the well region 401 is P type, the ion type of the source region 402 is N type; if the ion type of the well 401 is N type, the ion type of the source region 402 is P type.
In the ion implantation process, the isolation side wall 305 protects the second oxide layer 303, so that the second oxide layer 303 is prevented from being further damaged in the ion implantation, the breakdown voltage of the semiconductor device is reduced due to the damage of the second oxide layer 303, the gate leakage capacity is enhanced, the performance of the semiconductor device is reduced, and the service life of the semiconductor device is influenced; the implanted ions are scattered into the channel through the second oxide layer 303, when the semiconductor device is powered on, the channel is formed at the boundary between the second oxide layer 303 and the epitaxial layer 102, when the ions are scattered into the channel, the threshold voltage of the semiconductor device is reduced, and the isolation side wall 305 can prevent the threshold voltage of the semiconductor device from being reduced, so that the electrical performance of the semiconductor device is finally improved.
Referring to fig. 2E, after the ion implantation process, the method further includes: a third oxide layer 501 is formed on the surface of the second oxide layer 303, and the third oxide layer 501 covers the surface of the epitaxial layer 102 and fills the first opening. And etching the third oxide layer by using an etching process to form a second opening, a third opening and a fourth opening, wherein the second opening 505 exposes at least a portion of the top surface of the gate polysilicon layer 304, the third opening 506 exposes at least a portion of the top surface of the shield gate polysilicon layer 302, and the fourth opening 507 extends into the well region 401.
Referring to fig. 1 again, a front metal layer is formed on the third oxide layer 501, the front metal layer covers the third oxide layer 501 and fills the second opening, the third opening, and the fourth opening, and the front metal layer is electrically connected to the gate polysilicon layer 304, the shield gate polysilicon layer 302, the well region 401, and the source region 402; the front metal layer is patterned by a photolithography etching process to form a gate 502 and a source 503, the gate 502 is electrically connected to the gate polysilicon layer 304 through the second opening, the source 503 is electrically connected to the shield gate polysilicon layer 302 through the third opening, and the source 503 is also electrically connected to the source region 402 and the well region 401 through the fourth opening.
A drain region is formed on the back surface of the substrate 101, a back metal layer is formed on the back surface of the drain region, the back metal layer is electrically connected to the drain region, and the back metal layer serves as the drain 504.
In summary, according to the semiconductor device and the manufacturing method thereof provided by the present invention, the isolation sidewall is formed on the sidewall of the second oxide layer, the second oxide layer is the gate oxide layer, and the isolation sidewall can prevent the second oxide layer from being damaged in the subsequent ion implantation process, and prevent the implanted ions from entering the channel through scattering of the second oxide layer, so that the threshold voltage of the semiconductor device is prevented from being reduced, and the electrical performance of the semiconductor device is finally improved.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (12)
1. A semiconductor device, comprising:
a substrate;
a plurality of trenches formed in the substrate;
the grid structure is positioned in each groove and comprises a shielding grid polycrystalline silicon layer, a first oxidation layer, a second oxidation layer and an isolation side wall, wherein the first oxidation layer covers the inner wall of the groove, the shielding grid polycrystalline silicon layer is positioned on the first oxidation layer and fills the groove, the top of the first oxidation layer is lower than the top of the groove, so that a first opening is formed between the side wall of the groove and the shielding grid polycrystalline silicon layer, the second oxidation layer covers the surface of the substrate and the inner wall of the first opening and exposes the top of the first oxidation layer, the grid polycrystalline silicon layer is positioned on the first oxidation layer and fills the partial depth of the first opening, and the isolation side wall is positioned on the grid polycrystalline silicon layer and covers the second oxidation layer on the side wall of the first opening.
2. The semiconductor device according to claim 1, wherein the base comprises a substrate and an epitaxial layer on the substrate, the trench is located in the epitaxial layer, a source region and a well region are formed in the epitaxial layer on both sides of the gate structure, the source region is located above the surface of the well region, and a drain region is formed on the back surface of the substrate.
3. The semiconductor device according to claim 2, wherein a third oxide layer is further formed on the second oxide layer, the third oxide layer has a second opening, a third opening and a fourth opening therein, the second opening exposes at least a portion of the top surface of the gate polysilicon layer, the third opening exposes at least a portion of the top surface of the shield gate polysilicon layer, and the fourth opening extends into the well region;
a front metal layer is formed on the third oxide layer, covers the third oxide layer and fills the second opening, the third opening and the fourth opening so as to be electrically connected with the gate polysilicon layer, the shielding gate polysilicon layer, the source region and the well region;
and a back metal layer is formed on the back of the drain region and is electrically connected with the drain region.
4. The semiconductor device of claim 1, wherein a depth and a width of the plurality of trenches are the same and extend in the same direction.
5. The semiconductor device of claim 1, wherein a top of the shield gate polysilicon layer is flush with a top of the trench.
6. The semiconductor device of claim 1, wherein the isolation sidewall spacers comprise a nitride or an oxide.
7. The semiconductor device according to claim 1, wherein the semiconductor device is a trench field effect transistor.
8. A method of manufacturing a semiconductor device, comprising:
providing a substrate, wherein a plurality of grooves are formed in the substrate;
forming a grid structure in each groove, wherein the grid structure comprises a shielding grid polycrystalline silicon layer, a first oxidation layer, a second oxidation layer and an isolation side wall, the first oxide layer covers the inner wall of the groove, the shielding grid polycrystalline silicon layer is positioned on the first oxide layer and fills the groove, the top of the first oxide layer is lower than the top of the groove, so that a first opening is formed between the side wall of the trench and the shield grid polycrystalline silicon layer, the second oxide layer covers the surface of the substrate and the inner wall of the first opening and exposes the top of the first oxide layer, the gate polysilicon layer is located on the first oxide layer and fills a partial depth of the first opening, the isolation side wall is positioned on the grid polycrystalline silicon layer and covers the second oxidation layer on the side wall of the first opening.
9. The method for manufacturing a semiconductor device according to claim 8, wherein the step of forming the gate structure comprises:
forming the first oxidation layer on the inner wall of the groove, wherein the first oxidation layer covers the surface of the substrate and the inner wall of the groove;
forming the shielding grid polycrystalline silicon layer on the first oxide layer, wherein the shielding grid polycrystalline silicon layer fills the groove;
etching the shielding gate polycrystalline silicon layer to enable the top of the shielding gate polycrystalline silicon layer to be flush with the top of the groove;
etching the first oxidation layer to enable the first oxidation layer to be lower than the top of the groove, and forming the first opening;
forming the second oxide layer on the inner wall of the first opening, wherein the second oxide layer covers the surface of the substrate and the inner wall of the first opening and exposes the bottom of the first oxide layer;
forming the grid polycrystalline silicon layer on the first oxidation layer, wherein the grid polycrystalline silicon layer covers the first oxidation layer and the second oxidation layer and fills the first opening;
and etching the grid polycrystalline silicon layer to enable the grid polycrystalline silicon layer to be lower than the top of the first opening.
10. The method of manufacturing a semiconductor device according to claim 9, wherein the step of forming the gate structure after etching the gate polysilicon layer further comprises:
forming an isolation material layer on the substrate, wherein the isolation material layer covers the inner wall of the first opening and extends to cover the substrate;
and etching to remove the isolation material layer on the surface of the substrate and on the bottom wall of the first opening, wherein the isolation material layer on the side wall of the first opening forms the isolation side wall.
11. The method for manufacturing a semiconductor device according to claim 10, further comprising, after the gate structure is completed, the steps of:
and carrying out ion implantation on the substrate outside the grid polycrystalline silicon layer to form a well region and a source region, wherein the source region is positioned above the surface of the well region.
12. The method for manufacturing a semiconductor device according to claim 11, further comprising, after the ion implantation:
forming a third oxide layer on the substrate, wherein the third oxide layer covers the surface of the second oxide layer and fills the first opening;
etching the third oxide layer to form a second opening, a third opening and a fourth opening, wherein the second opening exposes at least part of the top surface of the gate polysilicon layer, the third opening exposes at least part of the top surface of the shield gate polysilicon layer, and the fourth opening extends to the well region;
forming a front metal layer on the third oxide layer, wherein the front metal layer covers the third oxide layer and fills the second opening, the third opening and the fourth opening to be electrically connected with the gate polysilicon layer, the shielding gate polysilicon layer, the source region and the well region;
and forming a drain region on the back surface of the substrate, forming a back metal layer on the back surface of the drain region, and electrically connecting the back metal layer with the drain region.
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