CN113192827A - Method for manufacturing semiconductor device - Google Patents
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- CN113192827A CN113192827A CN202110461289.7A CN202110461289A CN113192827A CN 113192827 A CN113192827 A CN 113192827A CN 202110461289 A CN202110461289 A CN 202110461289A CN 113192827 A CN113192827 A CN 113192827A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000000034 method Methods 0.000 title claims description 39
- 238000004519 manufacturing process Methods 0.000 title claims description 20
- 239000000758 substrate Substances 0.000 claims abstract description 60
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 56
- 238000005530 etching Methods 0.000 claims abstract description 50
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 31
- 229920005591 polysilicon Polymers 0.000 claims description 31
- 238000005468 ion implantation Methods 0.000 claims description 13
- 239000004020 conductor Substances 0.000 claims description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 238000002360 preparation method Methods 0.000 abstract description 4
- 230000003071 parasitic effect Effects 0.000 description 12
- 229920000642 polymer Polymers 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
Abstract
The invention provides a preparation method of a semiconductor device, which comprises the following steps: providing a substrate, and forming a plurality of grid structures and a plurality of target areas in the substrate, wherein the target areas are arranged on two sides of the grid structures; forming a dielectric layer on the surface of the substrate; forming a patterned photoresist layer on the dielectric layer, the patterned photoresist layer having a plurality of first openings, one of the first openings being aligned with one of the target regions; etching the dielectric layer by taking the patterned photoresist layer as a mask so as to form a plurality of second openings in the dielectric layer; removing the patterned photoresist layer; and etching a part of the depth of the substrate along the bottom of the second openings to form a plurality of third openings, wherein one second opening is communicated with one third opening and forms a first connecting through hole.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a preparation method of a semiconductor device.
Background
The shielded gate trench transistor is a typical trench transistor, a parasitic triode is formed among a gate, a source region and a drain region of the shielded gate trench transistor, a base of the parasitic triode is connected with a source region of a device, and the parasitic triode is easy to conduct due to high base voltage of the parasitic triode, so that the electrical performance of the device is affected. When the shielded gate trench transistor is manufactured, the size window of the connecting through hole is small due to the influence of an etching process, so that the base resistance of the parasitic triode is large, the base resistance of the parasitic triode represents that the base voltage of the parasitic triode is large, the base voltage is large, the parasitic triode is easy to conduct, and the electrical property of a device is influenced.
Disclosure of Invention
The invention aims to provide a preparation method of a semiconductor device, which is used for improving the electrical property of the semiconductor device.
In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device, comprising:
providing a substrate, and forming a plurality of grid structures and a plurality of target areas in the substrate, wherein the target areas are arranged on two sides of the grid structures;
forming a dielectric layer on the surface of the substrate;
forming a patterned photoresist layer on the dielectric layer, the patterned photoresist layer having a plurality of first openings, one of the first openings being aligned with one of the target regions;
etching the dielectric layer by taking the patterned photoresist layer as a mask so as to form a plurality of second openings in the dielectric layer;
removing the patterned photoresist layer; and the number of the first and second groups,
and etching part of the depth of the substrate along the bottoms of the second openings to form a plurality of third openings, wherein one second opening is communicated with one third opening to form a first connecting through hole.
Optionally, after etching a partial depth of the substrate along the bottom of the second opening to form a plurality of third openings, the method further includes:
and carrying out ion implantation on the target region to form a source region.
Optionally, after performing ion implantation on the target region to form the source region, the method further includes:
and carrying out ion implantation on the back surface of the substrate to form a drain region.
Optionally, the type of the implanted ions of the source region and the drain region is both N-type or both P-type.
Optionally, after performing ion implantation on the target region to form the source region, the method further includes:
and filling a conductive material in the first connecting through hole to form a source electrode electric connection piece.
Optionally, the power of the etching source end for etching the dielectric layer by using the patterned photoresist layer as a mask and etching the substrate along the bottom of the second opening by a partial depth is 1000W-1500W.
Optionally, the etching bias power of the part of the depth of the dielectric layer etched by using the patterned photoresist layer as a mask and the substrate etched along the bottom of the second opening are both 200W to 300W.
Optionally, the gate structure includes a gate polysilicon layer and a shield gate polysilicon layer, the patterned photoresist layer has a plurality of fourth openings, the fourth openings are aligned with the gate polysilicon layer, when a plurality of second openings are formed in the dielectric layer, the second openings are aligned with the target region, a plurality of fifth openings are also formed in the dielectric layer, the fifth openings are aligned with the gate polysilicon layer, and when the substrate is etched along the second openings to form third openings, the gate polysilicon layer is etched along the fifth openings to form second connecting through holes; and the number of the first and second groups,
and when the first connecting through hole is filled with the conductive material to form a source electrode electric connection, the second connecting through hole is also filled with the conductive material to form a gate electrode electric connection.
Optionally, the conductive material comprises one or more of tungsten, copper and aluminum.
Optionally, an anisotropic etching process is used to etch a part of the depth of the substrate along the bottom of the second opening to form a plurality of third openings.
In the preparation method of the semiconductor device, provided by the invention, a substrate is provided, a plurality of grid structures and a plurality of target areas are formed in the substrate, and the target areas are distributed on two sides of the grid structures; forming a dielectric layer on the surface of the substrate, and forming a patterned photoresist layer on the dielectric layer, wherein the patterned photoresist layer is provided with a plurality of first openings, and one first opening is aligned with one target area; then, etching the dielectric layer by taking the patterned photoresist layer as a mask so as to form a plurality of second openings in the dielectric layer; and after removing the patterned photoresist layer, etching partial depth of the substrate along the bottoms of the second openings to form a plurality of third openings, wherein one second opening is communicated with one third opening to form a first connecting through hole. When the third opening is formed by etching partial depth of the substrate, the patterned photoresist layer is removed in advance, so that the patterned photoresist layer is prevented from generating more polymers attached to the inner wall of the third opening, the polymers attached to the inner wall of the third opening are reduced, the size of the first connecting through hole can be increased, the resistance of the target area is reduced, and the electrical property of a semiconductor device is improved.
Drawings
Fig. 1 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 2A to 2F are schematic cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
wherein the reference numerals are:
10-a substrate; 20-a gate structure; 21-a gate polysilicon layer; 22-a shield gate polysilicon layer; 30-a target zone; 40-a dielectric layer; 50-a patterned photoresist layer; 51-a first opening; 52-fourth opening; 61-a second opening; 62-a third opening; 60-a first connecting via; 71-fifth opening; 72-sixth opening; 70-a second connecting via; 81-source region; 82-a drain region; 91-source electrical connection; 92-gate electrical connection.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Fig. 1 is a flowchart of a method for manufacturing a semiconductor device according to this embodiment. This embodiment provides a method for manufacturing a semiconductor device to improve the electrical performance of the device, please refer to fig. 1, which includes:
step S1: providing a substrate, and forming a plurality of grid structures and a plurality of target areas in the substrate, wherein the target areas are arranged on two sides of the grid structures;
step S2: forming a dielectric layer on the surface of the substrate;
step S3: forming a patterned photoresist layer on the dielectric layer, the patterned photoresist layer having a plurality of first openings, one of the first openings being aligned with one of the target regions;
step S4: etching the dielectric layer by taking the patterned photoresist layer as a mask so as to form a plurality of second openings in the dielectric layer;
step S5: removing the patterned photoresist layer; and the number of the first and second groups,
step S6: and etching part of the depth of the substrate along the bottoms of the second openings to form a plurality of third openings, wherein one second opening is communicated with one third opening to form a first connecting through hole.
Fig. 2A to 2F are schematic cross-sectional views illustrating corresponding steps of a method for manufacturing a semiconductor device provided in this embodiment, and the method for manufacturing a semiconductor device provided in this embodiment is described in detail below with reference to fig. 2A to 2F.
Referring to fig. 2A, step S1 is executed: providing a substrate 10, forming a plurality of gate structures 20 and a plurality of target regions 30 (only one gate structure 20 and two target regions 30 are shown in the figure) in the substrate 10, wherein the target regions 30 are arranged on two sides of the gate structures 20.
Specifically, the base 10 is provided, the material of the base 10 includes one or more of silicon, germanium, gallium, nitrogen or carbon, in this embodiment, the base 10 may include an epitaxial layer and a substrate, the epitaxial layer is grown on the substrate, the epitaxial layer has the same crystal structure as the substrate, the purity is higher, the lattice defects are fewer, the impurity type and concentration can also be controlled, and the plurality of gate structures 20 and the plurality of target regions 30 are formed in the epitaxial layer. A plurality of gate structures 20 and a plurality of target regions 30 are formed in the substrate 10, and the target regions 30 are arranged on two sides of the gate structures 20. In this embodiment, the semiconductor device is a shielded gate trench transistor, the manufacturing step of the gate structure in the shielded gate trench transistor is to form a gate trench (not shown in the figure) in the substrate 10, and then form the gate structure 20 in the gate trench, the gate structure 20 generally includes a gate polysilicon layer 21, a shielded gate polysilicon layer 22, a gate oxide layer, and a field oxide layer (not shown in the figure), and the specific structure in the gate structure 20 is not limited herein, and the semiconductor device may also be other types of devices.
Referring to fig. 2B, step S2 is executed: a dielectric layer 40 is formed on the surface of the substrate 10.
Specifically, the dielectric layer 40 is formed on the surface of the substrate 10, the dielectric layer 40 further covers the gate structure 20, the material of the dielectric layer 40 may be an oxide or a nitride, and a subsequent process forms an electrical connection member in the dielectric layer 40.
Referring to fig. 2B, step S3 is executed: a patterned photoresist layer 50 is formed on the dielectric layer 40, the patterned photoresist layer 50 having a plurality of first openings 51, one of the first openings 51 being aligned with one of the target regions 30.
Specifically, a photoresist layer (not shown) is formed on the dielectric layer 40, and the photoresist layer is patterned to obtain the patterned photoresist layer 50, where the patterned photoresist layer 50 has a plurality of first openings 51, one first opening 51 may be aligned with one target region 30, and the width of the target region 30 is greater than the width of the first opening 51. In addition, the patterned photoresist layer 50 further has a fourth opening 52, and the fourth opening 52 is aligned with the gate structure 20, and particularly, the fourth opening 52 and the gate polysilicon layer 21 may be aligned in the center. Since the semiconductor device in this embodiment is a shielded gate trench transistor, when the gate polysilicon layer 21 in one of the gate structures 20 shown in the figure is connected to a gate metal layer as a gate in a subsequent process, the shielded gate polysilicon layer 22 in one of the gate structures 20 shown in the figure is not connected to other structures; when the gate polysilicon layer in the other gate structure, not shown, is not connected to the gate metal layer, the shield gate polysilicon layer in the gate structure may be connected to the source metal layer in the subsequent process, the patterned photoresist layer 50 may have an opening aligned with the shield gate polysilicon layer, and the subsequent process of forming a corresponding source electrical connector along with the source region may be synchronized to form an electrical connector connecting the source metal layer to the shield gate polysilicon layer. Since the purpose of this embodiment is to form the first connecting via corresponding to the target region 30, and the etching of a part of the structure in the gate structure 20 is only formed by a synchronous process, there is no limitation on the etching process of the gate polysilicon layer 21 or the shield gate polysilicon layer 22 in the gate structure 20.
Referring to fig. 2C, step S4 is executed: and etching the dielectric layer 40 by using the patterned photoresist layer 50 as a mask to form a plurality of second openings 61 in the dielectric layer 40.
Specifically, the dielectric layer 40 is etched by using an anisotropic etching process, specifically, the patterned photoresist layer 50 is used as a mask, the dielectric layer 40 is etched along the first opening 51, the dielectric layer 40 is etched on the dielectric layer 40 along the fourth opening 52, the substrate 10 is used as an etching stop layer, and when the etching is performed until the surface of the substrate 10 is exposed, the etching is stopped. After the etching is stopped, a plurality of second openings 61 aligned with the target region 30 are formed in the dielectric layer 40, and a plurality of fifth openings 71 aligned with the gate polysilicon layer 21 are also formed in the dielectric layer 40.
Referring to fig. 2C and 2D, step S5 is executed: the patterned photoresist layer 50 is removed.
Specifically, after the second opening 61 is formed, the patterned photoresist layer 50 is removed, and plasma generated in the etching process impacts the patterned photoresist layer 50 when the dielectric layer 40 is etched, so that the patterned photoresist layer 50 generates more polymers attached to the sidewall of the second opening 61. In order to avoid the subsequent etching process that the patterned photoresist layer 50 continues to produce more polymer, the patterned photoresist layer 50 is removed.
Referring to fig. 2D, step S6 is executed: a part of the depth of the substrate 10 is etched along the bottom of the second openings 61 to form a plurality of third openings 62, and one of the second openings 61 communicates with one of the third openings 62 and constitutes a first connection via 60.
Specifically, after the patterned photoresist layer is removed, due to the difference in material between the dielectric layer 40 and the substrate 10, by adjusting the etching selection ratio in the etching process and using an anisotropic etching process, a part of the depth of the substrate 10 is etched along the bottom of the second opening 61 to form a plurality of third openings 62, and the second opening 61 and the third openings 62 form a first connection via 60. After the patterned photoresist layer is removed, the substrate 10 is etched by a partial depth to form a plurality of third openings 62, so that the patterned photoresist layer is prevented from generating more polymers attached to the side walls of the third openings 62, the polymers attached to the side walls of the third openings 62 are reduced, and the width of the third openings 62 is increased.
While etching a partial depth of the substrate 10 along the bottom of the second opening 61 to form a plurality of third openings 62, simultaneously etching a partial depth of the gate polysilicon layer 21 along the fifth opening 71 to form a sixth opening 72, wherein the fifth opening 71 and the sixth opening 72 form a second connecting via 70. As shown in the figure, the top of the gate polysilicon layer 21 may be lower than the surface of the substrate 10, that is, the dielectric layer 40 is filled in the gate trench, so that the dielectric layer 40 and the gate polysilicon layer 21 are etched along the fifth opening 71 by a partial depth to form the sixth opening 72, and the sixth opening 72 penetrates through the dielectric layer 40; in addition, in other device structures, the top of the gate polysilicon layer 21 may also be flush with the surface of the substrate 10, i.e., a part of the depth of the gate polysilicon layer 21 is etched along the fifth opening 71 to form a sixth opening 72.
In this embodiment, when the patterned photoresist layer is used as a mask to etch the dielectric layer 40 and etch a part of the depth of the substrate 10 along the bottom of the second opening 61, the power of the etching source of the two etching processes may be 1000W to 1500W, and the power of the etching bias may be 200W to 300W, although the etching power of the etching process is relatively high, after the patterned photoresist layer is removed, no more polymer may be formed when etching the part of the depth of the substrate 10 along the bottom of the second opening 61, so as to prevent the width of the third opening 62 from being affected by the polymer to be reduced.
Referring to fig. 2E, further, ion implantation is performed on the target region to form a source region 81, since the width of the third opening 62 is increased, when ion implantation is performed, the diffusion width of the ion implantation is increased, the width of the source region 81 is increased, and since the width of the source region 81 is increased, the resistance of the source region 81 is decreased.
Further, after performing ion implantation on the target region to form the source region 81, the method further includes: ion implantation is performed on the back side of the substrate 10 to form a drain region 82. In this embodiment, the type of the implanted ions of the source region 81 and the drain region 82 is both N-type or both P-type.
Referring to fig. 2F, after the formation of the source region 81, when the first connecting via 60 is filled with a conductive material to form a source electrical connection 91, and the second connecting via 70 is filled with the conductive material to form a gate electrical connection 92, the conductive material includes one or more of tungsten, copper, and aluminum.
The gate polysilicon layer 21 in the gate structure 20 is connected to the gate metal layer later, a parasitic triode (not shown in the figure) is formed among the gate polysilicon layer 21, the source region 81 and the drain region 82, the base of the parasitic triode is connected to the source region 81, when the resistance of the source region 81 becomes small, the base voltage of the parasitic triode becomes small, the parasitic triode is less likely to be conducted, and therefore the electrical performance of the semiconductor device is improved.
In summary, in the method for manufacturing a semiconductor device provided by the present invention, a substrate is provided, and a plurality of gate structures and a plurality of target regions are formed in the substrate, wherein the target regions are arranged on two sides of the gate structures; forming a dielectric layer on the surface of the substrate, and forming a patterned photoresist layer on the dielectric layer, wherein the patterned photoresist layer is provided with a plurality of first openings, and one first opening is aligned with one target area; then, etching the dielectric layer by taking the patterned photoresist layer as a mask so as to form a plurality of second openings in the dielectric layer; and after removing the patterned photoresist layer, etching partial depth of the substrate along the bottoms of the second openings to form a plurality of third openings, wherein one second opening is communicated with one third opening to form a first connecting through hole. When the third opening is formed by etching partial depth of the substrate, the patterned photoresist layer is removed in advance, so that the patterned photoresist layer is prevented from generating more polymers attached to the inner wall of the third opening, the polymers attached to the inner wall of the third opening are reduced, the size of the first connecting through hole can be increased, the resistance of the target area is reduced, and the electrical property of a semiconductor device is improved.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A method of manufacturing a semiconductor device, comprising:
providing a substrate, and forming a plurality of grid structures and a plurality of target areas in the substrate, wherein the target areas are arranged on two sides of the grid structures;
forming a dielectric layer on the surface of the substrate;
forming a patterned photoresist layer on the dielectric layer, the patterned photoresist layer having a plurality of first openings, one of the first openings being aligned with one of the target regions;
etching the dielectric layer by taking the patterned photoresist layer as a mask so as to form a plurality of second openings in the dielectric layer;
removing the patterned photoresist layer; and the number of the first and second groups,
and etching part of the depth of the substrate along the bottoms of the second openings to form a plurality of third openings, wherein one second opening is communicated with one third opening to form a first connecting through hole.
2. The method for manufacturing a semiconductor device according to claim 1, further comprising, after etching a partial depth of the substrate along a bottom of the second opening to form third openings:
and carrying out ion implantation on the target region to form a source region.
3. The method for manufacturing a semiconductor device according to claim 2, further comprising, after the ion implantation of the target region to form the source region:
and carrying out ion implantation on the back surface of the substrate to form a drain region.
4. The method for manufacturing a semiconductor device according to claim 3, wherein the type of the implanted ions of the source region and the drain region is either both N-type or both P-type.
5. The method for manufacturing a semiconductor device according to claim 2, further comprising, after the ion implantation of the target region to form the source region:
and filling a conductive material in the first connecting through hole to form a source electrode electric connection piece.
6. The method for manufacturing a semiconductor device according to claim 1, wherein the power of an etching source end for etching the dielectric layer by using the patterned photoresist layer as a mask and etching the substrate along the bottom of the second opening by a partial depth is 1000W to 1500W.
7. The method for manufacturing a semiconductor device according to claim 1 or 6, wherein the etching bias power for etching the dielectric layer with the patterned photoresist layer as a mask and for etching the substrate along the bottom of the second opening by a partial depth is 200W to 300W.
8. The method according to claim 5, wherein the gate structure comprises a gate polysilicon layer and a shield gate polysilicon layer, the patterned photoresist layer has a plurality of fourth openings aligned with the gate polysilicon layer, when a plurality of second openings aligned with the target region are formed in the dielectric layer, a plurality of fifth openings aligned with the gate polysilicon layer are also formed in the dielectric layer, and when the substrate is etched along the second openings to form third openings, the gate polysilicon layer is etched along the fifth openings to form second connecting through holes; and the number of the first and second groups,
and when the first connecting through hole is filled with the conductive material to form a source electrode electric connection, the second connecting through hole is also filled with the conductive material to form a gate electrode electric connection.
9. The method for manufacturing a semiconductor device according to claim 5 or 8, wherein the conductive material includes one or more of tungsten, copper, and aluminum.
10. The method for manufacturing a semiconductor device according to claim 1, wherein an anisotropic etching process is used to etch a part of the depth of the substrate along the bottom of the second opening to form third openings.
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| US20070004214A1 (en) * | 2005-06-30 | 2007-01-04 | Matthias Schaller | Technique for reducing etch damage during the formation of vias and trenches in interlayer dielectrics |
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| CN112242305A (en) * | 2020-10-27 | 2021-01-19 | 上海华虹宏力半导体制造有限公司 | Semiconductor device and method for manufacturing the same |
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