CN109216465B - Floating gate type flash memory and manufacturing method thereof - Google Patents
Floating gate type flash memory and manufacturing method thereof Download PDFInfo
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- CN109216465B CN109216465B CN201811103347.3A CN201811103347A CN109216465B CN 109216465 B CN109216465 B CN 109216465B CN 201811103347 A CN201811103347 A CN 201811103347A CN 109216465 B CN109216465 B CN 109216465B
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
Abstract
The invention provides a floating gate type flash memory and a manufacturing method thereof, wherein the method comprises the following steps: providing a substrate; forming a first groove on a substrate; forming an isolation layer in the first groove; forming a floating gate in the first groove, and defining a second groove in the first groove by the floating gate; forming an interelectrode dielectric layer on the surface of the floating gate; forming a control gate in the second recess; an ion implantation process is performed to the top surface of the substrate to form a drain layer. The manufacturing method of the floating gate type flash memory improves the storage density of the floating gate memory device.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a floating gate type flash memory and a manufacturing method thereof.
Background
Floating gate flash memory generally includes a gate structure, a source region and a drain region formed on a substrate. For example, fig. 1 is a schematic cross-sectional view of a floating gate flash memory in the prior art, as shown in fig. 1, a source region 200 and a drain region 300 are formed on a surface of a substrate 100, and a gate structure 400 is formed above the surface of the substrate 100 and between the source region 200 and the drain region 300, so as to implement the writing and erasing functions of the device.
However, the large surface area of the floating gate type flash memory in the prior art affects the storage density of the floating gate memory device.
Disclosure of Invention
The invention aims to provide a floating gate type flash memory and a manufacturing method thereof, which aim to solve the problem that the storage density of a floating gate storage device is reduced due to the large surface area of the existing floating gate type flash memory.
In order to solve the above technical problem, the present invention provides a method for manufacturing a floating gate type flash memory, including:
providing a substrate, and sequentially forming an active pole layer and an active layer in the substrate from bottom to top;
forming a first groove on the substrate, wherein the first groove penetrates through the active layer and extends into the source layer;
forming an isolation layer in the first groove, wherein the top position of the isolation layer is lower than that of the first groove;
forming a floating gate in the first groove, wherein the floating gate is close to the inner side wall of the first groove, and a second groove is defined in the first groove by the floating gate;
forming an interelectrode dielectric layer on the surface of the floating gate;
forming a control gate in the second groove, the control gate being located on the inter-electrode dielectric layer to isolate the floating gate from the control gate by the inter-electrode dielectric layer;
performing an ion implantation process on a top surface of the active layer of the substrate to form a drain layer in the top surface of the active layer.
Optionally, the method for forming the floating gate includes:
filling a floating gate material layer in the first groove;
performing a back etching process to partially consume the floating gate material layer so that the top position of the floating gate material layer is lower than the top position of the first groove;
forming a side wall structure on the exposed inner side wall of the first groove, wherein the side wall structure covers the part, close to the inner side wall of the first groove, of the floating gate material layer; and the number of the first and second groups,
and etching the floating gate material layer by taking the side wall structure as a mask to form the floating gate.
Optionally, the method further includes forming a first gate dielectric layer on an inner sidewall of the first groove, and the floating gate covers the first gate dielectric layer.
Optionally, after the floating gate is formed, the method further includes forming a second gate dielectric layer on the inner sidewall exposed by the second groove, where the second gate dielectric layer is located on the first gate dielectric layer and is connected to the first gate dielectric layer.
Optionally, the method further includes: forming an inter-electrode dielectric layer, wherein the forming method of the inter-electrode dielectric layer and the second gate dielectric layer comprises the following steps:
and performing a thermal oxidation process to form a second gate dielectric layer on the exposed inner side wall of the second groove and form the inter-electrode dielectric layer on the surface of the floating gate.
Optionally, the method for forming the first groove on the substrate includes forming a mask layer on the surface of the substrate, the mask layer having an opening; etching the substrate by taking the mask layer as a mask to form the first groove corresponding to the opening, wherein the first groove is communicated with the opening;
and the forming method of the control gate comprises the following steps: filling a control gate material layer in the second groove, and filling the control gate material layer in the second groove and extending into the opening; and etching the control gate material layer by an etching process until the top position of the remaining control gate material layer is lower than the top position of the second groove to form the control gate.
Optionally, the method further includes: and etching the mask layer by performing an etching process.
Optionally, the depth of the first groove is between 3000 angstroms and 30000 angstroms.
Optionally, a plurality of memory cell regions are defined in the substrate, a trench isolation structure is formed between the plurality of memory cell regions, and the plurality of memory cell regions are arranged in an array.
Alternatively, the plurality of first recesses are connected to each other and extend in the row direction, and connect the plurality of floating gates to each other and extend in the row direction, and the plurality of control gates are connected to each other and extend in the row direction, in the plurality of memory cell regions arranged in the same row.
Further, in order to solve the above technical problem, the present invention also provides a floating gate type flash memory, including:
the semiconductor device comprises a substrate, a plurality of memory cell areas are defined in the substrate, an active electrode layer, an active layer and a drain electrode layer are sequentially formed in the substrate of the memory cell areas from bottom to top, a first groove is further formed in the substrate, and the first groove sequentially penetrates through the drain electrode layer and the active layer and extends into the source electrode layer;
the grid structure is formed in the first groove and comprises a floating grid, a control grid and an interelectrode dielectric layer positioned between the floating grid and the control grid, the floating grid is close to the inner side wall of the first groove, a second groove is defined in the first groove by the floating grid, and the control grid is filled in the second groove.
Optionally, the floating gate flash memory further includes: the first grid dielectric layer is formed between the floating grid and the inner side wall of the first groove;
and the second gate dielectric layer is formed between the control gate and the inner side wall of the second groove, is positioned on the first gate dielectric layer and is connected with the first gate dielectric layer.
Optionally, the top position of the control gate is lower than the top position of the second recess.
In summary, in the method for manufacturing the floating gate type flash memory according to the present invention, a first recess extending to a source layer is formed on a substrate including the source layer, a gate structure including a floating gate, an inter-electrode dielectric layer and a control gate is formed in the first recess, and a drain layer is formed on a top surface of the substrate, so as to form the floating gate type flash memory. Therefore, the substrate surface of the floating gate type flash memory provided by the invention only needs to form the drain layer, and compared with the prior art that the source region, the drain region and the gate structure are all formed on the surface layer of the substrate, the length of the substrate of the floating gate type flash memory provided by the invention is smaller, so that the occupied area of the floating gate type flash memory is smaller, and the floating gate type flash memory provided by the invention is accommodated in the same space, so that the storage density of the floating gate memory device is improved.
Drawings
FIG. 1 is a schematic cross-sectional view of a prior art floating gate flash memory;
FIG. 2 is a flow chart illustrating a method for fabricating a floating gate flash memory according to an embodiment of the present invention;
FIG. 3 is a flow chart illustrating a method for fabricating a floating gate flash memory according to another embodiment of the present invention;
FIGS. 4 to 14 are schematic cross-sectional views illustrating a floating gate flash memory according to an embodiment of the present invention during a manufacturing process thereof;
FIG. 15 is a top view of a floating gate flash memory according to an embodiment of the present invention;
fig. 16 is a top view of a prior art floating gate type flash memory.
Detailed Description
As described in the background art, the main reasons for the large surface area of the current floating gate flash memory are: for example, as shown in fig. 1, the drain region 300, the gate structure 400 and the source region 200 are laterally formed on the surface of the substrate 100 along the first direction X, so that the length of the substrate in the first direction X is relatively large, which results in a relatively large surface area of the floating gate flash memory and ultimately affects the storage density of the floating gate memory device.
In the prior art, in order to solve the technical problem, the lengths of the source region and the drain region in the first direction X are usually reduced, or the length of the channel is usually reduced, so that the source-drain breakdown voltage is often lower, or a short channel effect is caused, and the performance of the floating gate memory device is finally affected.
Therefore, the invention provides a floating gate type flash memory and a manufacturing method thereof, which can improve the storage density of a floating gate memory device and simultaneously can not influence the performance of the floating gate memory device.
The floating gate flash memory and the method for manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Fig. 2 is a flow chart illustrating a method for manufacturing a floating gate flash memory according to an embodiment of the present invention. As shown in fig. 2, the method includes:
in step 100a, a substrate is provided. The substrate comprises a source layer and an active layer which are sequentially formed from bottom to top.
In step 200a, a first recess is formed in the substrate, the first recess penetrating the active layer and extending into the source layer.
In summary, in the method for manufacturing the floating gate type flash memory according to the present invention, a first recess extending to a source layer is formed on a substrate including the source layer, a gate structure including a floating gate, an inter-electrode dielectric layer and a control gate is formed in the first recess, and a drain layer is formed on a top surface of the substrate, so as to form the floating gate type flash memory. Therefore, the drain layer, the gate structure and the source layer of the floating gate type flash memory provided by the invention are longitudinally formed in the substrate from top to bottom, that is, only the drain layer needs to be formed on the surface of the substrate, and compared with the prior art in which the source region, the drain region and the gate structure are formed on the surface layer of the substrate, the substrate of the floating gate type flash memory provided by the invention has a smaller transverse length, so that the floating gate type flash memory occupies a smaller area, and the floating gate type flash memory provided by the invention is accommodated in a larger number in the same space, thereby improving the storage density of the floating gate memory device.
Fig. 3 is a flow chart illustrating a method for manufacturing a floating gate flash memory according to another embodiment of the present invention. As shown in fig. 3, the method includes:
in step 100b, a substrate is provided.
Fig. 4 is a schematic structural diagram of a substrate according to an embodiment of the invention. As shown in fig. 4, an active layer 11 and an active layer 12 are sequentially formed in the substrate from bottom to top.
In step 200b, a first recess is formed in the substrate, wherein the first recess penetrates the active layer 12 and extends into the source layer 11.
In this embodiment, the first groove may be formed on the substrate by performing a photolithography process on the substrate.
Specifically, a mask layer is formed on the substrate, the mask layer has an opening, and the material of the mask layer may include silicon nitride or silicon oxide. And etching the substrate by taking the mask layer as a mask to form the first groove corresponding to the opening, wherein the first groove is communicated with the opening, and the depth of the first groove can be between 3000 angstroms and 30000 angstroms.
Further, fig. 5 is a schematic structural diagram of the substrate after the step 200b is performed, and as shown in fig. 5, a mask layer 13 is formed on the substrate, and the mask layer 13 further has an opening (not shown in fig. 5), and meanwhile, the substrate 11 further includes a first groove a formed by performing the step 200b, and the first groove a is further communicated with the opening.
And 300b, forming an isolation layer in the first groove.
Specifically, the isolation material layer may be first used to fill the first groove a, and then a dry etching process is performed to etch a portion of the isolation material layer to form the isolation layer. Wherein the top position of the isolation layer is lower than that of the first groove, and the height of the isolation layer can range from 150 angstroms to 500 angstroms. The material of the isolation layer may include silicon oxide.
Further, fig. 6 is a schematic structural diagram of the substrate after step 300b is performed, and as shown in fig. 6, an isolation layer 14 is formed in the first groove a of the substrate, and a top position of the isolation layer 14 is lower than a top position of the first groove a.
And step 400b, forming a first gate dielectric layer on the inner side wall of the first groove.
Further, fig. 7 is a schematic structural diagram of the substrate after the step 400b is performed, and as shown in fig. 7, a first gate dielectric layer 15 is formed on an inner sidewall of the first groove a, and the first gate dielectric layer 15 is located on the isolation layer 14. The material of the first gate dielectric layer 15 may include silicon oxide.
In step 500b, the first recess a shown in fig. 7 is filled with a floating gate material layer, wherein the material of the floating gate material layer may include polysilicon.
Fig. 8 is a schematic structural diagram of the floating gate type flash memory after step 600b is performed, as shown in fig. 8, the floating gate material layer 16 is formed on the isolation layer 14 of the first recess a of the substrate, and the top position of the floating gate material layer 16 is lower than the top position of the first recess a, wherein the height of the floating gate material layer 16 may be between 200 angstroms and 1000 angstroms, and the material of the floating gate material layer 16 may include polysilicon.
And 700b, forming a side wall structure on the exposed inner side wall of the first groove A, wherein the side wall structure covers the part, close to the inner side wall of the first groove, of the floating gate material layer.
Fig. 9 is a schematic structural diagram of the substrate after the step 700b is performed, and as can be seen from fig. 8 and 9, a sidewall structure 17 is formed on the inner sidewall exposed by the first groove a, and the sidewall structure 17 covers a portion of the floating gate material layer 16 close to the first groove a, where the material of the sidewall structure 17 may include silicon nitride or silicon nitride.
And 800b, etching the floating gate material layer by taking the side wall structure as a mask to form the floating gate.
Fig. 10 is a schematic structural diagram of the substrate after the step 800b is performed, and as can be seen from fig. 9 and 10, after the floating gate material layer 16 is etched by using the sidewall structure 17 as a mask, the floating gate 18 is formed in the first recess a.
And 900b, removing the side wall structure 17 and part of the first gate dielectric layer 15 by adopting a wet etching process. So that the upper surface of the remaining first gate dielectric layer 15 is flush with the upper surface of the floating gate 18.
Further, fig. 11 is a schematic structural diagram of the substrate after the step 900b is performed, and as shown in fig. 11, the upper surface of the floating gate 18 is flush with the upper surface of the remaining first gate dielectric layer 15.
At this time, the floating gate 18 also defines a second recess B in the first recess.
And 1000B, performing a thermal oxidation process, forming a second gate dielectric layer on the inner side wall exposed by the second groove B, and forming an inter-electrode dielectric layer on the surface of the floating gate. The second gate dielectric layer is located on the first gate dielectric layer and connected with the first gate dielectric layer, and the second gate dielectric layer and the inter-electrode dielectric layer can both be made of silicon oxide.
Further, fig. 12 is a schematic structural diagram of the substrate after the step 1000B is performed, and as shown in fig. 12, a second gate dielectric layer 19 is formed in the second recess B, and an inter-electrode dielectric layer 20 is formed on the exposed surface of the floating gate 18. The second gate dielectric layer 19 is located on the exposed inner sidewall of the second groove B, located on the first gate dielectric layer 15, and connected to the first gate dielectric layer 15.
In step 1100B, a control gate is formed in the second recess B, the control gate is located on the inter-electrode dielectric layer 20 to isolate the floating gate 18 from the control gate by using the inter-electrode dielectric layer 20, and a material of the control gate may include silicon oxide.
The method for forming the control gate in step 1100b may be: the second recess B is filled with a control gate material layer, and the control gate material layer fills the second recess B and extends into the opening of the mask layer in step 200B. And then, etching the control gate material layer by an etching process until the top position of the remaining control gate material layer is lower than the top position of the second groove to form the control gate. Thereafter, the mask layer 13 may be etched away using an etching process.
Fig. 13 is a schematic structural diagram of the substrate formed after the step 1100B is performed, and referring to fig. 12 and 13, the control gate 21 is formed on the inter-electrode dielectric layer 20 in the second recess B, and the top of the control gate 21 is lower than the top of the second recess, where the height of the control gate 21 may be between 1000 angstroms and 10000 angstroms, and the material of the control gate 21 may include polysilicon.
In step 1200b, an ion implantation process is performed on a top surface of the active layer of the substrate to form a drain layer in the top surface of the active layer.
Further, fig. 14 is a schematic structural diagram of the floating gate type flash memory formed after step 1200b is performed. As shown in fig. 14, a drain layer 22 is formed in the top surface of the active layer 12 of the substrate.
At this time, the floating gate 18, the interpoly dielectric layer 20, and the control gate 21 are formed in the first recess to form a gate structure, and a drain layer 22 and a source layer 11 are formed at upper and lower ends of the gate structure, respectively, thereby forming a vertical floating gate type flash memory.
In the floating gate type flash memory shown in fig. 14, when the drain layer provides hot carriers and a positive voltage is applied to the control gate, the control gate can pull the hot carriers into the floating gate through coupling, so as to implement writing of the device; when a higher negative voltage is applied to the control gate, the control gate pushes out electrons in the floating gate through coupling so as to erase the device.
Further, fig. 15 is a top view of the floating gate flash memory shown in fig. 14, as shown in fig. 15, a plurality of memory cell regions C are defined in the substrate, and the memory cell regions C may be arranged in an array, where the memory cell region C includes memory cells, the memory cells may be the floating gate flash memory shown in fig. 14, and a trench isolation structure D is formed between the memory cell regions C.
Further, in the plurality of memory cell regions C arranged in the same row, the plurality of first recesses are connected to each other and extend in the row direction, and connect the plurality of floating gates to each other and extend in the row direction, and the plurality of control gates are connected to each other and extend in the row direction.
Still further, fig. 15 also shows the relative sizes of the control gate 21, the contact window E, and the memory cell region C and the trench isolation structure D, and it can be known from the relative sizes shown in fig. 15 that the surface area of the floating gate type flash memory is 0.0156 square microns.
In addition, fig. 16 is a top view of the prior art floating gate type flash memory, and the relevant dimensions of the floating gate type flash memory are shown in fig. 16, and it can be understood from fig. 16 that the surface area of the prior art floating gate type flash memory is generally 0.0289 square microns.
In comparison, the floating gate type flash memory manufactured by the method provided by the invention has smaller surface area and correspondingly smaller occupied area, so that more floating gate type flash memories provided by the invention can be accommodated in the same space, thereby improving the storage density of the floating gate memory device.
Further, the present invention also provides a floating gate type flash memory, which may be as shown in fig. 14 and 15, and includes:
a substrate 11, where a plurality of memory cell areas C are defined in the substrate 11, an active electrode layer 11, an active layer 12, and a drain electrode layer 22 are sequentially formed in the substrate of the memory cell area C from bottom to top, and a first groove a (not shown in fig. 14 and 15, see fig. 5 in particular) is further formed in the substrate, and the first groove a sequentially penetrates through the drain electrode layer 22 and the active layer 12 and extends into the source electrode layer 11.
And a gate structure formed in the first recess a and including a floating gate 18, a control gate 21, and an inter-electrode dielectric layer 20 (not shown in fig. 14 and 15, and refer to fig. 12 in particular) between the floating gate 18 and the control gate 21, wherein the floating gate 18 is close to an inner sidewall of the first recess a and defines a second recess B (not shown in fig. 14 and 15, and refer to fig. 12 in particular) in the first recess a by the floating gate 18, the control gate 21 is filled in the second recess B, and a top position of the control gate 21 is lower than a top position of the second recess B.
Optionally, the floating gate flash memory further includes: a first gate dielectric layer 15 formed between the floating gate 18 and the inner side wall of the first groove A;
and the second gate dielectric layer 19 is formed between the control gate 21 and the inner side wall of the second groove B, and the second gate dielectric layer 19 is positioned on the first gate dielectric layer 15 and is connected with the first gate dielectric layer 15.
In summary, the drain layer, the gate structure and the source layer of the floating gate flash memory provided by the present invention are longitudinally arranged from top to bottom in the substrate, and only the drain layer needs to be formed on the surface of the substrate, compared to the prior art in which the source region, the drain region and the gate structure are formed on the surface of the substrate, the length of the substrate of the floating gate flash memory provided by the present invention is smaller, so that the occupied area of the floating gate flash memory is smaller, and a larger number of floating gate flash memories provided by the present invention can be accommodated in the same space, thereby increasing the storage density of the floating gate memory device.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the system disclosed by the embodiment, the description is relatively simple because the system corresponds to the method disclosed by the embodiment, and the relevant points can be referred to the method part for description.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (12)
1. A method for manufacturing a floating gate type flash memory, the method comprising:
providing a substrate, and sequentially forming an active pole layer and an active layer in the substrate from bottom to top;
forming a first groove on the substrate, wherein the first groove penetrates through the active layer and extends into the source layer;
forming an isolation layer in the first groove, wherein the top position of the isolation layer is lower than that of the first groove;
forming a floating gate in the first groove, wherein the floating gate is close to the inner side wall of the first groove, and a second groove is defined in the first groove by the floating gate;
forming an interelectrode dielectric layer on the surface of the floating gate;
forming a control gate in the second groove, the control gate being located on the inter-electrode dielectric layer to isolate the floating gate from the control gate by the inter-electrode dielectric layer;
performing an ion implantation process on a top surface of the active layer of the substrate to form a drain layer in the top surface of the active layer;
the substrate is defined with a plurality of memory cell regions arranged in a plurality of memory cell regions in a same row, the first grooves are communicated with each other and extend along the row direction, the floating gates are connected with each other and extend along the row direction, and the control gates are connected with each other and extend along the row direction.
2. The method of manufacturing a floating gate type flash memory according to claim 1, wherein the method of forming the floating gate includes:
filling a floating gate material layer in the first groove;
performing a back etching process to partially consume the floating gate material layer so that the top position of the floating gate material layer is lower than the top position of the first groove;
forming a side wall structure on the exposed inner side wall of the first groove, wherein the side wall structure covers the part, close to the inner side wall of the first groove, of the floating gate material layer; and the number of the first and second groups,
and etching the floating gate material layer by taking the side wall structure as a mask to form the floating gate.
3. The method of claim 2, further comprising forming a first gate dielectric layer on inner sidewalls of the first recess, wherein the floating gate covers the first gate dielectric layer.
4. The method of claim 3, wherein after forming the floating gate, the method further comprises forming a second gate dielectric layer on the exposed inner sidewalls of the second recess, the second gate dielectric layer overlying and being connected to the first gate dielectric layer.
5. The method of manufacturing a floating gate type flash memory according to claim 4, further comprising: forming an inter-electrode dielectric layer, wherein the forming method of the inter-electrode dielectric layer and the second gate dielectric layer comprises the following steps:
and performing a thermal oxidation process to form a second gate dielectric layer on the exposed inner side wall of the second groove and form the inter-electrode dielectric layer on the surface of the floating gate.
6. The method of claim 1, wherein the step of forming the first recess in the substrate comprises forming a mask layer on the surface of the substrate, the mask layer having an opening; etching the substrate by taking the mask layer as a mask to form the first groove corresponding to the opening, wherein the first groove is communicated with the opening;
and the forming method of the control gate comprises the following steps: filling a control gate material layer in the second groove, and filling the control gate material layer in the second groove and extending into the opening; and etching the control gate material layer by an etching process until the top position of the remaining control gate material layer is lower than the top position of the second groove to form the control gate.
7. The method of manufacturing a floating gate type flash memory according to claim 6, further comprising: and etching the mask layer by performing an etching process.
8. The method of claim 1, wherein the depth of the first recess is between 3000 angstroms and 30000 angstroms.
9. The method of any of claims 1 to 8, wherein a trench isolation structure is formed between the plurality of memory cell regions, and the plurality of memory cell regions are arranged in an array.
10. A floating gate type flash memory, comprising:
the semiconductor device comprises a substrate, a plurality of memory cell areas are defined in the substrate, an active electrode layer, an active layer and a drain electrode layer are sequentially formed in the substrate of the memory cell areas from bottom to top, a first groove is further formed in the substrate, and the first groove sequentially penetrates through the drain electrode layer and the active layer and extends into the source electrode layer;
the grid structure is formed in the first groove and comprises a floating grid, a control grid and an interelectrode dielectric layer positioned between the floating grid and the control grid, the floating grid is close to the inner side wall of the first groove, a second groove is defined in the first groove by the floating grid, and the control grid is filled in the second groove;
the substrate is defined with a plurality of memory cell regions arranged in a plurality of memory cell regions in a same row, the first grooves are communicated with each other and extend along the row direction, the floating gates are connected with each other and extend along the row direction, and the control gates are connected with each other and extend along the row direction.
11. The floating gate type flash memory of claim 10, further comprising: the first grid dielectric layer is formed between the floating grid and the inner side wall of the first groove;
and the second gate dielectric layer is formed between the control gate and the inner side wall of the second groove, is positioned on the first gate dielectric layer and is connected with the first gate dielectric layer.
12. The floating gate type flash memory according to claim 10, wherein a top position of the control gate is lower than a top position of the second recess.
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| CN108447866A (en) * | 2018-03-06 | 2018-08-24 | 武汉新芯集成电路制造有限公司 | Floating-gate device and preparation method thereof |
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| US7511332B2 (en) * | 2005-08-29 | 2009-03-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Vertical flash memory |
| US9041092B2 (en) * | 2012-09-07 | 2015-05-26 | Unisantis Electronics Singapore Pte. Ltd. | Semiconductor device and method for producing the same |
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