KR100733228B1 - Semiconductor device and method for fabricating the same - Google Patents

Abstract

A semiconductor device and its manufacturing method are provided to reduce the leakage current of a bit line and to improve refresh characteristics of the device by acquiring a nonuniform thickness from a gate insulating layer using an additional oxide layer formed at a sidewall of a recess channel region. A semiconductor device includes a semiconductor substrate(110) with an isolation layer(120) for defining an active region, a recess channel region, a gate insulating layer and a gate electrode. The recess channel region is formed within the active region. The recess channel region includes a vertical channel region and a horizontal channel region. The gate insulating layer(160) is formed on the active region including the recess channel region. The thickness of the gate insulating layer is different corresponding to the vertical channel region, the horizontal channel region and the active region. The gate electrode(197) is formed on the gate insulating layer in the recess channel region.

Description

Semiconductor device and manufacturing method therefor {SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME}

1 is a layout of a semiconductor device according to the prior art.

2A to 2G are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the prior art.

3 is a layout of a semiconductor device in accordance with an embodiment of the present invention.

4 is a cross-sectional view of a semiconductor device in accordance with an embodiment of the present invention.

5A through 5H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, an oxide film is further formed on sidewalls of a recess channel region, thereby forming a gate insulating layer on the vertical channel region, the horizontal channel region, and the upper region of the recess channel region in the longitudinal direction of the active region. The present invention relates to a semiconductor device and a method of manufacturing the same, which can reduce the bit line leakage current and improve the refresh characteristics of the device by designing the semiconductor device so as to form different thicknesses of the semiconductor device.

In general, as the channel length of the cell transistor decreases, the ion concentration of the cell channel is increased to meet the threshold voltage of the cell transistor, and as a result, the electric field of the S / D region is increased to increase the leakage current. Falls out. Therefore, the following semiconductor device structure has been proposed in order to increase the channel length of the cell transistor.

1 is a layout of a semiconductor device showing an active region 1, a recess gate region 3 and a gate region 5 according to the prior art.

Referring to FIG. 1, the line width of the recess gate region 3 is shown as 2D narrower than the line width of the gate region 5, and the width between the gate regions 5 is shown as F.

2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art, and FIGS. 2A to 2G are cross-sectional views taken along line II ′ of FIG. 1, and FIGS. 2A to 2G. (ii) is sectional drawing along II-II 'of FIG.

Referring to FIG. 2A, the device isolation layer 20 is formed on the semiconductor substrate 10 including the pad oxide layer 13 and the pad nitride layer 15.

Referring to FIG. 2B, after the pad nitride layer 15 is removed, ions are implanted into the entire surface to form wells and channel ion implantation regions (not shown) in the semiconductor substrate 10. Next, a planarized polysilicon layer 25 is formed over the entire surface.

Referring to FIG. 2C, the polysilicon layer pattern defining the recess gate region 3 of FIG. 1 by etching the polysilicon layer 25 and the pad oxide layer 13 using a recess gate mask (not shown) as an etch mask. 25a and the pad oxide film pattern 13a are formed.

Referring to FIG. 2D, the semiconductor substrate 10 of the recess gate region 3 of FIG. 1 is etched by a predetermined thickness to form the first recess 35. At this time, when the first recess 35 is formed, the polysilicon layer pattern 25a is also removed. In addition, since the etching rate of the semiconductor substrate 10 adjacent to the isolation layer 20 is relatively slow, a silicon horn is formed.

Referring to FIG. 2E, the spacer 40 of the CVD oxide layer is formed on the sidewalls of the first recess 35 and the pad oxide pattern 13a, and then exposed to the lower portion of the first recess 35 using an etching mask. The second substrate 50 is formed by etching the semiconductor substrate 10 by a predetermined thickness.

Referring to FIG. 2F, after removing the spacer 40 and the pad oxide layer pattern 13a, a gate insulating layer 60 is formed on the exposed semiconductor substrate 10. Next, a planarized gate conductive layer 65 filling the second recess 50 is formed, and a hard mask layer 90 is formed thereon. Here, the gate conductive layer 65 is formed in a stacked structure of the lower gate conductive layer 70 and the upper gate conductive layer 80.

Referring to FIG. 2G, the gate 99 is formed by patterning the hard mask layer 90 and the gate conductive layer 65 using a gate mask (not shown) as an etch mask. Here, the gate channel L1 + L2 + L3 under the storage electrode junction region 5 formed in a subsequent process includes the vertical channel regions L1 and L3 and the horizontal channel region L2.

Subsequent processes perform a general transistor manufacturing process to complete a semiconductor device.

However, the above-described method of manufacturing a semiconductor device exposes the semiconductor substrate 10 at the upper corner of the first recess 35 when the spacer 40 is formed on the sidewall of the first recess 35. In this case, the exposed semiconductor substrate 10 is etched during an etching process for forming a subsequent recess channel region to cause cell transistor failure. In addition, since the thickness of the gate insulating layer is the same in the recess channel region and the active region, high ions must be implanted into the bit line junction region for the threshold voltage. However, this high concentration of ion implantation increases the electric field in the bit line junction region, causing an increase in bit line leakage current. In addition, the high concentration of the bit line junction region is limited in increasing the ion implantation concentration of the storage electrode junction region, thereby improving the refresh characteristics of the device.

The present invention has been made to solve the above problems, and in particular, an oxide film is further formed on the sidewalls of the recess channel region so that the gate is formed on the vertical channel region, the vertical channel region, and the upper portion of the active region in the longitudinal direction of the active region. By designing a semiconductor device to form a different thickness of the insulating film, to provide a semiconductor device and a method for manufacturing the semiconductor device that can reduce the bit line leakage current and improve the refresh characteristics of the device by maintaining a low doping concentration of the bit line junction region have.

The present invention is to achieve the above object, the semiconductor device according to the present invention,
A semiconductor substrate having a device isolation layer defining an active region, a recess channel region formed in the active region, the recess channel region including a vertical channel region and a horizontal channel region, and an upper region of the active region including a recess channel region, And a gate insulating layer formed on the vertical channel region, the horizontal channel region, and the active region, respectively, and having a different thickness, and a gate electrode filling the recess channel region and formed on the gate insulating layer of the gate region.

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Moreover, the manufacturing method of the semiconductor element which concerns on this invention is

(a) forming an isolation layer over the semiconductor substrate with the pad insulating film, (b) etching the pad insulating film to a predetermined thickness, and then forming a hard mask layer over the entire surface; and (c) the recess. Etching the hard mask layer and the semiconductor substrate using a gate mask to form a recess; (d) forming a first oxide film on the sidewall of the recess, and then etching the semiconductor substrate below the recess by a predetermined thickness to form a recess. Forming a recess channel region comprising a channel region and a vertical channel region, and (e) forming a gate insulating film over the exposed semiconductor substrate including the recess channel region, the horizontal channel region, the vertical channel region and the semiconductor Forming a gate insulating film having a different thickness on the substrate, (f) forming a planarized gate conductive layer filling the recess channel region, and (g) a gate diagram. Characterized in that it comprises the step and, (h) the step of using the gate mask as an etch mask for patterning the gate hard mask layer and the gate conductive layer to form a gate forming the gate hard mask layer on the upper layer.

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

3 is a layout of a semiconductor device illustrating an active region 101, a recess gate region 103, and a gate region 105 defined by an isolation layer 120, according to an exemplary embodiment.

Referring to FIG. 3, the line width of the recess gate region 103 is shown to be 2D narrower than the line width of the gate region 105, and the width between the gate regions 105 is shown as F.

4 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept, FIG. 4 (i) is a cross-sectional view taken along line II ′ of FIG. 3, and FIG. 4 (ii) is a cross-sectional view taken along line II-II ′ of FIG. It is a cross section.

Referring to FIG. 4, the isolation layer 120 defining the active region 101 of FIG. 3 is formed in the semiconductor substrate 110 and recessed by a mask defining the recess gate region 103 of FIG. 3. Channel region 155 is formed. In this case, the recess channel region 155 may be divided into a vertical channel region and a horizontal channel region in the longitudinal direction of the active region 101 of FIG. 3. Further, an additional oxide film is formed only in the vertical channel region of the recess channel region 155 to prevent the exposure of the semiconductor substrate 110 on the upper sidewall of the recess channel region 155.

The gate insulating layer 160 is formed on the active region including the recess channel region 155. In this case, the gate insulating layer 160 is formed to have a different thickness on the horizontal channel region, the vertical channel region and the active region of the recess channel region 155. Here, the thickness of the gate insulating layer 160 formed in the vertical channel region of the recess channel region 155 may be equal to or larger than the thickness of the gate insulating layer 160 formed on the active region 101 of FIG. 3. Meanwhile, the thickness of the gate insulating layer 160 formed in the vertical channel region of the recess channel region 155 may be smaller than the thickness of the gate insulating layer 160 formed on the active region 103 of FIG. 3. In this case, ion implantation of the bit line junction region 200 may be performed by differently forming the thickness of the horizontal channel region of the recess channel region 155, the vertical channel region thereof, and the gate insulating layer 160 on the active region 101 of FIG. 3. The concentration can be lowered to improve bit line junction characteristics and to improve device refresh characteristics.

In addition, the gate 199 is formed on the gate insulating layer 160 of the gate region 105 of FIG. 3. Here, the gate 199 is a stacked structure of the gate electrode 197 and the hard mask layer pattern 195, and the gate electrode 197 is a stacked structure of the gate lower electrode 175 and the gate upper electrode 185. Do.

5A to 5G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention. FIGS. 5A to 5G are cross-sectional views taken along line II ′ of FIG. 3, and FIG. ii) to 5g (ii) are cross-sectional views along II-II 'of FIG.

Referring to FIG. 5A, after the pad oxide layer 113 and the pad nitride layer 115 are formed on the semiconductor substrate 110, a photoresist layer (not shown) is formed on the pad nitride layer 115. Next, a photoresist film is exposed and developed with an element isolation mask to form a photoresist pattern (not shown) defining an element isolation region. Thereafter, a trench (not shown) defining the active region 103 of FIG. 3 is sequentially etched by sequentially etching the pad nitride layer 115, the pad oxide layer 113, and the semiconductor substrate 110 having a predetermined thickness using the photoresist pattern as an etching mask. After formation, the photosensitive film pattern is removed. Next, after forming an isolation layer (not shown) filling the trench, the isolation layer 120 is formed by planarizing etching of the isolation layer until the pad nitride layer 115 is exposed. Here, it is preferable to form a laminated structure of a thermal oxide film (not shown), a liner nitride film (not shown), and a liner oxide film (not shown) at an interface between the oxide film for isolation and the trench.

Referring to FIG. 5B, the device isolation layer 120 is etched by a predetermined thickness by a wet etching method to lower its height, and then the remaining pad nitride film 115 and the pad oxide layer 113 are removed by a wet etching method to remove the semiconductor substrate 110. To expose. Next, after forming the first oxide film 123 on the exposed semiconductor substrate 110, a photosensitive film (not shown) is applied over the entire surface. Thereafter, the photoresist layer is exposed and developed using a mask that exposes the cell region to form a photoresist pattern (not shown). Then, the photoresist pattern is implanted with an ion implantation mask to implant the well and channel ion implantation regions ( Not shown). Then, the photoresist pattern is removed. Thereafter, the planarized hard mask layer 125 is formed on the entire surface. Here, the removal process for the pad nitride film 115 and the pad oxide film 113 is performed by a wet etching method. The hard mask layer 125 may be formed of any one selected from the group consisting of a polysilicon layer, an amorphous carbon film, a CVD oxide film, a SiON film, and a combination thereof. A buffer oxide film may be added at the interface between the hard mask layer 125 and the pad oxide film 113.

Meanwhile, according to another exemplary embodiment, after the pad nitride layer 115 is removed by a wet etching method, wells and channel ion implantation regions (not shown) are formed in the semiconductor substrate 110 by implanting ions over the entire surface. Next, the pad oxide layer 113 may be removed by a wet etching method to expose the semiconductor substrate 110, and then the first oxide layer 123 may be formed on the exposed semiconductor substrate 110. A buffer oxide film (not shown) may be further formed between the first oxide film 123 and the hard mask layer 125.

Furthermore, after the pad nitride layer 115 is removed by a wet etching method, ions are implanted over the entire surface to form wells and channel ion implantation regions (not shown) in the semiconductor substrate 110. Next, after the sacrificial oxide film (not shown) is formed on the pad oxide film 113, the hard mask layer 125 may be formed on the entire surface.

5C and 5D, after the photoresist film (not shown) is formed on the hard mask layer 125, the recess gate of FIG. 3 is exposed and developed by using a recess gate mask (not shown) as an exposure mask. A photoresist pattern (not shown) defining the region 103 is formed. Next, the semiconductor substrate 110 of the recess gate region 103 is exposed by etching the hard mask layer 125 and the first oxide layer 123 in which the photoresist pattern is exposed as an etching mask, and then the exposed semiconductor substrate ( The first recess 135 is formed by etching 110 by a predetermined thickness. Thereafter, after the entire surface is cleaned, a second oxide film 133 is formed on the surface of the first recess 135 and on the remaining first oxide film 123. Next, a hard mask polysilicon layer 137 is formed over the entire surface. Here, during the etching process for forming the first recess 135, the photoresist pattern and the remaining hard mask layer 125 may be removed at the same time. In addition, it is preferable that the hard mask polysilicon layer 137 is not ion implanted. The second oxide film 133 is preferably formed of any one selected from the group consisting of a thermal oxide film, a deposited oxide film, and a combination thereof.

Referring to FIG. 5E, the hard mask polysilicon layer 137 is etched by a dry etching method to form spacers 145 on sidewalls of the first recess 135. Next, the exposed second oxide layer 133 is removed by a dry etching method to expose the semiconductor substrate 110 under the first recess 135.

Referring to FIG. 5F, the semiconductor substrate 110 exposed under the recess 135 is isotropically etched by a predetermined thickness to form a second recess 150 having an elliptical or circular shape in the longitudinal direction of the active region. Here, the spacer 145 may be removed at the same time during the etching process for forming the second recess 150.

Referring to FIG. 5G, after the cleaning process is performed on the entire surface, the remaining second oxide film 133 and the first oxide film 123 including the semiconductor substrate 110 exposed under the second recess 150 are disposed. On the surface of the gate insulating film 160 including the insulating film 153 is formed. Next, after forming the planarized lower gate conductive layer 170 filling the recess channel region 155 defined by the first recess 135 and the second recess 150, the lower gate conductive layer ( The upper gate conductive layer 180 and the gate hard mask layer 190 are formed on the upper portion 170. Here, the remaining second oxide film 133 and the first oxide film 123 are used as a part of the gate insulating film 160, so that the gate insulating film 160 is formed under the second recess 150 and the second recess 150. They are formed at different thicknesses on the sidewalls and on top of the active area, respectively. On the other hand, the gate insulating film 160 is preferably formed of any one selected from the group consisting of oxide film, nitride oxide film, Al ₂ O ₃ film and combinations thereof. The lower gate conductive layer 170 may be formed of any one selected from the group consisting of a polysilicon layer, a SiGe layer, and a combination thereof. The upper gate conductive layer 180 may include a titanium nitride film, a tungsten layer, and a combination thereof. It is preferable to form any one selected from the group consisting of.

Referring to FIG. 5H, a photoresist film (not shown) is coated on the gate hard mask layer 190, and then the photoresist film is exposed and developed with a gate mask (not shown) to define the gate region 105 of FIG. 3. A pattern (not shown) is formed. Next, the gate hard mask layer 190, the upper gate conductive layer 180, and the lower gate conductive layer 170 are etched using the photoresist pattern as an etch mask to form the gate hard mask layer pattern 195 and the upper gate electrode 185. And a gate 199 formed of a stacked structure of the lower gate electrode 175. After removing the photoresist pattern, the gate 199 is ion implanted with an ion implantation mask to form an LDD region (not shown) in the semiconductor substrate 110 between the gates 199. The lower gate conductive layer 170 may be formed of any one selected from the group consisting of a polysilicon layer, a SiGe layer, and a combination thereof, and the upper gate conductive layer 180 may include a titanium nitride film, a tungsten nitride film, and a tungsten polyside. It is preferable to form one selected from the group consisting of a layer, a titanium polyside layer, a titanium layer, a tungsten layer and a combination thereof.

Subsequent processes perform semiconductor transistor manufacturing processes such as gate sidewall insulating film formation, S / D region formation, contact plug formation, bit line contacts and bit line formation, capacitor contact and capacitor formation, metal wiring contacts and metal wiring formation. Complete the device.

As described above, the semiconductor device and the manufacturing method thereof according to the present invention further form an oxide film on the sidewalls of the recess channel region, thereby preventing exposure of the semiconductor substrate on the upper sidewalls of the recess channel region.

Further, by varying the thickness of the gate insulating layer in the vertical channel region of the recess channel region, the horizontal channel region and the upper portion of the active region in the longitudinal direction of the active region, the ion implantation concentration of the bit line junction region can be lowered, The electric field in the line junction area is reduced. Thus, leakage current in the bit line junction region can be reduced.

In addition, the ion implantation concentration of the storage electrode junction region can be lowered due to the ion implantation concentration of the low bit line junction region. Therefore, there is an advantage in that the refresh characteristics of the device can be improved.

In addition, the preferred embodiment of the present invention for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (21)

A semiconductor substrate having a device isolation film defining an active region; A recess channel region formed in the active region and including a vertical channel region and a horizontal channel region; A gate insulating layer formed over the active region including the recess channel region, the gate insulating layer having a different thickness on the vertical channel region, the horizontal channel region, and the active region; And And a gate electrode filling the recess channel region and formed on the gate insulating layer of the gate region. The method of claim 1, And a thickness of the gate insulating layer in the vertical channel region is equal to or larger than a thickness of the gate insulating layer on the active region. The method of claim 1, And a thickness of the gate insulating layer in the vertical channel region is smaller than a thickness of the gate insulating layer above the active region. (a) forming an isolation layer on the semiconductor substrate having a pad insulating film; (b) etching the pad insulating film to a predetermined thickness, and then forming a hard mask layer over the entire surface; (c) etching the hard mask layer and the semiconductor substrate by a recess gate mask to form a recess; forming a recess channel region including a horizontal channel region and a vertical channel region by forming a first oxide layer on a sidewall of the recess and then etching a semiconductor substrate below the recess by a predetermined thickness; (e) forming a gate insulating layer on the exposed semiconductor substrate including the recess channel region, and forming a gate insulating layer having a different thickness on the horizontal channel region, the vertical channel region, and the semiconductor substrate; (f) forming a planarized gate conductive layer filling the recess channel region; (g) forming a gate hard mask layer on the gate conductive layer; And (h) patterning the gate hard mask layer and the gate conductive layer by using a gate mask as an etch mask to form a gate Method of manufacturing a semiconductor device comprising a. The method of claim 4, wherein Step (a) is (a-1) forming a trench by etching a semiconductor substrate including a pad insulating film as a device isolation mask by a predetermined thickness; And (a-2) forming an isolation layer for filling the trench, and then forming an isolation layer by planarizing etching the isolation layer until the pad insulation layer is exposed Method of manufacturing a semiconductor device comprising a. The method of claim 5, And forming a stacked structure of a thermal oxide film, a liner nitride film and a liner oxide film at an interface between the trench and the device isolation insulating film. The method of claim 4, wherein Step (b) is (b-1) removing the pad nitride film by etching the pad insulating film having a stacked structure of a pad oxide film and a pad nitride film; (b-2) ion implanting the entire surface to form well and channel ion implantation regions in the semiconductor substrate; And (b-3) forming a hard mask layer over the entire surface Method of manufacturing a semiconductor device comprising a. The method of claim 7, wherein Step (b-2) Removing the pad oxide layer to expose the semiconductor substrate; Forming a second oxide layer on the exposed semiconductor substrate; And Ion implantation over the entire surface to form well and channel ion implantation regions in the semiconductor substrate Method of manufacturing a semiconductor device comprising a. The method of claim 7, wherein Step (b-2) Ion implanting the entire surface to form well and channel ion implantation regions in the semiconductor substrate; Removing the remaining pad oxide film to expose the semiconductor substrate; And Forming a second oxide layer on the exposed semiconductor substrate Method of manufacturing a semiconductor device comprising a. The method of claim 4, wherein The hard mask layer may be formed of any one selected from the group consisting of a polysilicon film, a CVD oxide film, an amorphous carbon film, an amorphous carbon film, a SiON film, and a combination thereof. The method of claim 4, wherein A buffer oxide film is further formed at an interface between the hard mask layer and the semiconductor substrate. The method of claim 4, wherein Step (c) is (c-1) forming a photoresist film on the hard mask layer; (c-2) exposing and developing the photoresist with a recess gate mask to form a photoresist pattern defining a recess gate region; (c-3) etching the hard mask layer using the photoresist pattern as an etch mask to expose a semiconductor substrate in the recess gate region; And (c-4) etching the exposed semiconductor substrate and the device isolation layer to form a recess, and simultaneously removing the photoresist pattern and the remaining hard mask layer. Method of manufacturing a semiconductor device comprising a. The method of claim 4, wherein Between the step (c) and the step (d), further comprising the step of cleaning the entire surface. The method of claim 4, wherein Step (d) (d-1) forming a first oxide film on a surface of the semiconductor substrate including the recess; (d-2) forming a hard mask polysilicon layer over the entire surface; (d-3) etching the hard mask polysilicon layer to form a spacer on a sidewall of the recess; (d-4) exposing the semiconductor substrate under the recess by removing the first oxide film exposing the spacer with an etch mask; And (d-5) forming a recess channel region in a length direction of the active region by etching a thickness of the semiconductor substrate exposed under the recess; Method of manufacturing a semiconductor device comprising a. The method of claim 14, The etching process for the hard mask polysilicon layer of step (d-3) is performed by a dry etching method. The method of claim 14, The removal process of the first oxide film of step (d-4) is performed by a dry etching method. The method of claim 14, The etching process for the semiconductor substrate of step (d-5) is performed by an isotropic etching method. The method of claim 14, The spacer is a method of manufacturing a semiconductor device, characterized in that during the etching process for the semiconductor substrate in the step (d-5) at the same time removed. The method of claim 4, wherein The gate insulating film is a semiconductor device manufacturing method, characterized in that formed by any one selected from the group consisting of oxide film, nitride oxide film, Al ₂ O ₃ film and combinations thereof. The method of claim 4, wherein In the step (e), the thickness of the gate insulating film formed in the vertical channel region is the same or larger than the thickness of the gate insulating film formed on the active region. The method of claim 4, wherein In the step (e), the thickness of the gate insulating film formed in the vertical channel region is smaller than the thickness of the gate insulating film formed on the active region.

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