CN114388629A - Split-gate flash memory unit and preparation method thereof - Google Patents
Split-gate flash memory unit and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 66
- 239000000463 material Substances 0.000 claims description 66
- 238000000034 method Methods 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 230000008878 coupling Effects 0.000 description 13
- 238000010168 coupling process Methods 0.000 description 13
- 238000005859 coupling reaction Methods 0.000 description 13
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000005549 size reduction Methods 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42336—Gate electrodes for transistors with a floating gate with one gate at least partly formed in a trench
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
Abstract
The invention provides a split-gate flash memory unit and a preparation method thereof, wherein the preparation method comprises the following steps: a substrate; a trench located within the substrate; the source line layer is positioned in the groove and divides the groove into two sub-grooves; the first floating gate and the second floating gate respectively fill the two sub-grooves and extend to cover part of the surface of the substrate, and the tops of the first floating gate and the second floating gate are higher than the source line layer; the erasing grid is positioned on the source line layer; the source region is positioned in the substrate below the source line layer and is electrically connected with the source line layer; the invention is beneficial to reducing the size of the split-gate flash memory unit.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a split-gate flash memory unit and a preparation method thereof.
Background
Flash memory, as a non-volatile memory, is used for storing data by controlling the switching of a gate channel by changing the threshold voltage of a transistor or a memory cell, so that the data stored in the memory is not lost due to power interruption, and as a special structure of an electrically erasable and programmable read only memory, flash memory has already occupied most of the market share of non-volatile semiconductor memory, and is the fastest-developing non-volatile semiconductor memory.
Fig. 1 is a cross-sectional view of a split gate flash memory cell. Referring to fig. 1, a certain width of the source region 10 'and the floating gate 20' are required to overlap laterally on the device structure as a coupling portion (shown in a dashed box) which is in a horizontal plane structure, and the coupling portion is used to ensure the coupling coefficient of the source region 10 'and the floating gate 20' to facilitate the programming of the split-gate flash memory cell. In order to ensure that the source region 10 'and the floating gate 20' have a certain width overlap in the lateral direction, the width of the floating gate cannot be too small, so that the size of the device structure is difficult to shrink.
Disclosure of Invention
The invention aims to provide a split-gate flash memory unit and a preparation method thereof, which are beneficial to reducing the size of the split-gate flash memory unit.
In order to achieve the above object, the present invention provides a split gate flash memory cell, including:
a substrate;
a trench located within the substrate;
the source line layer is positioned in the groove and divides the groove into two sub-grooves;
the first floating gate and the second floating gate respectively fill the two sub-grooves and extend to cover part of the surface of the substrate, and the tops of the first floating gate and the second floating gate are higher than the source line layer;
the erasing grid is positioned on the source line layer;
and the source region is positioned in the substrate below the source line layer and is electrically connected with the source line layer.
Optionally, the tips of the floating gates of the first floating gate and the second floating gate are disposed oppositely, and the erase gate extends to cover the tip of the floating gate.
Optionally, the first gate structure further includes a first sidewall, where the first sidewall is located on the first floating gate and covers one side of the erase gate; and/or the presence of a gas in the gas,
the second gate-splitting structure further comprises a second side wall, and the second side wall is located on the second floating gate and covers the other side of the erasing gate.
Optionally, the first split-gate structure further includes a third sidewall and a first word line gate, the third sidewall covers the first sidewall and a side of the first floating gate away from the erase gate, and the first word line gate covers at least a part of a surface of the third sidewall; and/or the presence of a gas in the gas,
the second grid-splitting structure further comprises a fourth side wall and a second word line grid, the fourth side wall covers the second side wall and one side, far away from the erasing grid, of the second floating grid, and the second word line grid covers at least part of the surface of the fourth side wall.
Optionally, the transistor further includes two drain regions respectively located in the substrate outside the first word line grid and the second word line grid.
Optionally, the material of the source line layer includes polysilicon.
A preparation method of a split-gate flash memory unit comprises the following steps:
providing a substrate, and forming a groove in the substrate; and the number of the first and second groups,
forming a source line layer in the groove, forming a first gate dividing structure and a second gate dividing structure part in the groove, forming an erasing gate on the source line layer, and forming a source region in the substrate below the source line layer;
wherein the source line layer divides the trench into two sub-trenches;
the first floating gate and the second floating gate respectively fill two sub-grooves and extend to cover part of the surface of the substrate, and the tops of the first floating gate and the second floating gate are higher than the source line layer;
the source region is electrically connected with the source line layer.
Optionally, the step of forming the first floating gate, the second floating gate, the source line layer, the erase gate, and the source region includes:
forming a floating gate material layer and a dielectric layer on the substrate in sequence, wherein the floating gate material layer fills the groove;
etching the dielectric layer to form a first opening, wherein the surface of the floating gate material layer is exposed out of the first opening, and the first opening is positioned above the substrate and a part of the groove;
etching the floating gate material layer to enable the first opening to extend into the floating gate material layer and the bottom of the side wall of the first opening to be arc-shaped;
filling a side wall material layer in the first opening;
etching and removing the dielectric layer and the floating gate material layer below the dielectric layer to form a second opening, wherein the second opening exposes the surface of the substrate at the bottom of the groove, and a floating gate tip is formed in the floating gate material layer after etching;
performing ion implantation on the substrate at the bottom of the groove to form a source region in the substrate;
filling and forming a source line layer in partial depth of the second opening;
removing part of the lateral width of the side wall material layer to expose the tip of the floating gate, and filling the residual depth of the second opening to form the erasing gate, wherein the erasing gate extends to cover the tip of the floating gate; and the number of the first and second groups,
the side wall material layer and the floating gate material layer are etched in sequence to expose the surface of the substrate, the remaining floating gate material layers on two sides of the second opening are respectively used as the first floating gate and the second floating gate, the remaining side wall material layers on the first floating gate form a first side wall, the remaining side wall material layers on the second floating gate form a second side wall, and the tips of the floating gates of the first floating gate and the second floating gate are opposite.
Optionally, after the first side wall and the second side wall are formed, the method further includes:
and forming a third side wall on one side of the first side wall and the first floating gate far away from the erasing gate, and forming a fourth side wall on one side of the second side wall and the second floating gate far away from the erasing gate.
Optionally, after forming the third side wall and the fourth side wall, the method further includes:
and forming a first grid on at least part of the surface of the third side wall, and forming a second grid on at least part of the surface of the fourth side wall.
Optionally, after forming the first word line gate and the second word line gate, the method further includes:
and respectively carrying out ion implantation on the substrates at the outer sides of the first word line grid and the second word line grid so as to form a drain region in the substrate.
In the split-gate flash memory unit and the preparation method thereof provided by the invention, the source line layer is positioned in the groove and divides the groove into two sub-grooves; the first floating gate and the second floating gate respectively fill the two sub-trenches and extend to cover part of the surface of the substrate, and the tops of the first floating gate and the second floating gate are higher than the source line layer; the erasing grid is positioned on the source line layer; the source region is located in the substrate below the source line layer and is electrically connected with the source line layer. According to the invention, the source line layer is positioned in the groove, the first floating gate and the second floating gate are respectively filled in the two sub-grooves, and the source line layer is electrically connected with the source region, so that the coupling part can be changed into a three-dimensional structure from a planar structure, the planar width of the first floating gate and the second floating gate can be reduced while the first floating gate, the second floating gate and the source region are ensured to have better coupling coefficients, and the size reduction of the split-gate flash memory unit is facilitated.
Drawings
FIG. 1 is a cross-sectional view of a split-gate flash memory cell;
fig. 2 is a flowchart of a method for manufacturing a split-gate flash memory cell according to an embodiment of the present invention;
fig. 3A to fig. 3M are schematic cross-sectional views illustrating corresponding steps in a method for manufacturing a split-gate flash memory cell according to an embodiment of the invention, wherein fig. 3M is a schematic cross-sectional view illustrating the split-gate flash memory cell according to an embodiment of the invention;
wherein the reference numerals are:
a 10' -source region; 20' -a floating gate; 10-a substrate; 11-a trench; 21-a first oxide layer; 22-a second oxide layer; 23-a third oxide layer; 30-a layer of floating gate material; 31-a first floating gate; 32-a second floating gate; 40-a dielectric layer; 51-a first opening; 52-a second opening; 60-side wall material layer; 61-a first side wall; 62-a second side wall; 63-a third side wall; 64-a fourth side wall; 71-a source region; 72-a drain region; 80-source line layer; 90-an erase gate; 110-a first word line grid; 120-second word line gate.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Fig. 3M is a schematic cross-sectional view of the split-gate flash memory cell provided in this embodiment. Referring to fig. 3M, the present embodiment provides a split-gate flash memory cell, including: the semiconductor device includes a substrate 10, a trench, a first gate structure, a second gate structure, a source line layer 80, an erase gate 90, and a source region 71, wherein the trench (not shown) is located in the substrate 10, and a material of the substrate 10 includes one or more of silicon, germanium, gallium, nitrogen, or carbon.
The source line layer 80 is located in the trench to divide the trench into two sub-trenches (not shown), and in this embodiment, the source line layer 80 is preferably made of polysilicon.
The first floating gate structure and the second floating gate structure respectively comprise a first floating gate 31 and a second floating gate 32, the first floating gate 31 and the second floating gate 32 respectively fill two sub-trenches and extend to cover part of the surface of the substrate 10, the tops of the first floating gate 31 and the second floating gate 32 are higher than the top of the source line layer 80, floating gate tips are arranged at the tops of the first floating gate 31 and the second floating gate 32, the floating gate tips of the first floating gate 31 and the second floating gate 32 are arranged oppositely, the floating gate tips can enhance the erasing performance of the device, the erasing current is improved, and the erasing voltage is reduced. Further, a first oxide layer 21 is formed between the first floating gate 31 and the second floating gate 32 and the side wall of the trench, and a second oxide layer 22 is formed between the source line layer 80 and the first floating gate 31 and the second floating gate 32.
The source region 71 is positioned in the substrate 10 below the source line layer 80, the source region 71 is electrically connected with the source line layer 80, the area of the source line layer 80, the first floating gate 31 and the second floating gate 32 opposite to each other is a coupling part of the source region 71, the first floating gate 31 and the second floating gate 32, the size of the coupling surface represents the coupling coefficient of the source region 71, the first floating gate 31 and the second floating gate 32, the coupling coefficient of the source region 71, the first floating gate 31 and the second floating gate 32 is larger, and the erasing efficiency is increased; and the coupling part is changed from a horizontal plane structure to a vertical three-dimensional structure, so that the planar widths of the first floating gate 31 and the second floating gate 32 can be reduced while the first floating gate 31, the second floating gate 32 and the source region 71 have better coupling coefficients, and the size reduction of the device is facilitated.
An erase gate 90 is located on source line layer 80, and erase gate 90 extends over the floating gate tip. Furthermore, the first split gate structure further includes a first sidewall 61, where the first sidewall 61 is located on the first floating gate 31 and covers one side of the erase gate 90; the second split-gate structure further includes a second sidewall 62, and the second sidewall 62 is located on the second floating gate 32 and covers the other side of the erase gate 90. In the present embodiment, a third oxide layer 23 is formed between the erase gate 90 and the first and second sidewalls 61 and 62, and the third oxide layer 23 is further located between the erase gate 90 and the tip of the floating gate.
Further, the first grid-splitting structure further includes a third sidewall 63 and a first word line grid 110, the third sidewall 63 covers the first sidewall 61 and a side of the first floating gate 31 away from the erase gate 90, and the first word line grid 110 covers at least a part of a surface of the third sidewall 63; the second gate-splitting structure further includes a fourth sidewall 64 and a second word line gate 120, the fourth sidewall 64 covers the second sidewall 62 and a side of the second floating gate 32 away from the erase gate 90, and the second word line gate 120 covers at least a portion of a surface of the fourth sidewall 64.
Further, two drain regions 72 are included in the substrate 10 outside the first word line gate 110 and the second word line gate 120, respectively.
In the present embodiment, a split-gate flash memory device can be formed by using a plurality of split-gate flash memory cells, and how the plurality of split-gate flash memory cells are arranged is not limited in this description.
Fig. 2 is a flowchart of a method for manufacturing a split-gate flash memory cell according to this embodiment. Referring to fig. 2, the present embodiment provides a method for manufacturing a split-gate flash memory cell, including:
step S1: providing a substrate, and forming a groove in the substrate; and the number of the first and second groups,
step S2: forming a source line layer in the groove, forming a first gate dividing structure and a second gate dividing structure part in the groove, forming an erasing gate on the source line layer, and forming a source region in the substrate below the source line layer;
the source line layer divides the groove into two sub-grooves;
the first floating gate and the second floating gate respectively fill the two sub-trenches and extend to cover part of the surface of the substrate, and the tops of the first floating gate and the second floating gate are higher than the source line layer;
the source region is electrically connected with the source line layer.
Fig. 3A to 3M are schematic cross-sectional views of corresponding steps in a method for manufacturing a split-gate flash memory cell provided in this embodiment, and the method for manufacturing a split-gate flash memory cell provided in this embodiment is described in detail with reference to fig. 3A to 3M.
Referring to fig. 3A, step S1 is executed: a substrate 10 is provided, the material of the substrate 10 comprising one or more of silicon, germanium, gallium, nitrogen or carbon, the substrate 10 is etched to form trenches 11 in the substrate 10.
Step S2 is executed: the steps of forming the first floating gate, the second floating gate, the source line layer, the erase gate and the source region include:
specifically, referring to fig. 3B, a first oxide layer 21 and a floating gate material layer 30 are sequentially formed on the substrate 10, the first oxide layer 21 covers the inner wall of the trench, and the floating gate material layer 30 fills the trench; the surface of the floating gate material layer 30 is flush by grinding, and the floating gate material layer 30 is made of polysilicon.
Referring to fig. 3C and fig. 3D, a dielectric layer 40 is formed on the floating gate material layer 30, and the material of the dielectric layer 40 may be silicon nitride; further, a first patterned photoresist layer (not shown in the figure) is formed on the dielectric layer 40, the dielectric layer 40 is etched by using the first patterned photoresist layer as a mask to form a plurality of first openings 51 in the dielectric layer 40, the surfaces of the floating gate material layer 30 are exposed out of the first openings 51, the width of the substrate 10 and the width of the trench are partially corresponding to the width of the floating gate material layer 30 under the first openings 51, and the remaining dielectric layer 40 is located right above the central region of the trench; and removing the first patterned photoresist layer.
Referring to fig. 3E, a portion of the floating gate material layer 30 is etched to remove the first opening 51 extending into the floating gate material layer 30, and the bottom of the sidewall of the first opening 51 is arc-shaped.
Referring to fig. 3F, the first opening 51 is filled with a sidewall material layer 60, and the surface of the sidewall material layer 60 is leveled by polishing, wherein the sidewall material layer 60 may be silicon oxide or silicon nitride.
Referring to fig. 3G, a second patterned photoresist layer (not shown) is formed on the sidewall material layer 60 and the dielectric layer 40, the floating gate material layer 30 directly under the dielectric layer 40 and the dielectric layer 40 is etched and removed by using the second patterned photoresist layer as a mask to form a second opening 52, and the surface of the first oxide layer 21 is exposed by the second opening 52; and removing the second patterned photoresist layer. After the second opening 52 is formed by etching, the top of the floating gate material layer 30 is in a sharp angle close to the second opening 52, and the sharp angle is a floating gate tip to form the floating gate tip, so that the erasing performance of the device can be enhanced, the erasing current can be increased, and the erasing voltage can be reduced.
Referring to fig. 3H, a second oxide layer 22 is formed on the inner wall of the second opening 52, and the first oxide layer 21 and the second oxide layer 22 at the bottom of the second opening 52 are removed to expose the surface of the substrate 10, that is, the second oxide layer 22 only covers the sidewall of the second opening 52, and the second opening 52 exposes the surface of the substrate 10; further, ion implantation is performed on the substrate 10 at the bottom of the second opening 52 to form a source region 71 in the substrate 10.
Referring to fig. 3I, the second opening 52 is filled with a source connection material layer (not shown), and the surface of the source connection material layer is leveled by grinding; furthermore, a third patterned photoresist layer (not shown) is formed on the sidewall material layer 60 and the source connection material layer, a portion of the source connection material layer in the second opening 52 is etched away by using the third patterned photoresist layer as a mask, the remaining source connection material layer is used as a source line layer 80, that is, the source line layer 80 fills a portion of the depth of the second opening 52, the top of the source line layer 80 is lower than the top of the floating gate material layer 30, and the source region 71 is electrically connected to the source line layer 80, wherein the material of the source line layer connection material layer is preferably polysilicon.
Referring to fig. 3J, a wet cleaning process is performed to remove a portion of the second oxide layer 22, specifically to remove the second oxide layer 22 not covered by the source line layer 80; a portion of the lateral width of the sidewall material layer 60 is simultaneously removed to expose the tip of the floating gate (shown in the dashed box), and the second opening 52 extends laterally into the sidewall material layer 60.
Referring to fig. 3K, a third oxide layer 23 is formed on the inner wall of the remaining depth of the second opening 52, and the third oxide layer 23 covers the tip of the floating gate; furthermore, an erase gate 90 is formed by filling the remaining depth of the second opening 52, the erase gate 90 extends to cover the tip of the floating gate, and the erase gate 90 is made of polysilicon.
Referring to fig. 3L, a fourth patterned photoresist layer (not shown) is formed on the sidewall material layer 60 and the erase gate 90, and the sidewall material layer 60 and the floating gate material layer 30 are sequentially etched using the fourth patterned photoresist layer as a mask, so that the etching process can be stopped at the first oxide layer 21, the first oxide layer 21 with at least a partial thickness is retained in the figure, or the first oxide layer 21 can be etched to remove the surface of the substrate 10 exposed by the first oxide layer 21; after etching, the remaining floating gate material layers on the two sides of the second opening are respectively used as the first floating gate 31 and the second floating gate 32, the remaining sidewall material layers on the first floating gate 31 form a first sidewall 61, the remaining sidewall material layers on the second floating gate 32 form a second sidewall 62, the tips of the floating gates of the first floating gate 31 and the second floating gate 32 are opposite, and the erasing gate 90 is located between the first sidewall 61 and the second sidewall 62 and on the source line layer 80.
Referring to fig. 3M, further, after forming the first side wall 61 and the second side wall 62, the method further includes: third sidewalls 63 are formed on the first sidewalls 61 and the sides of the first floating gates 31 away from the erase gates 90, and fourth sidewalls 64 are formed on the second sidewalls 62 and the sides of the second floating gates 32 away from the erase gates 90. Further, a first word line gate 110 is formed on at least a part of the surface of the third side wall 63, and a second word line gate 120 is formed on at least a part of the surface of the fourth side wall 64. The first floating gate 31, the first sidewall 61, the third sidewall 63 and the first word line grid 110 form a first grid splitting structure, the second floating gate 32, the second sidewall 62, the fourth sidewall 64 and the second word line grid 120 form a second grid splitting structure, and the first grid splitting structure and the second grid splitting structure are respectively located on two sides of the source line layer 80 and the erase grid 90.
With continued reference to fig. 3M, after forming the first word line gate 110 and the second word line gate 120, the method further includes: ion implantation is performed on the substrate 10 outside the first word line gate 110 and the second word line gate 120, respectively, to form two drain regions 72 in the substrate.
In summary, in the split-gate flash memory cell and the method for fabricating the same according to the present invention, the source line layer is located in the trench and divides the trench into two sub-trenches; the first floating gate and the second floating gate respectively fill the two sub-trenches and extend to cover part of the surface of the substrate, and the tops of the first floating gate and the second floating gate are higher than the source line layer; the erasing grid is positioned on the source line layer; the source region is located in the substrate below the source line layer and is electrically connected with the source line layer. According to the invention, the source line layer is positioned in the groove, the first floating gate and the second floating gate are respectively filled in the two sub-grooves, and the source line layer is electrically connected with the source region, so that the coupling part can be changed into a three-dimensional structure from a planar structure, the planar width of the first floating gate and the second floating gate can be reduced while the first floating gate, the second floating gate and the source region are ensured to have better coupling coefficients, and the size reduction of the split-gate flash memory unit is facilitated.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (11)
1. A split-gate flash memory cell, comprising:
a substrate;
a trench located within the substrate;
the source line layer is positioned in the groove and divides the groove into two sub-grooves;
the first floating gate and the second floating gate respectively fill the two sub-grooves and extend to cover part of the surface of the substrate, and the tops of the first floating gate and the second floating gate are higher than the source line layer;
the erasing grid is positioned on the source line layer;
and the source region is positioned in the substrate below the source line layer and is electrically connected with the source line layer.
2. The split-gate flash memory cell of claim 1 wherein the floating gate tips of the first floating gate and the second floating gate are disposed opposite to each other and the erase gate extends over the floating gate tips.
3. The split-gate flash memory cell of claim 1 wherein the first split-gate structure further comprises a first sidewall on the first floating gate and covering one side of the erase gate; and/or the presence of a gas in the gas,
the second gate-splitting structure further comprises a second side wall, and the second side wall is located on the second floating gate and covers the other side of the erasing gate.
4. The split-gate flash memory cell of claim 3 wherein the first split-gate structure further comprises a third sidewall and a first word line gate, the third sidewall covers the first sidewall and a side of the first floating gate away from the erase gate, the first word line gate covers at least a portion of a surface of the third sidewall; and/or the presence of a gas in the gas,
the second grid-splitting structure further comprises a fourth side wall and a second word line grid, the fourth side wall covers the second side wall and one side, far away from the erasing grid, of the second floating grid, and the second word line grid covers at least part of the surface of the fourth side wall.
5. The split-gate flash memory cell of claim 4 further comprising two drain regions in the substrate outside the first word line gate and the second word line gate, respectively.
6. The split-gate flash memory cell of claim 1 wherein the source line layer comprises polysilicon.
7. A method for preparing a split-gate flash memory unit is characterized by comprising the following steps:
providing a substrate, and forming a groove in the substrate; and the number of the first and second groups,
forming a source line layer in the groove, forming a first gate dividing structure and a second gate dividing structure part in the groove, forming an erasing gate on the source line layer, and forming a source region in the substrate below the source line layer;
wherein the source line layer divides the trench into two sub-trenches;
the first floating gate and the second floating gate respectively fill two sub-grooves and extend to cover part of the surface of the substrate, and the tops of the first floating gate and the second floating gate are higher than the source line layer;
the source region is electrically connected with the source line layer.
8. The method of manufacturing the split-gate flash memory cell of claim 7, wherein the step of forming the first floating gate, the second floating gate, the source line layer, the erase gate and the source region comprises:
forming a floating gate material layer and a dielectric layer on the substrate in sequence, wherein the floating gate material layer fills the groove;
etching the dielectric layer to form a first opening, wherein the surface of the floating gate material layer is exposed out of the first opening, and the first opening is positioned above the substrate and a part of the groove;
etching the floating gate material layer to enable the first opening to extend into the floating gate material layer and the bottom of the side wall of the first opening to be arc-shaped;
filling a side wall material layer in the first opening;
etching and removing the dielectric layer and the floating gate material layer below the dielectric layer to form a second opening, wherein the second opening exposes the surface of the substrate at the bottom of the groove, and a floating gate tip is formed in the floating gate material layer after etching;
performing ion implantation on the substrate at the bottom of the groove to form a source region in the substrate;
filling and forming a source line layer in partial depth of the second opening;
removing part of the lateral width of the side wall material layer to expose the tip of the floating gate, and filling the residual depth of the second opening to form the erasing gate, wherein the erasing gate extends to cover the tip of the floating gate; and the number of the first and second groups,
the side wall material layer and the floating gate material layer are etched in sequence to expose the surface of the substrate, the remaining floating gate material layers on two sides of the second opening are respectively used as the first floating gate and the second floating gate, the remaining side wall material layers on the first floating gate form a first side wall, the remaining side wall material layers on the second floating gate form a second side wall, and the tips of the floating gates of the first floating gate and the second floating gate are opposite.
9. The method for manufacturing a split-gate flash memory cell according to claim 8, wherein after forming the first sidewall and the second sidewall, the method further comprises:
and forming a third side wall on one side of the first side wall and the first floating gate far away from the erasing gate, and forming a fourth side wall on one side of the second side wall and the second floating gate far away from the erasing gate.
10. The method of claim 9, further comprising, after forming the third and fourth sidewalls:
and forming a first grid on at least part of the surface of the third side wall, and forming a second grid on at least part of the surface of the fourth side wall.
11. The method of manufacturing a split-gate flash memory cell according to claim 10, further comprising, after forming the first word line gate and the second word line gate:
and respectively carrying out ion implantation on the substrates at the outer sides of the first word line grid and the second word line grid so as to form a drain region in the substrate.
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| WO2023216369A1 (en) * | 2022-05-10 | 2023-11-16 | 北京知存科技有限公司 | Semiconductor device and manufacturing method therefor |
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