WO2023216369A1

WO2023216369A1 - Semiconductor device and manufacturing method therefor

Info

Publication number: WO2023216369A1
Application number: PCT/CN2022/099944
Authority: WO
Inventors: 王春明; 王绍迪
Original assignee: 北京知存科技有限公司
Priority date: 2022-05-10
Filing date: 2022-06-20
Publication date: 2023-11-16
Also published as: CN115000073A

Abstract

Provided are a semiconductor device and a manufacturing method therefor. The semiconductor device comprises: a substrate comprising a memory unit region, wherein the memory unit region comprises a first drain region, a first channel region and a source region, wherein the first channel region extends between the first drain region and the source region; a first floating gate located above a first portion of the first channel region; source polysilicon located above the source region; an erase gate located above the source polysilicon; a first select gate located above a second portion of the first channel region and on the side of the first floating gate opposite to the source polysilicon; a first programming channel extending from the first drain region to the edge portion of the first floating gate facing the first select gate; a second programming channel extending from the first drain region to the source region; and a first erase channel extending to the erase gate from the edge portion of the first floating gate facing the erase gate.

Description

Semiconductor device and manufacturing method thereof

Technical field

The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor device and a manufacturing method thereof.

Background technique

In electronic devices, memory is needed to read and store data. Therefore, as the demand for electronic devices continues to grow, so do the requirements for memory technology.

Flash memory is an electrically erasable and reprogrammable electrical non-volatile computer storage medium that retains on-chip information even after the power supply is turned off. Flash memory is easy to use, has both read and write flexibility and fast access speed, and has the characteristics of not losing information after power failure. Therefore, flash memory technology is developing very rapidly.

Flash memory includes an array of addressable memory cells, where each memory cell includes a floating gate transistor for storing corresponding information. Therefore, it is desirable to improve the performance and/or parameters of memory cells in flash memory to improve the overall performance and/or size of the flash memory.

Contents of the invention

According to some embodiments of the present disclosure, a semiconductor device is provided, including: a substrate including a memory cell region, wherein the memory cell region includes a first drain region, a first channel region, and a source region, wherein the A channel region extends between the first drain region and the source region; a first floating gate is located above a first portion of the first channel region; source polysilicon is located above the source region; an erase gate , located above the source polysilicon; a first select gate located over the second portion of the first channel region and on a side of the first floating gate opposite the source polysilicon; a first programming channel, located from the A drain region extends to an edge of the first floating gate facing the first selection gate; a second programming channel extends from the first drain region to the source region; and a first erase channel extends from the first drain region to the source region. An edge portion of a floating gate facing the erase gate extends to the erase gate.

According to some embodiments of the present disclosure, a method for manufacturing a semiconductor device is also provided, including: forming an oxide layer on a substrate; forming a floating gate layer on the oxide layer; forming Hard mask layer; etching the hard mask layer and the floating gate layer to form a first opening through the hard mask layer and the floating gate layer; forming a source in a region of the substrate below the first opening electrode region; remove the portion of the oxide layer over the source region and deposit polysilicon over the source region; etch the remaining portion of the hard mask layer to form a hard mask; etch the remaining portion of the floating gate layer and polysilicon to form the floating gate and source polysilicon; forming an erase gate over the source polysilicon; forming a select gate on the side of the floating gate opposite the source polysilicon; and A drain region is formed in the substrate on the side opposite the floating gate.

According to some embodiments of the present disclosure, a method for manufacturing a semiconductor device is also provided, including: forming an oxide layer on a substrate; forming a floating gate layer on the oxide layer; forming hard mask layer; etching the hard mask layer to form a first opening through the hard mask layer; forming stack spacers on both sides of the first opening; etching a portion of the floating gate layer located between the stack spacers to form a second opening through the stacked spacer and the floating gate layer; form a source region in a region of the substrate below the second opening; remove the portion of the oxide layer over the source region, and depositing polysilicon over the source region; etching the remainder of the hard mask layer; etching the remainder of the floating gate layer and the polysilicon to form the floating gate and source polysilicon; forming an eraser over the source polysilicon a gate; forming a select gate on a side of the floating gate opposite the source polysilicon; and forming a drain region in the substrate on a side of the select gate opposite the floating gate.

These and other aspects of the disclosure will be apparent from and elucidated with reference to the embodiments described hereinafter.

Description of the drawings

Further details, features and advantages of the present disclosure are disclosed in the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

1 is a schematic cross-sectional structural diagram of a semiconductor device according to some embodiments of the present disclosure;

2 is a circuit schematic diagram of a memory cell array according to some embodiments of the present disclosure;

Figure 3 is a top plan view of a memory cell array in accordance with some embodiments of the present disclosure;

Figure 4 is a schematic cross-sectional structural diagram of a semiconductor device according to some embodiments of the present disclosure;

Figure 5 is a schematic cross-sectional structural diagram of a semiconductor device according to some embodiments of the present disclosure;

Figure 6 is a circuit schematic diagram of a memory cell array according to some embodiments of the present disclosure;

7 is a top plan view of a memory cell array in accordance with some embodiments of the present disclosure;

Figure 8 is a schematic cross-sectional structural diagram of a semiconductor device according to some embodiments of the present disclosure;

Figure 9 is a schematic cross-sectional structural diagram of a semiconductor device according to some embodiments of the present disclosure;

Figure 10 is a schematic cross-sectional structural diagram of a semiconductor device according to some embodiments of the present disclosure;

Figure 11 is a schematic cross-sectional structural diagram of a semiconductor device according to some embodiments of the present disclosure;

Figure 12 is a schematic flowchart of a method of fabricating a semiconductor device according to some embodiments of the present disclosure;

13A-13H are schematic cross-sectional views of steps of a method of fabricating a semiconductor device according to some embodiments of the present disclosure;

14A-14M are schematic cross-sectional views of steps of a method of fabricating a semiconductor device according to some embodiments of the present disclosure;

15A-15O are schematic cross-sectional views of steps of a method of fabricating a semiconductor device according to some embodiments of the present disclosure;

Figure 16 is a schematic flowchart of a method of fabricating a semiconductor device according to some embodiments of the present disclosure;

17A-17E are schematic cross-sectional views of steps of a method of fabricating a semiconductor device according to some embodiments of the present disclosure;

18A-18E are schematic cross-sectional views of steps of a method of fabricating a semiconductor device according to some embodiments of the present disclosure.

Detailed ways

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or Sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.

Spatially relative terms such as "below", "below", "lower", "under", "above", "upper", etc. may be used herein for convenience. Description is used to describe the relationship of one element or feature to another element or feature(s) as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "under other elements or features" or "beneath other elements or features" would then be oriented "below" the other elements or features. characteristics”. Thus, the example terms "below" and "beneath" may encompass both an above and below orientation. Terms such as “before” or “before” and “after” or “following” may similarly be used, for example, to indicate the order in which light passes through elements. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Additionally, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprising" and/or "including" when used in this specification specify the presence of stated features, integers, steps, operations, elements and/or parts, but do not exclude the presence of one or more The presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items, and the phrase "at least one of A and B" means only A, only B, Or both A and B.

It will be understood that when an element or layer is referred to as being "on", "connected to", "coupled to" or "adjacent another element or layer" It can be directly on, directly connected to, directly coupled to, or directly adjacent another element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on another element or layer," "directly connected to another element or layer," "directly coupled to another element or layer," or "directly adjacent another element or layer" , no intermediate components or layers are present. However, in no event shall "on" or "directly on" be construed as requiring one layer to completely cover the underlying layer.

Embodiments of the present disclosure are described herein with reference to schematic illustrations (and intermediate structures) of idealized embodiments of the disclosure. Because of this, variations in the shapes illustrated may be expected, for example, as a result of manufacturing techniques and/or tolerances. Thus, embodiments of the present disclosure should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. Accordingly, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shapes of the regions of the device and are not intended to limit the scope of the present disclosure.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be construed to have meanings consistent with their meanings in the relevant art and/or in the context of this specification, and are not to be idealistic or overly Construed in a formal sense, unless expressly so defined herein.

As used herein, the term "substrate" may refer to a substrate of a diced wafer, or may refer to a substrate of an undiced wafer. Similarly, the terms chip and die may be used interchangeably unless such interchange would cause a conflict.

In the existing technology, memory cells in flash memory have problems such as low erasure efficiency and large device size. In order to solve the above problems, the present disclosure provides a semiconductor device, including: a substrate including a memory cell region, wherein the memory cell region includes a first drain region, a first channel region and a source region, wherein the first a channel region extending between a first drain region and a source region; a first floating gate located over a first portion of the first channel region; a source polysilicon located over the source region; an erase gate, located above the source polysilicon; a first select gate located over the second portion of the first channel region and on an opposite side of the first floating gate from the source polysilicon; a first programming channel from the first The drain region extends to an edge of the first floating gate facing the first selection gate; a second programming channel extends from the first drain region to the source region; and a first erase channel extends from the first An edge portion of the floating gate facing the erase gate extends to the erase gate.

FIG. 1 is a schematic cross-sectional structural diagram of a semiconductor device 100 according to some embodiments of the present disclosure.

As shown in FIG. 1 , the semiconductor device 100 includes a substrate 110 and

gate structures

121 a , 123 and 124 a and a source polysilicon 122 formed over the substrate. Wherein, the substrate 110 includes a memory cell region 110a, and the memory cell region 110a includes a first drain region 111a, a source region 112, and a first channel region 113a extending between the first drain region 111a and the source region 112. , the

gate structures

121a, 123 and 124a include a first floating gate 121a, an erase gate 123 and a first selection gate 124a.

Specifically, as shown in FIG. 1 , the source polysilicon 122 is located above the source region 112 , the erase gate 123 is located above the source polysilicon 122 , and the first floating gate 121a is located above the first portion of the first channel region 113a , the first select gate 124a is located over the second portion of the first channel region 113a and on the side of the first floating gate 121a opposite the source polysilicon 122.

According to some embodiments, source polysilicon 122 is electrically connected to source region 112 while first floating gate 121a, erase gate 123, first select gate 124a, and source polysilicon 122 are electrically isolated from each other. According to some embodiments, spacers (eg, oxide structures and/or or silicon nitride structure) to achieve electrical insulation effect.

According to some embodiments, both first floating gate 121a and first select gate 124a are electrically insulated from substrate 110. According to some embodiments, an oxide structure may be disposed between the first floating gate 121a and the first selection gate 124a and the substrate to achieve an electrical insulation effect. According to some embodiments, the oxide structure between the first floating gate 121a and the substrate 110 and the oxide structure between the first selection gate 124a and the substrate 110 may be set to different thicknesses to achieve desired performance.

As shown in FIG. 1 , the semiconductor device 100 includes a first programming channel 131 a , a second programming channel 131 b and an erase channel 132 a , wherein the first programming channel 131 a extends from the first drain region 111 a to the first floating gate 121 a Facing the edge of the first selection gate 124a, the second programming channel 131b extends from the first drain region 111a to the source region 112, and the first erase channel 132a erases from the edge of the first floating gate 121a. The edge portion of the except gate 123 extends to the erase gate 123 .

According to some embodiments, when performing a programming operation, a positive voltage (eg, 1V) higher than the threshold voltage is applied to the first select gate 124a, while the source terminal (ie, the source polysilicon 122 and the source region 112 ) and the erase gate 123 apply a positive voltage (for example, 4.5V) to provide a lateral strong electric field, and a negative current (for example, 2μA) is poured into the first drain region 111a. At this time, due to the electron source injection effect, A part of the hot electrons are injected into the first floating gate 121a through the first programming channel 131a, and a part of the hot electrons migrate to the source end through the second programming channel 131b.

According to some embodiments, when an erase operation is performed, a higher positive voltage (eg, 11V) is applied to the erase gate 123, and the first selection gate 124a, the first drain region 111a, the source Both the polysilicon 122 and the source region 112 are set to 0V. At this time, due to the FN (Fowler-Nordheim) tunneling effect, under the action of the voltage difference between the erase gate 123 and the first floating gate 121a, the Electrons in a floating gate 121a are pulled to erase gate 123.

According to some embodiments, when a read operation is performed, by applying a positive voltage (eg, 1.8V) to the first selection gate 124a, a lower positive voltage (eg, 0.6V) is applied to the first drain region 111a. V), and the erase gate 123, the source polysilicon 122 and the source region 112 are all set to 0V. At this time, the memory cell in the semiconductor device 100 is determined by the current value between the source terminal and the drain terminal. The state in which it is located.

In embodiments as described in the present disclosure, since the erase gate is disposed above the source polysilicon, the coupling area between the erase gate and the floating gate can be adjusted, thereby reducing the coupling area between the erase gate and the floating gate. The coupling voltage between the gates allows for a more efficient erase operation; and because the erase gate is placed above the source polysilicon, the requirements for the thickness of the floating gate can be reduced and the difficulty of the manufacturing process can be reduced .

Moreover, in embodiments as described in the present disclosure, since the source polysilicon is disposed above the source region in the substrate, electrical connections between the plurality of bit lines can be achieved through the source polysilicon (see below with reference to FIG. 3 described in more detail). Therefore, compared with the prior art solution that uses a source active area or a combination of tungsten plugs and metal lines to achieve electrical connections between multiple bit lines, the floating gates of adjacent memory cells in the memory cell array are shortened. The distance between the poles allows the size of the memory cell array to be reduced.

Figure 2 is a circuit schematic diagram of memory cell array 200 in accordance with some embodiments of the present disclosure. It should be understood that the numbers of memory cells, word lines, bit lines, source lines and erase lines in Figure 2 are only illustrative, and any of the above numbers can be adjusted according to actual application requirements to achieve greater or smaller memory cell arrays.

As shown in FIG. 2 , the memory cell array 200 includes a plurality of memory cells (eg, the memory cell 210 shown in FIG. 2 ), where each memory cell may be the semiconductor device 100 shown in FIG. 1 . According to some embodiments, each memory cell includes a selection transistor and a floating transistor connected in series. For example, the memory unit 210 in FIG. 2 includes a selection transistor 211 and a floating gate transistor 212, wherein a fixed address can be selected by the selection transistor 211. The memory cell operates while floating gate transistor 212 can store information.

According to some embodiments, each row of memory cells corresponds to a word line. For example, in Figure 2, the memory cells of the upper row correspond to the word line WLn-1, the memory cells of the lower row correspond to the word line WLn, and each The word lines are connected to the gates of the select transistors in corresponding memory cells. According to some embodiments, the memory cells of each column correspond to a bit line. For example, in FIG. 2, the memory cells of the left column correspond to the bit line BLn-1, the memory cells of the middle column correspond to the bit line BLn, and the memory cells of the right column correspond to the bit line BLn-1. The memory cells correspond to bit lines BLn+1, and each bit line is connected to the drain of the select transistor in the corresponding memory cell. According to some embodiments, two adjacent rows of memory cells correspond to one source line. For example, in Figure 2, the memory cells in the upper and lower rows correspond to the source line SL, and each source line is connected to the corresponding memory cell. source of the floating gate transistor. According to some embodiments, the source lines of all memory cells in each sector in the memory are electrically connected together.

According to some embodiments, the drain of the selection transistor in the memory unit corresponds to the first drain region 111a in the semiconductor device 100 shown in FIG. 1 , and the gate of the selection transistor in the memory unit corresponds to the semiconductor shown in FIG. 1 The first select gate 124a in the device 100, the floating gate of the floating transistor in the memory cell corresponds to the first floating gate 121a in the semiconductor device 100 shown in FIG. 1, the floating transistor in the memory cell. The source corresponds to the source terminal (ie, the source polysilicon 122 and the source region 112) in the semiconductor device 100 shown in FIG. 1 .

Figure 3 is a top plan view of a memory cell array 300 (eg, the memory cell array 200 shown in the circuit diagram of Figure 2) in accordance with some embodiments of the present disclosure. As shown in FIG. 3 , the memory cell array 300 includes a plurality of bit lines BLn-1, BLn and BLn+1, a plurality of word lines WLn-1 and WLn, a plurality of floating gates FG1-FG6, a source line SL and an eraser line. Except line EG.

According to some embodiments, the memory cells in each column correspond to the same bit line. For example, as shown in FIG. 3 , the two memory cells in the left column both correspond to the bit line BLn-1. It should be understood that, although not shown, the bit line structures of memory cells of the same column are electrically connected.

According to some embodiments, the memory cells in each row correspond to the same word line. For example, as shown in FIG. 3 , the three memory cells in the upper row all correspond to the word line WLn-1. According to some embodiments, as shown in Figure 3, each word line extends across multiple memory cells in the same row.

According to some embodiments, each memory cell has a corresponding floating gate. For example, as shown in Figure 3, the memory cell in the upper left corner has a corresponding floating gate FG1.

According to some embodiments, memory cells in adjacent rows correspond to the same source line and the same erase line. For example, as shown in FIG. 3 , six memory cells in the upper and lower rows all correspond to the source line SL and the erase line. Line EG. According to some embodiments, as shown in Figure 3, source lines SL and erase lines EG extend through adjacent rows of memory cells, where the source lines correspond to source polysilicon disposed above the substrate. It should be understood that although only a part of the source line SL is shown in FIG. 3 , in fact, the remaining part of the source line SL is blocked by the erasure line EG located above and, similar to the erasure line EG, extends through the upper and lower rows. six memory cells.

According to some embodiments, the semiconductor device of the present disclosure further includes: a first hard mask or a first stack spacer on an upper surface of the first floating gate.

FIG. 4 is a schematic cross-sectional structural diagram of a semiconductor device 400 according to some embodiments of the present disclosure. The same or similar reference numerals in Figures 4 and 1 indicate the same or similar structures.

According to some embodiments, in addition to having the features described with reference to the semiconductor device 100 in FIG. 1 , the semiconductor device 400 shown in FIG. 4 also has the following features: a first stack located on the upper surface of the first floating gate 121 a Structure 125a, the first stacked structure 125a may be a first hard mask or a first stacked spacer. According to some embodiments, the first stacked structure 125a is formed in a process of forming the first floating gate 121a, for example, as a mask for the floating gate layer.

According to some embodiments, the semiconductor device of the present disclosure further includes: a first control gate located above the first floating gate and a first hard mask located on an upper surface of the first control gate.

FIG. 5 is a schematic cross-sectional structural diagram of a semiconductor device 500 according to some embodiments of the present disclosure. The same or similar reference numerals in Figures 5 and 1 indicate the same or similar structures.

According to some embodiments, in addition to having the features described with reference to the semiconductor device 100 in FIG. 1 , the semiconductor device 500 shown in FIG. 5 also has the following features: a first control gate 125 a located on the first floating gate 121 a and a first hard mask 126a located on the first control gate 125a. According to some embodiments, during a programming operation, by applying a higher voltage (eg, 11V) to the first control gate 125a, a voltage is coupled to the first floating gate 121a to turn on the floating gate and provide a vertical Strong electric field in the direction, thereby improving programming efficiency. According to some embodiments, the first hard mask 126a is formed during the process of forming the first floating gate 121a, for example, as a mask for the floating gate layer.

In the semiconductor device 500 as shown in FIG. 5 , in addition to reducing the coupling voltage between the erase gate and the floating gate as described above, the erasing operation can be performed more efficiently and the load on the floating gate can be reduced. In addition to reducing the difficulty of the manufacturing process and reducing the size of the memory cell due to the thickness requirement, the coupling between the floating gate and the control gate is improved, thereby improving programming performance.

Figure 6 is a circuit schematic diagram of a memory cell array 600 in accordance with some embodiments of the present disclosure. It should be understood that the numbers of memory cells, word lines, bit lines, source lines and erase lines in Figure 6 are only illustrative, and any of the above numbers can be adjusted according to actual application requirements to achieve greater or smaller memory cell arrays. The same or similar reference numerals in Figures 6 and 2 indicate the same or similar structures.

According to some embodiments, in addition to having the features described with reference to the memory cell array 200 in Figure 2, the memory cell array 600 shown in Figure 6 also has the following features:

1) In the memory cell array 600, each row of memory cells corresponds to a control line. For example, in Figure 2, the memory cells in the upper row correspond to the control line CGn-1, and the memory cells in the lower row correspond to the control line CGn. , and each control line is connected to the gate of the floating transistor in the corresponding memory cell;

2) The control gate of the floating transistor in the memory cell corresponds to the first control gate 125a in the semiconductor device 500 shown in FIG. 5 .

Figure 7 is a top plan view of a memory cell array 700 (eg, the memory cell array 600 shown in the circuit diagram of Figure 6) in accordance with some embodiments of the present disclosure.

According to some embodiments, in addition to having the features described with reference to the memory cell array 300 in FIG. 3 , the memory cell array 700 shown in FIG. 7 also has the following features: the memory cells in each row correspond to the same control line, for example, as As shown in Figure 7, the three memory cells in the upper row all correspond to the control line CGn-1. According to some embodiments, as shown in Figure 7, each control line extends through multiple memory cells in the same row.

It should be understood that, although not shown in FIG. 7 , similar to FIG. 3 , each memory cell in FIG. 7 has a corresponding floating gate, where these floating gates are not shown in FIG. 7 because they are located below the control lines. out.

According to some embodiments, the semiconductor device of the present disclosure further includes: a first floating gate spacer between the first floating gate and the source polysilicon, and a lower surface of the erase gate and A tunnel oxide structure facing the side of the first floating gate.

According to some embodiments, a semiconductor device as described in the present disclosure further includes a first hard mask spacer between the first hard mask and the tunnel oxide structure.

According to some embodiments, the semiconductor device of the present disclosure further includes a second floating gate spacer between the first floating gate and the first selection gate.

According to some embodiments, the semiconductor device of the present disclosure further includes: a first substrate oxide structure between the first floating gate and the substrate, and a first select gate between the first select gate and the substrate. Second substrate oxide structure.

According to some embodiments, the first substrate oxide structure has a different thickness than the second substrate oxide to accommodate the requirements of different structures of the memory cell (eg, first floating gate and first select gate).

According to some embodiments, the first drain region further includes a lightly doped drain region and a heavily doped drain region, and the semiconductor device according to the present disclosure further includes: a first lightly doped drain spacer located at Above the first drain region and on the side of the first select gate opposite the first floating gate.

According to some other embodiments, the first drain region only includes a drain region of the same doping concentration, for example, a lightly doped drain process is not performed on the memory cell.

According to some embodiments, a semiconductor device as described in the present disclosure further includes a silicide structure over the first drain region, the first select gate, and the erase gate. In the embodiments described in the present disclosure, a silicide structure is provided above the first drain region, the first selection gate and the erase gate to facilitate subsequent extraction of electrodes to apply voltage to perform corresponding operations.

FIG. 8 is a schematic cross-sectional structural diagram of a semiconductor device 800 according to some embodiments of the present disclosure. The same or similar reference numerals in Figures 8 and 4 indicate the same or similar structures.

According to some embodiments, in addition to having the features described with reference to the semiconductor device 400 in FIG. 4 , the semiconductor device 800 shown in FIG. 8 also has the following features:

1) The semiconductor device 800 further includes: a first floating gate spacer 141a located between the first floating gate 121a and the source polysilicon 122, and a spacer formed on a lower surface of the erase gate 123 and facing the first Tunnel oxide structure 142 on the sides of floating gate 121a;

2) The semiconductor device 800 further includes: a first hard mask spacer 143 located between the first hard mask 125a and the tunnel oxide structure 142;

3) The semiconductor device 800 further includes: a second floating gate spacer 141b located between the first floating gate 121a and the first selection gate 124a;

4) The semiconductor device 800 further includes: a first substrate oxide structure 151 located between the first floating gate 121a and the substrate 110, and a second substrate oxide structure 151 located between the first selection gate 124a and the substrate 110. Bottom oxide structure 152;

5) In the semiconductor device 800, the first drain region 111a also includes a lightly doped drain region 1111a and a heavily doped drain region 1112a, and the semiconductor device 800 further includes: located above the first drain region 111a and on the first lightly doped drain spacer 144 on the side of the first select gate 124a opposite the first floating gate 121a;

6) The semiconductor device 800 further includes: silicide structures 161a-161c formed over the erase gate 123, the first selection gate 124a, and the first source region 111a respectively.

FIG. 9 is a schematic cross-sectional structural diagram of a semiconductor device 900 according to some embodiments of the present disclosure. The same or similar reference numerals in Figures 9 and 8 indicate the same or similar structures.

According to some embodiments, in addition to having the features described with reference to the semiconductor device 800 in FIG. 8 , the semiconductor device 900 shown in FIG. 9 also has the following features: the semiconductor device 900 includes a first hard mask for replacing the first hard mask in FIG. 8 and a first spacer 125a of a first hard mask spacer.

According to some embodiments, the semiconductor device of the present disclosure further includes: a first dielectric structure located on an upper surface of the first floating gate, wherein the first control gate is located on an upper surface of the first dielectric structure superior.

According to some embodiments, a semiconductor device as described in the present disclosure further includes a first control gate spacer formed on both sides of the first dielectric structure, the first control gate, and the first hard mask.

According to some embodiments, the first control gate spacer may be made of two layers of materials, such as oxide and silicon nitride. According to other embodiments, the first control gate spacer may be made of only one layer of material, such as oxide or silicon nitride.

FIG. 10 is a schematic cross-sectional structural diagram of a semiconductor device 1000 according to some embodiments of the present disclosure. The same or similar reference numerals in Figures 10 and 5 indicate the same or similar structures.

According to some embodiments, in addition to having the features described with reference to the semiconductor device 500 in FIG. 5 , the semiconductor device 1000 shown in FIG. 10 also has the following features:

1) The semiconductor device 1000 further includes a first dielectric structure 145 located on the upper surface of the first floating gate 121a, wherein the first control gate 125a is located on the upper surface of the first dielectric structure 145.

2) According to some embodiments, as shown in Figure 10, the semiconductor device 1000 further includes: control gates formed on both sides of the first dielectric structure 145, the first control gate 125a, and the first hard mask 126a.

Spacers

143a and 143b. According to some embodiments, the semiconductor device 1000 may include only the control gate spacer 143a formed on the side of the first dielectric structure 145, the first control gate 125a, and the first hard mask 126a facing the source polysilicon 122 .

3) The semiconductor device 1000 further includes: a first floating gate spacer 141a located between the first floating gate 121a and the source polysilicon 122, and a spacer formed on the lower surface of the erase gate 123 and facing the first Tunnel oxide structure 142 on the sides of floating gate 121a;

4) The semiconductor device 1000 further includes: a second floating gate spacer 141b located between the first floating gate 121a and the first selection gate 124a;

5) The semiconductor device 1000 further includes: a first substrate oxide structure 151 located between the first floating gate 121a and the substrate 110, and a second substrate oxide structure 151 located between the first selection gate 124a and the substrate 110. Bottom oxide structure 152;

6) In the semiconductor device 1000, the first drain region 111a further includes a lightly doped drain region 1111a and a heavily doped drain region 1112a, and the semiconductor device 1000 further includes: located above the first drain region 111a and on the first lightly doped drain spacer 144 on the side of the first select gate 124a opposite the first floating gate 121a;

7) The semiconductor device 1000 further includes: silicide structures 161a-161c respectively formed over the erase gate 123, the first selection gate 124a, and the first source region 111a.

According to some embodiments, the memory cell region further includes: a second drain region and a second channel region, wherein the second channel region extends between the second drain region and the source region; and as described in the present disclosure The semiconductor device further includes: a second floating gate located over the first portion of the second channel region; a second selection gate located over the second portion of the second channel region and on the second floating gate the side opposite to the source polysilicon; the third programming channel extends from the second drain region to the edge of the second floating gate facing the second selection gate; the fourth programming channel extends from the second drain region to the edge of the second floating gate facing the second selection gate; the electrode region extends to the source region; and a second erase channel extends from an edge portion of the second floating gate facing the second erase gate to the erase gate. In the semiconductor structure as described in the present disclosure, by symmetrically arranging a pair of gate structures (ie, a floating gate and a selection gate), a pair of memory cells (for example, two cells located in the same column in FIG. 2 Memory cells) can share erase gates, source polysilicon, and source regions, reducing the overall area and size of the memory cell array.

FIG. 11 is a schematic cross-sectional structural diagram of a semiconductor device 1100 according to some embodiments of the present disclosure. The same or similar reference numerals in Figures 11 and 1 indicate the same or similar structures.

According to some embodiments, in addition to having the features described with reference to the semiconductor device 100 in FIG. 1 , the semiconductor device 1100 shown in FIG. 11 also has the following features:

1) The memory cell region 110a further includes: a second drain region 111b arranged symmetrically with the first drain region 111a, and a second channel region 113b extending between the second drain region 111b and the source region 112.

2) The semiconductor device 1100 further includes: a second floating gate 121b disposed symmetrically with the first floating gate 121a and located above the first portion of the second channel region 113b; and a second floating gate 121b disposed symmetrically with the first selection gate 124a. The second select gate 124b is located over the second portion of the second channel region and on the side of the second floating gate 121b opposite the source polysilicon 122.

3) Similar to the semiconductor device 100 in FIG. 1 , the semiconductor device 1100 has a first programming channel 131 a and a second programming channel 131 b for performing a programming operation on the left memory cell, and a first programming channel 131 b for performing a programming operation on the left memory cell. a first erase channel 132a for an erase operation; and, the semiconductor device 1100 has a third programming channel 131c and a fourth programming channel 131d for performing a programming operation on the memory cell on the right side, and a third programming channel 131d for performing a programming operation on the memory cell on the right side. The second erase channel 132b performs the erase operation, wherein the third programming channel 131c extends from the second drain region 111b to the edge of the second floating gate 121b facing the second selection gate 124b, and the fourth The programming channel extends from the second drain region 111b to the source region 112, and the second erase channel 132b extends from an edge portion of the second floating gate 121b facing the second erase gate 121b to the erase gate 123 . According to some embodiments, the memory cells in the semiconductor device 1100 may be programmed, erased or read in a manner similar to that described above with reference to FIG. 1 .

According to other embodiments, similar to what is described with reference to FIG. 11 , other symmetrical gate structures, hard masks, and Spacers, oxide structures, and/or drain structures so that a pair of memory cells (e.g., two memory cells in the same column in Figure 2) can share the erase gate, source polysilicon, and source area, shrink The overall area and size of the memory cell array. For example, similar to FIG. 11 , the semiconductor structure may be configured as a symmetrical structure of the semiconductor structures in FIGS. 4-5 and 8-10 .

According to some embodiments, the semiconductor device of the present disclosure further includes: a second hard mask or a second stack spacer located on the upper surface of the second floating gate.

According to some embodiments, the semiconductor device of the present disclosure further includes: a second control gate located above the second floating gate, and a second hard mask located on an upper surface of the second control gate.

According to some embodiments, the substrate further includes a logic region, and a semiconductor device as described in the present disclosure further includes a logic device located over the logic region of the substrate. According to some embodiments, shallow trench isolation may be provided between the logic device and the memory cell to electrically isolate the logic device and the memory cell. According to some embodiments, logic devices include, but are not limited to, control devices and status reading devices that perform programming operations, erasing operations, or reading operations on memory cells.

The present disclosure provides a method for manufacturing a semiconductor device, which includes: forming an oxide layer on a substrate; forming a floating gate layer on the oxide layer; forming a hard mask layer on the floating gate layer; etching the hard mask layer. a mask layer and a floating gate layer to form a first opening through the hard mask layer and the floating gate layer; forming a source region in a region of the substrate below the first opening; in the source region Deposit polysilicon on top; etch the remainder of the hardmask layer to form the hardmask; etch the remainder of the floating gate layer and the polysilicon to form the floating gate and source polysilicon; form a wiper over the source polysilicon removing the gate; forming a select gate on a side of the floating gate opposite the source polysilicon; and forming a drain region in the substrate on a side of the select gate opposite the floating gate.

FIG. 12 is a schematic flowchart of a method 1200 of fabricating a semiconductor device according to some embodiments of the present disclosure.

At step S1201, an oxide layer is formed on the substrate.

According to some embodiments, the manufacturing method 1200 further includes: preforming shallow trench isolation in the substrate before forming an oxide layer on the substrate, for example, forming a memory cell array 300 on the substrate as shown in FIG. 3 Or bit line parallel shallow trench isolation in the memory cell array 700 shown in FIG. 7 . According to some embodiments, the manufacturing method 1200 further includes: pre-implanting a memory cell well in the substrate before forming an oxide layer on the substrate.

According to some embodiments, the process of forming shallow trench isolation may include, but is not limited to, the following steps: forming pad oxide, depositing silicon nitride, exposing active areas, etching shallow insulating trenches, filling shallow insulating trenches, shallow insulating Trench planarization, and silicon nitride removal.

According to some embodiments, an oxide layer is grown on the upper surface of the substrate.

At step S1202, a floating gate layer is formed on the oxide layer.

According to some embodiments, floating gate polysilicon is deposited on an upper surface of the oxide layer, and the floating gate polysilicon is planarized.

At step S1203, a hard mask layer is formed on the floating gate layer.

According to some embodiments, a hard mask material is deposited on the upper surface of the floating gate layer.

FIG. 13A shows a cross-sectional view of an exemplary structure formed after steps S1201-S1203. As shown in FIG. 13A , the semiconductor structure 1300 includes, from bottom to top, a substrate 110, an oxide layer 1301, a floating gate layer 1302, and a hard mask layer 1303.

At step S1204, the hard mask layer and the floating gate layer are etched to form a first opening through the hard mask layer and the floating gate layer.

According to some embodiments, before etching the hard mask layer and the floating gate layer, photoresist is coated on the hard mask layer, and a photolithography process is performed to form a photoresist pattern required for a subsequent etching process.

According to some embodiments, the hard mask layer is first etched, and hard mask spacers are formed on the sides on both sides of the opening of the hard mask layer, and then the floating gate layer is etched.

FIG. 13B shows a cross-sectional view of an exemplary structure formed after steps S1201 to S1204. As shown in FIG. 13B , the semiconductor structure 1300 also includes a first opening 1310 through the hard mask layer 1303 and the floating gate layer 1302 .

At step S1205, a source region is formed in a region of the substrate below the first opening.

According to some embodiments, a source implant process (eg, using arsenic or phosphorus) is performed to form a source region in a region of the substrate below the first opening.

FIG. 13C shows a cross-sectional view of an exemplary structure formed after steps S1201 to S1205. As shown in FIG. 13C , the semiconductor structure 1300 further includes a source region 112 located below the first opening 1310 .

At step S1206, a portion of the oxide layer on the source region is removed, and polysilicon is deposited on the source region.

According to some embodiments, after forming the source region, a portion of the oxide layer in the first opening located on the source region is cleaned.

According to some embodiments, polysilicon is deposited on the source region to fill the first opening through the hard mask layer, floating gate layer, and oxide layer, and the deposited polysilicon is planarized.

According to some embodiments, a floating gate oxide structure is formed on the sides of the first opening before polysilicon is deposited on the source region. According to some embodiments, a floating gate oxide is deposited in the first opening, and the deposited floating gate oxide is etched to form a floating gate oxide structure on sides of the first opening.

FIG. 13D shows a cross-sectional view of an exemplary structure formed after steps S1201 to S1206. As shown in FIG. 13D , semiconductor structure 1300 also includes polysilicon 1320 over source region 112 .

At step S1207, the remaining portion of the hard mask layer is etched to form a hard mask.

According to some embodiments, before etching the remaining portion of the hard mask layer, photoresist is coated on the hard mask layer and a photolithography process is performed to form a photoresist pattern required for a subsequent etching process.

FIG. 13E shows a cross-sectional view of an exemplary structure formed after steps S1201 to S1207. As shown in FIG. 13E, the semiconductor structure 1300 further includes first and second

hard masks

125a and 125b formed by etching the remaining portions of the hard mask layer.

At step S1208, the remaining portion of the floating gate layer and the polysilicon are etched to form floating gate and source polysilicon.

According to some embodiments, the remainder of the floating gate layer and the polysilicon may be etched in the same process step. According to other embodiments, the remaining portion of the floating gate layer and the polysilicon may be etched separately in different process steps.

According to some embodiments, when etching the polysilicon, the thickness of the etched polysilicon is adjusted so that the height of the source polysilicon is a desired value, thereby adjusting coupling between the source polysilicon and the subsequently formed floating gate.

According to some embodiments, a word line threshold voltage injection process may be performed before etching the remainder of the floating gate layer and polysilicon to improve the performance of a subsequently formed select gate.

FIG. 13F shows a cross-sectional view of an exemplary structure formed after steps S1201 to S1208. As shown in FIG. 13F , the semiconductor structure 1300 further includes a first floating gate 121 a , a second floating gate 121 b and a source polysilicon 122 formed by etching the remaining portions of the floating gate layer and the polysilicon.

At step S1209, an erase gate is formed over the source polysilicon.

According to some embodiments, before forming the erase gate over the source polysilicon, a portion of the floating gate oxide structure on the sides of the first opening is etched to form a gap between the floating gate and the source polysilicon. a first floating gate spacer; and forming a tunnel oxide structure on the sides of the first opening and on the upper surface of the source polysilicon.

According to some embodiments, the process of forming the erase gate may include, but is not limited to, the steps of depositing polysilicon, polysilicon planarization (with or without dummy poly), photolithography of the polysilicon, and etching the polysilicon.

At step S1210, a select gate is formed on the side of the floating gate opposite the source polysilicon.

According to some embodiments, a second floating gate is formed on the hard mask and on a side of the floating gate opposite the source polysilicon before the select gate is formed on the side of the floating gate opposite the source polysilicon. spacer.

According to some embodiments, after forming the second floating gate spacer and before forming the select gate, etching the exposed portions of the oxide layer (ie, the portions over which the gate structure, polysilicon, or spacers are not formed), and The oxide is grown on the substrate to provide an oxide with a desired thickness for select gates and/or logic devices.

According to some embodiments, before forming the select gate on a side of the floating gate opposite the source polysilicon: etching a portion of the oxide layer on a side of the floating gate opposite the source polysilicon to form a a first substrate oxide structure between the floating gate and the substrate; and depositing a second oxide on the substrate on a side of the floating gate opposite the source polysilicon to form a select gate and a second substrate oxide structure between the substrate.

According to some embodiments, the process of forming the select gate may include, but is not limited to, the steps of depositing polysilicon, polysilicon planarization (with or without dummy poly), photolithography of the polysilicon, and etching the polysilicon.

According to some embodiments, the erase gate and the select gate may be formed simultaneously in the same manufacturing process. According to other embodiments, the erase gate and the select gate may be formed sequentially in different manufacturing processes.

FIG. 13G shows a cross-sectional view of an exemplary structure formed after steps S1201 to S1210. As shown in FIG. 13G, the semiconductor structure 1300 further includes an erase gate 123 formed on the source polysilicon 122, and a first select gate formed on a side of the first floating gate 121a opposite to the source polysilicon 122. electrode 124a and a second select gate 124b formed on the side of the second floating gate 121b opposite the source polysilicon 122.

At step S1211, a drain region is formed in the substrate on the side of the selection gate opposite to the floating gate.

According to some embodiments, a drain implant process is performed to form a drain region in the substrate on a side of the select gate opposite the floating gate.

According to some embodiments, forming the drain region in the substrate on a side of the select gate opposite the floating gate further includes: performing lightening in the substrate on a side of the select gate opposite the floating gate. doping implants to form a lightly doped drain region; forming a lightly doped drain spacer on a side of the select gate opposite the floating gate; and forming a lightly doped drain spacer on a side of the lightly doped drain spacer opposite the select gate. A heavily doped implant is performed into one side of the substrate to form a heavily doped drain region. In the method as described in the present disclosure, by performing a lightly doped implant to form a lightly doped drain region, the channel electric field distribution in the memory cell can be improved.

According to some embodiments, the manufacturing method as described in the present disclosure further includes, after forming a drain region in the substrate on a side of the select gate opposite the floating gate: in the drain region, the select gate and the erase A silicide structure is formed above the gate.

FIG. 13H shows a cross-sectional view of an exemplary structure formed after steps S1201 to S1211. As shown in FIG. 13H , the semiconductor structure 1300 further includes a first drain region 111a in the substrate 110 on a side of the first selection gate 124a opposite the first floating gate 121a and a second selection gate 111a in the substrate 110 . The second drain region 111b in the substrate 110 on the side of 124b opposite to the second floating gate 121b.

According to some embodiments, after forming the symmetrical structure as shown in Figure 13H, slicing can be performed along the center line of the erase gate and source polysilicon to form the structures shown in Figures 1, 4-5 and 8-10 single memory cell structure. According to other embodiments, slicing may not be performed, so that adjacent memory cells in a symmetrical structure share the erase gate, source polysilicon, and source region, so as to reduce the overall area and size of the memory cell array.

According to some embodiments, the method of manufacturing a semiconductor device according to the present disclosure further includes forming a logic device over a logic region of the substrate.

14A-14M are schematic cross-sectional views of steps of a method of fabricating a semiconductor device 1400 according to some embodiments of the present disclosure.

According to some embodiments, as shown in FIG. 14A , similar to that described with reference to FIG. 13A , the semiconductor structure 1400 includes, from bottom to top, a substrate 110 , an oxide layer 1401 , a floating gate layer 1402 and a hard mask layer 1403 .

According to some embodiments, first, the oxide layer 1401 is grown on the upper surface of the substrate 110; then, floating gate polysilicon is deposited on the upper surface of the oxide layer 1401, and the floating gate polysilicon is planarized to form the floating gate layer 1402; then, a hard mask layer 1403 is deposited on the upper surface of the floating gate layer 1402.

According to some embodiments, before forming the oxide layer 1401 on the substrate 110, shallow trench isolation is pre-formed in the substrate 110, and/or memory cell wells are pre-implanted in the substrate 110.

According to some embodiments, as shown in Figure 14B, the hard mask layer 1403 is etched to form an opening 1411 through the hard mask layer 1403, and a first hard mask spacer 143a and a second hard mask spacer 143a are formed on the sides of the opening 1411. Hard mask spacer 143b.

According to some embodiments, as shown in FIG. 14C , floating gate layer 1402 is etched to form openings 1412 through hard mask layer 1403 and floating gate layer 1402 .

According to some embodiments, as shown in FIG. 14D , first, a source implantation process is performed in the area in the substrate 110 below the opening 1410 to form the source region 112 ; then, the residual material on the upper surface of the source region 112 is The oxide is cleaned to form openings 1410 through the hard mask layer 1403, the floating gate layer 1402, and the oxide layer 1401; then, an oxide is deposited in the openings 1410 (e.g., by high temperature oxidation), and the deposited oxide to form floating gate oxide structures 1431a-1431b on the sides of opening 1410.

According to some embodiments, as shown in Figure 14E, polysilicon is deposited over the source region 112 to fill the opening 1410 as shown in Figure 14D, and the deposited polysilicon is planarized.

According to some embodiments, as shown in Figure 14F, a photolithography process is performed on the upper surface of the semiconductor structure 1400 to form a photoresist pattern 1404 to etch the remaining portion of the hard mask layer 1403 as shown in Figure 14E , thereby forming the first hard mask 125a and the second hard mask 125b.

According to some embodiments, as shown in Figure 14G, first, the photoresist 1404 is removed; secondly, the remaining portion of the floating gate layer 1402 and the polysilicon 1420 as shown in Figure 14F are etched to form a first floating gate 121a, second floating gate 121b and source polysilicon 122.

According to some embodiments, as shown in Figure 14H, a second floating gate spacer 141b is formed on the side of the first floating gate 121a and the first hard mask 125a opposite the source polysilicon 122, in A fourth floating gate spacer 141d is formed on the side of the second floating gate 121b and the second hard mask 125b opposite the source polysilicon 122, and on the first floating gate oxide structure 1431a On the side of the second floating gate oxide structure 1431b facing the source polysilicon 122, a third floating gate oxide structure 1432a is formed, and on the side of the second floating gate oxide structure 1431b facing the source polysilicon 122, a fourth floating gate is formed. Oxide structure 1432b.

According to some embodiments, as shown in FIG. 14I , portions of the first floating gate oxide structure 1431a and the second floating gate oxide structure 1431b are removed to form a structure between the first floating gate 121a and the source. The first floating gate spacer 141a between the pole polysilicon 122 and the third floating gate spacer 141c between the second floating gate 121b and the source polysilicon 122, and the third floating gate spacer 141c is removed. Gate oxide structure 1432a and fourth floating gate oxide structure 1432b. Specifically, the first floating gate oxide structure 1431a may be removed through a photolithography process (eg, forming

photoresist patterns

1405a and 1405b as shown in FIG. 14I) and a wet etching process (eg, using a DHF solution) and a portion of the second floating gate oxide structure 1431b, as well as the third floating gate oxide structure 1432a and the fourth floating gate oxide structure 1432b.

According to some embodiments, as shown in FIG. 14J , first, a tunnel oxide is deposited over the source polysilicon 122 to form a tunnel oxide structure 142; then, the exposed portions of the oxide layer (i.e., those not formed over the source polysilicon 122) are etched. portions of the gate structure, polysilicon, or spacers); then,

oxide structures

152a and 152b are grown on the substrate 110 to provide the desired substrate oxide thickness for subsequently formed select gates and/or logic devices. .

According to some embodiments, as shown in Figure 14K, the first select gate 124a is formed on the side of the second floating gate spacer 141b opposite the first floating gate 121a, and on the fourth floating gate spacer A second select gate 124b is formed on the side of the body 141d opposite the second floating gate 121b, and an erase gate 123 is formed on the tunnel oxide structure 142. Specifically, forming select gates 124a-124b and erase gate 123 includes, but is not limited to, the steps of depositing polysilicon, polysilicon planarization (with or without dummy poly), photolithography of the polysilicon, and etching the polysilicon. .

According to some embodiments, as shown in FIG. 14L , first, a lightly doped implant is performed to form a first lightly doped drain region 1112a and a second lightly doped drain region 1112b; then, on the first select gate 124a A first lightly doped drain spacer 144a is formed on the side opposite to the second floating gate spacer 141b, and a third lightly doped drain spacer 144a is formed on the side of the second selection gate 124b opposite to the fourth floating gate spacer 141d. Two lightly doped drain spacers 144b; then, a heavily doped implant is performed to form a first heavily doped drain region 1111a and a second heavily doped drain region 1111b. According to some embodiments, photoresist may be used to cover areas on the substrate where logic devices are to be formed before lightly doped implantation is performed to protect these areas from exposure.

According to some embodiments, as shown in FIG. 14M, in the first heavily doped drain region 1111a and the second heavily doped drain region 1111b, the first select gate 124a, the second select gate 124b and the erase gate Silicide structures 161a-161e are formed on the upper surface of 123. According to some embodiments, the first heavily doped drain region 1111a and the second heavily doped drain region 1111b may be removed before forming a silicide structure on the first heavily doped drain region 1111a and the second heavily doped drain region 1111b. Oxide on drain region 1111b.

According to some embodiments, before etching the hard mask layer and the floating gate layer, a control gate layer is formed over the floating gate layer, and a hard mask layer is formed over the control gate layer. According to some embodiments, a dielectric layer (eg, an ONO layer) is formed on the floating gate layer before the control gate layer is formed on the floating gate layer.

According to some embodiments, etching the hard mask layer and the floating gate layer includes: etching the hard mask layer and the control gate layer to form a second opening through the hard mask layer and the control gate layer; and etching the floating gate layer. A portion of the gate layer located below the second opening to form the first opening. According to some embodiments, etching the hard mask layer and the control gate layer includes etching the hard mask layer, the control gate layer, and the dielectric layer to form the second opening.

According to some embodiments, etching the remaining portion of the hard mask layer includes etching the remaining portions of the hard mask layer and the control gate layer to form the hard mask and the control gate. According to some embodiments, etching remaining portions of the hard mask layer and control gate layer includes etching remaining portions of the hard mask layer, control gate layer, and dielectric layer to form the hard mask, control gate, and dielectric structures .

According to some embodiments, a first control gate spacer is formed on a side of the second opening before etching a portion of the floating gate layer below the second opening. According to some embodiments, two materials (eg, oxide and silicon nitride) may be used to form the first control gate spacer, for example, by depositing an oxide, depositing silicon nitride, and etching the deposited oxide and silicon nitride to form the first control gate spacer. According to some embodiments, a material (eg, oxide or silicon nitride) may be used to form the first control gate spacer, for example, by depositing a spacer material, and etching the deposited material to form the first control gate Polar spacer.

According to some embodiments, a second control gate spacer is formed on the side of the hard mask, control gate, and dielectric structure opposite the source polysilicon before etching the remainder of the floating gate layer and the polysilicon. According to some embodiments, two materials (eg, oxide and silicon nitride) may be used to form the second control gate spacer, for example, by depositing an oxide, depositing silicon nitride, and etching the deposited oxide and Silicon nitride to form the second control gate spacer. According to some embodiments, a material (eg, oxide or silicon nitride) may be used to form the second control gate spacer, for example, by depositing the spacer material, and etching the deposited material to form the first control gate Polar spacer.

15A-15O are schematic cross-sectional views of steps of a method of fabricating a semiconductor device 1500 according to some embodiments of the present disclosure.

According to some embodiments, as shown in FIG. 15A , similar to that described with reference to FIG. 13A , the semiconductor structure 1500 includes in order from bottom to top: a substrate 110 , an oxide layer 1501 , a floating gate layer 1502 , a dielectric layer 1503 , and a control gate. pole layer 1504 and hard mask layer 1505.

According to some embodiments, first, the oxide layer 1501 is grown on the upper surface of the substrate 110; then, floating gate polysilicon is deposited on the upper surface of the oxide layer 1501, and the floating gate polysilicon is planarized , to form the floating gate layer 1502; then, the dielectric layer 1503, the control gate layer 1504 and the hard mask layer 1505 are sequentially deposited on the upper surface of the floating gate layer 1502.

According to some embodiments, before forming the oxide layer 1501 on the substrate 110 , shallow trench isolation is pre-formed in the substrate 110 , and/or memory cell wells are pre-implanted in the substrate 110 .

According to some embodiments, as shown in Figure 15B, first, a photolithography process is performed, for example,

photoresist patterns

1506a and 1506b are formed as shown in Figure 15B; secondly, the dielectric layer 1503, the control gate layer 1504 and the hard mask are etched. film layer 1505 to form an opening 1511 through the hard mask layer 1505, the control gate layer 1504, and the dielectric layer 1503.

According to some embodiments, as shown in FIG. 15C , first and third

control gate spacers

143 a and 143 c are formed on the sides of the opening 1511 .

According to some embodiments, as shown in FIG. 15D , a portion of floating gate layer 1502 located below opening 1511 is etched to form a layer through hard mask layer 1505 , control gate layer 1504 , dielectric layer 1503 and floating gate layer Opening 1512 of 1502.

According to some embodiments, as shown in FIG. 15E , first, a source implantation process is performed in the area in the substrate 110 below the opening 1510 to form the source region 112 ; then, the residual material on the upper surface of the source region 112 is The oxide is cleaned to form openings 1510 through hard mask layer 1505, control gate layer 1504, dielectric layer 1503, floating gate layer 15022, and oxide layer 1501; then, an oxide (eg, , by high-temperature oxidation), and etching the deposited oxide to form floating gate oxide structures 1531a-1532b on the sides of opening 1510.

According to some embodiments, as shown in Figure 15F, polysilicon is deposited over the source region 112 to fill the opening 1510 as shown in Figure 15E, and the deposited polysilicon is planarized.

According to some embodiments, as shown in Figure 15G, a photolithography process is performed on the upper surface of the semiconductor structure 1500 to form a photoresist pattern 1504 to etch the remaining portion of the hard mask layer 1503 as shown in Figure 15E , thereby forming the first hard mask 126a, the second hard mask 126b, the first control gate 125a, the second control gate 125b, the first dielectric structure 145a and the second dielectric structure 145b.

According to some embodiments, as shown in Figure 15H, first, the photoresist pattern 1504 is removed; then, on the first hard mask 126a, the first control gate 125a and the first dielectric structure 145a opposite to the polysilicon 1520 A second control gate spacer 143b is formed on the side, and a fourth control gate spacer is formed on the side of the second hard mask 126b, the second control gate 125b, and the second dielectric structure 145b opposite the polysilicon 1520 Body 143d.

According to some embodiments, as shown in Figure 15I, the remaining portion of the floating gate layer 1502 and the polysilicon 1520 shown in Figure 15H are etched to form the first floating gate 121a, the second floating gate 121b and the source Extremely polysilicon 122.

According to some embodiments, as shown in Figure 15J, a second floating gate spacer is formed on the side of the stack of first floating gate 121a to first hard mask 125a opposite source polysilicon 122 141b, on the side of the stack of the second floating gate 121b to the second hard mask 125b opposite to the source polysilicon 122, a fourth floating gate spacer 141d is formed, and on the first floating gate 141b, a fourth floating gate spacer 141d is formed. On the side of the gate oxide structure 1531a facing the source polysilicon 122, a third floating gate oxide structure 1532a is formed, and on the side of the second floating gate oxide structure 1531b facing the source polysilicon 122, a third floating gate oxide structure 1532a is formed. Fourth floating gate oxide structure 1532b.

According to some embodiments, as shown in Figure 15K, partial structures of the first floating gate oxide structure 1531a and the second floating gate oxide structure 1531b shown in Figure 15J are removed to form a first floating gate oxide structure located on the first floating gate oxide structure 1531b. a first floating gate spacer 141a between the gate 121a and the source polysilicon 122 and a third floating gate spacer 141c between the second floating gate 121b and the source polysilicon 122, and, The third floating gate oxide structure 1532a and the fourth floating gate oxide structure 1532b shown in Figure 15J are removed. Specifically, the first floating gate oxide structure 1531a may be removed through a photolithography process (eg, forming

photoresist patterns

1505a and 1505b as shown in FIG. 15K) and a wet etching process (eg, using a DHF solution) and a portion of the second floating gate oxide structure 1531b, as well as the third floating gate oxide structure 1532a and the fourth floating gate oxide structure 1532b.

According to some embodiments, as shown in FIG. 15L , first, a tunnel oxide is deposited over the source polysilicon 122 to form a tunnel oxide structure 142; then, the exposed portions of the oxide layer (i.e., those not formed over the source polysilicon 122) are etched. portions of the gate structure, polysilicon, or spacers); then,

oxide structures

According to some embodiments, as shown in FIG. 15M , the first selection gate 124a is formed on the side of the second floating gate spacer 141b opposite the first floating gate 121a, and in the fourth floating gate spacer A second select gate 124b is formed on the side of the body 141d opposite the second floating gate 121b, and an erase gate 123 is formed on the tunnel oxide structure 142. Specifically, forming select gates 124a-124b and erase gate 123 includes, but is not limited to, the steps of depositing polysilicon, polysilicon planarization (with or without dummy poly), photolithography of the polysilicon, and etching the polysilicon. .

According to some embodiments, as shown in FIG. 15N , first, a lightly doped implant is performed to form a first lightly doped drain region 1112a and a second lightly doped drain region 1112b; then, on the first select gate 124a A first lightly doped drain spacer 144a is formed on the side opposite to the second floating gate spacer 141b, and a third lightly doped drain spacer 144a is formed on the side of the second selection gate 124b opposite to the fourth floating gate spacer 141d. Two lightly doped drain spacers 144b; then, a heavily doped implant is performed to form a first heavily doped drain region 1111a and a second heavily doped drain region 1111b. According to some embodiments, photoresist may be used to cover areas on the substrate where logic devices are to be formed before lightly doped implantation is performed to protect these areas from exposure.

According to some embodiments, as shown in Figure 15O, in the first heavily doped drain region 1111a and the second heavily doped drain region 1111b, the first select gate 124a, the second select gate 124b and the erase gate Silicide structures 161a-161e are formed on the upper surface of 123. According to some embodiments, the first heavily doped drain region 1111a and the second heavily doped drain region 1111b may be removed before forming a silicide structure on the first heavily doped drain region 1111a and the second heavily doped drain region 1111b. Oxide on drain region 1111b.

The present disclosure provides a method for manufacturing a semiconductor device, which includes: forming an oxide layer on a substrate; forming a floating gate layer on the oxide layer; forming a hard mask layer on the floating gate layer; etching the hard mask layer. a mask layer to form a first opening through the hard mask layer; forming stack spacers on both sides of the first opening; etching portions of the floating gate layer between the stack spacers to form stack spacers through a second opening of the body and floating gate layers; forming a source region in the substrate in a region below the second opening; depositing polysilicon over the source region; etching the remaining portion of the hard mask layer; etching the floating Remaining portion of the gate layer and polysilicon to form the floating gate and source polysilicon; forming an erase gate over the source polysilicon; forming a select gate on the side of the floating gate opposite the source polysilicon ; and forming a drain region in the substrate on a side of the select gate opposite the floating gate.

FIG. 16 is a schematic flowchart of a method 1600 of fabricating a semiconductor device according to some embodiments of the present disclosure.

At step S1601, an oxide layer is formed on the substrate.

According to some embodiments, step S1601 may be similar to that described with reference to step S1201 in FIG. 12 .

At step S1602, a floating gate layer is formed on the oxide layer.

According to some embodiments, step S1602 may be similar to that described with reference to step S1202 in FIG. 12 .

At step S1603, a hard mask layer is formed on the floating gate layer.

According to some embodiments, step S1603 may be similar to that described with reference to step S1203 in FIG. 12 .

FIG. 17A shows a cross-sectional view of an exemplary structure 1700 formed after steps S1601-S1603. As shown in FIG. 17A , similar to that described with reference to FIG. 13A , the semiconductor structure 1700 includes, from bottom to top, a substrate 110 , an oxide layer 1701 , a floating gate layer 1702 and a hard mask layer 1703 .

At step S1604, the hard mask layer is etched to form a first opening through the hard mask layer.

According to some embodiments, before etching the hard mask layer, photoresist is coated on the hard mask layer, and a photolithography process is performed to form a photoresist pattern required for a subsequent etching process.

At step S1605, stack spacers are formed on both sides of the first opening.

Figure 17B shows a cross-sectional view of an exemplary structure 1700 formed after steps S1601-S1605. As shown in FIG. 17B , the semiconductor structure 1700 further includes first spacers 125 a and second spacers 125 b formed in the first opening 1710 .

At step S1606, a portion of the floating gate layer located between the stacked spacers is etched to form a second opening through the stacked spacers and the floating gate layer.

At step S1607, a source region is formed in a region of the substrate below the second opening.

According to some embodiments, a source implant process (eg, using arsenic or phosphorus) is performed to form a source region in a region of the substrate below the second opening.

At step S1608, a portion of the oxide layer on the source region is removed, and polysilicon is deposited on the source region.

According to some embodiments, polysilicon is deposited on the source region to fill the second opening through the hard mask layer, floating gate layer, and oxide layer, and the deposited polysilicon is planarized.

According to some embodiments, a floating gate oxide structure is formed on the sides of the second opening before polysilicon is deposited on the source region.

Figure 17C shows a cross-sectional view of an exemplary structure 1700 formed after steps S1601-S1608. As shown in FIG. 17C , semiconductor structure 1700 also includes polysilicon 1720 over source region 112 .

At step S1609, the remaining portion of the hard mask layer is etched.

At step S1610, the remaining portion of the floating gate layer and the polysilicon are etched to form the floating gate and source polysilicon.

FIG. 17D shows a cross-sectional view of the exemplary structure 1700 formed after steps S1601 to S1610. As shown in FIG. 17D , the semiconductor structure 1700 also includes a first floating gate 121 a , a second floating gate 121 b and a source polysilicon 122 that are etched from the remaining portions of the floating gate layer and the polysilicon.

At step S1611, an erase gate is formed over the source polysilicon.

According to some embodiments, step S1611 may be similar to that described with reference to step S1209 in FIG. 12 .

According to some embodiments, before forming the erase gate over the source polysilicon, a portion of the floating gate oxide structure on the sides of the second opening is etched to form a gap between the floating gate and the source polysilicon. a first floating gate spacer; and forming a tunnel oxide structure on the sides of the second opening and on the upper surface of the source polysilicon.

At step S1612, a select gate is formed on the side of the floating gate opposite the source polysilicon.

According to some embodiments, step S1612 may be similar to that described with reference to step S1210 in FIG. 12 .

According to some embodiments, a second floating gate is formed on the stacked spacer and the side of the floating gate opposite the source polysilicon before the select gate is formed on the side of the floating gate opposite the source polysilicon. spacer.

According to some embodiments, before forming the select gate on the side of the floating gate opposite the source polysilicon, a portion of the oxide layer on the side of the floating gate opposite the source polysilicon is etched to form a a first substrate oxide structure between the floating gate and the substrate; and depositing a second oxide on the substrate on a side of the floating gate opposite the source polysilicon to form a select gate and a second substrate oxide structure between the substrate.

At step S1613, a drain region is formed in the substrate on the side of the selection gate opposite to the floating gate.

According to some embodiments, step S1613 may be similar to that described with reference to step S1211 in FIG. 12 .

According to some embodiments, forming the drain region in the substrate on a side of the select gate opposite the floating gate further includes: performing lightening in the substrate on a side of the select gate opposite the floating gate. doping implants to form a lightly doped drain region; forming a lightly doped drain spacer on a side of the select gate opposite the floating gate; and forming a lightly doped drain spacer on a side of the lightly doped drain spacer opposite the select gate. A heavily doped implant is performed into one side of the substrate to form a heavily doped drain region.

Figure 17E shows a cross-sectional view of an exemplary structure 1700 formed after steps S1601 to S1613. As shown in FIG. 17E , the semiconductor structure 1700 further includes an erase gate 123 formed over the source polysilicon 122 , and a first select gate formed on a side of the first floating gate 121 a opposite to the source polysilicon 122 . electrode 124a, a second selection gate 124b formed on the side of the second floating gate 121b opposite to the source polysilicon 122, and a side of the first selection gate 124a opposite to the first floating gate 121a. a first drain region 111a in the substrate 110, and a second drain region 111b in the substrate 110 on a side of the second selection gate 124b opposite to the second floating gate 121b.

According to some embodiments, after forming the symmetrical structure as shown in Figure 17E, slicing can be performed along the center line of the erase gate and source polysilicon to form the structures shown in Figures 1, 4-5, and 8-10 single memory cell structure. According to other embodiments, slicing may not be performed, so that adjacent memory cells in a symmetrical structure share the erase gate, source polysilicon, and source region, so as to reduce the overall area and size of the memory cell array.

18A-18E are schematic cross-sectional views of steps of a method of fabricating a semiconductor device 1800 according to some embodiments of the present disclosure.

According to some embodiments, as shown in FIG. 18A , similar to that described with reference to FIG. 17A , the semiconductor structure 1800 includes, from bottom to top, a substrate 110 , an oxide layer 1801 , a floating gate layer 1802 and a hard mask layer 1803 .

According to some embodiments, as shown in FIG. 18B , similar to that described with reference to FIG. 17B , the semiconductor structure 1800 further includes first spacers 125 a and second spacers 125 b formed in the first opening 1810 .

According to some embodiments, as shown in FIG. 18C , first, a portion of the floating gate layer 1802 located between the stacked spacers 125a - 125b is etched to form a layer through the stacked spacers 125a - 125b and the floating gate layer 1802 a second opening; then, the source region 112 is formed in the area of the substrate 110 below the second opening; then, the remaining oxide on the upper surface of the source region 112 is cleaned; then, in the second opening Floating gate oxide structures 1831a-1831b are formed on the sides of the source region 112; then, polysilicon 1820 is deposited on the source region 112, and the deposited polysilicon 1820 is planarized.

According to some embodiments, as shown in Figure 18D, similar to that described with reference to 17D, the remaining portion of the hard mask layer is etched, and the remaining portion of the floating gate layer and the polysilicon are etched to form the first floating gate 121a , the second floating gate 121b and the source polysilicon 122.

According to some embodiments, by processing the semiconductor structure 1800 through the process steps described with reference to FIGS. 14H-14M, the semiconductor structure 1800 as shown in FIG. 18E can be obtained.

According to the manufacturing method of a semiconductor device according to an embodiment of the present disclosure, in the semiconductor device manufactured by disposing the erase gate above the source polysilicon, the coupling area between the erase gate and the floating gate can be adjusted, thereby reducing erasure. Eliminating the coupling voltage between the gate and the floating gate allows for a more efficient erase operation; and since the erase gate is disposed above the source polysilicon, the thickness requirements for the floating gate can be reduced , reducing the difficulty of the manufacturing process.

Furthermore, in the method of manufacturing a semiconductor device according to the present disclosure, since source polysilicon is provided above the source region in the substrate, electrical connection between the plurality of bit lines can be achieved through the source polysilicon. Therefore, compared with the prior art solution that uses a source active area or a combination of tungsten plugs and metal lines to achieve electrical connections between multiple bit lines, the floating gates of adjacent memory cells in the memory cell array are shortened. The distance between the poles allows the size of the memory cell to be reduced.

Some example aspects of the disclosure are described below.

Aspect 1. A semiconductor device, including:

A substrate includes a memory cell region, wherein the memory cell region includes a first drain region, a first channel region, and a source region, wherein the first channel region is between the first drain region and extending between the source regions;

a first floating gate located above the first portion of the first channel region;

Source polysilicon, located above the source region;

an erase gate located above the source polysilicon;

a first select gate located over the second portion of the first channel region and on a side of the first floating gate opposite the source polysilicon;

A first programming channel extends from the first drain region to an edge of the first floating gate facing the first selection gate;

a second programming channel extending from the first drain region to the source region; and

A first erase channel extends from an edge portion of the first floating gate facing the erase gate to the erase gate.

Aspect 2. The semiconductor device according to aspect 1, further comprising:

A first hard mask or a first stacked spacer is located on the upper surface of the first floating gate.

Aspect 3. The semiconductor device according to aspect 1, further comprising:

a first control gate located above the first floating gate; and

A first hard mask is located on the upper surface of the first control gate.

Aspect 4. The semiconductor device of aspect 3, further comprising:

a first dielectric structure located on the upper surface of the first floating gate,

Wherein, the first control gate is located on the upper surface of the first dielectric structure.

Aspect 5. The semiconductor device of aspect 4, further comprising:

Control gate spacers are formed on both sides of the first dielectric structure, the first control gate, and the first hard mask.

Aspect 6. The semiconductor device according to any one of aspects 1-5, further comprising:

a first floating gate spacer between the first floating gate and the source polysilicon; and

A tunnel oxide structure is formed on the lower surface of the erase gate and the side facing the first floating gate.

Aspect 7. The semiconductor device according to any one of Aspects 1-5, further comprising:

A second floating gate spacer is located between the first floating gate and the first selection gate.

Aspect 8. The semiconductor device according to any one of Aspects 1-5, further comprising:

a first substrate oxide structure located between the first floating gate and the substrate; and

A second substrate oxide structure is located between the first selection gate and the substrate.

Aspect 9. The semiconductor device according to any one of aspects 1-5, wherein the first drain region further includes a lightly doped drain region and a heavily doped drain region, and the semiconductor device further include:

A first lightly doped drain spacer is located above the first drain region and on a side of the first select gate opposite the first floating gate.

Aspect 10. The semiconductor device according to any one of aspects 1-5, further comprising:

A silicide structure is located above the first drain region, the first select gate and the erase gate.

Aspect 11. The semiconductor device according to any one of aspects 1-5, wherein the memory cell region further includes:

a second drain region and a second channel region, wherein the second channel region extends between the second drain region and the source region; and

The semiconductor device also includes:

a second floating gate located above the first portion of the second channel region;

a second select gate located over a second portion of the second channel region and on a side of the second floating gate opposite the source polysilicon;

A third programming channel extends from the second drain region to an edge of the second floating gate facing the second selection gate;

a fourth programming channel extending from the second drain region to the source region; and

A second erase channel extends from an edge portion of the second floating gate facing the second erase gate to the erase gate.

Aspect 12. The semiconductor device of aspect 11, further comprising:

A second hard mask or a second stacked spacer is located on the upper surface of the second floating gate.

Aspect 13. The semiconductor device of aspect 11, further comprising:

a second control gate located above the second floating gate; and

A second hard mask is located on the upper surface of the second control gate.

Aspect 14. The semiconductor device of any one of aspects 1-5, wherein the substrate further includes a logic region, and the semiconductor device further includes:

A logic device is located over the logic area of the substrate.

Aspect 15. A method of manufacturing a semiconductor device, comprising:

forming an oxide layer on the substrate;

forming a floating gate layer on the oxide layer;

forming the hard mask layer on the floating gate layer;

Etching the hard mask layer and the floating gate layer to form a first opening through the hard mask layer and the floating gate layer;

forming a source region in a region of the substrate below the first opening; removing a portion of the oxide layer on the source region, and depositing polysilicon on the source region;

etching a remaining portion of the hard mask layer to form the hard mask;

etching remaining portions of the floating gate layer and the polysilicon to form the floating gate and the source polysilicon;

forming an erase gate over the source polysilicon;

forming a select gate on a side of the floating gate opposite the source polysilicon; and

A drain region is formed in the substrate on a side of the select gate opposite the floating gate.

Aspect 16. The method of aspect 15, further comprising before etching the hard mask layer and the floating gate layer:

forming the control gate layer over the floating gate layer; and

forming the hard mask layer on the control gate layer, and,

The etching of the hard mask layer and the floating gate layer includes:

Etching the hard mask layer and the control gate layer to form a second opening through the hard mask layer and the control gate layer; and

etching a portion of the floating gate layer below the second opening to form the first opening, and

The etching the remaining portion of the hard mask layer includes:

Remaining portions of the hard mask layer and the control gate layer are etched to form the hard mask and the control gate.

Aspect 17. The method of aspect 16, further comprising before forming the control gate layer on the floating gate layer:

forming a dielectric layer on the floating gate layer, and,

The etching of the hard mask layer and the control gate layer includes:

etching the hard mask layer, the control gate layer, and the dielectric layer to form the second opening, and

Etching remaining portions of the hard mask layer and the control gate layer includes:

Remaining portions of the hard mask layer, the control gate layer, and the dielectric layer are etched to form the hard mask, the control gate layer, and the dielectric structure.

Aspect 18. The method of aspect 17, further comprising before etching a portion of the floating gate layer located below the second opening:

forming a first portion of a first control gate spacer on a side of the second opening, and,

The method also includes before etching the remaining portion of the floating gate layer and the polysilicon:

A second portion of the first control gate spacer is formed on the hard mask, the control gate, and the side of the dielectric structure opposite the source polysilicon.

Aspect 19. The method of any one of aspects 15-18, further comprising prior to depositing polysilicon on the source region:

forming a floating gate oxide structure on the side of the first opening, and,

The method further includes prior to forming an erase gate over the source polysilicon:

etching a portion of the floating gate oxide structure on the sides of the first opening to form a first floating gate spacer between the floating gate and the source polysilicon; and

A tunnel oxide structure is formed on the sides of the first opening and on the upper surface of the source polysilicon.

Aspect 20. The method of any one of aspects 15-18, further comprising prior to forming a select gate on a side of the floating gate opposite the source polysilicon:

A second floating gate spacer is formed on the hard mask and the side of the floating gate opposite the source polysilicon.

Aspect 21. The method of any one of aspects 15-18, further comprising prior to forming a select gate on a side of the floating gate opposite the source polysilicon:

Etching a portion of the oxide layer on a side of the floating gate opposite the source polysilicon to form a first substrate oxide between the floating gate and the substrate physical structure; and

A second oxide is deposited on the substrate on the side of the floating gate opposite the source polysilicon to form a second oxide between the select gate and the substrate. Bottom oxide structure.

Aspect 22. The method of any one of aspects 15-18, wherein forming a drain region in the substrate on a side of the select gate opposite the floating gate further comprises:

performing a lightly doped implant in the substrate on a side of the select gate opposite the floating gate to form a lightly doped drain region;

Forming a lightly doped drain spacer on the side of the select gate opposite the floating gate; and

A heavily doped implant is performed in the substrate on a side of the lightly doped drain spacer opposite the select gate to form a heavily doped drain region.

Aspect 23. The method of any one of aspects 15-18, further comprising, after forming a drain region in the substrate on a side of the select gate opposite the floating gate:

A silicide structure is formed over the drain region, the select gate and the erase gate.

Aspect 24. The method of any of Aspects 15-18, further comprising:

Logic devices are formed over logic areas of the substrate.

Aspect 25. A method of manufacturing a semiconductor device, comprising:

forming an oxide layer on the substrate;

forming a floating gate layer on the oxide layer;

forming the hard mask layer on the floating gate layer;

etching the hard mask layer to form a first opening through the hard mask layer;

forming stacked spacers on both sides of the first opening;

Etching a portion of the floating gate layer between the stacked spacers to form a second opening through the stacked spacers and the floating gate layer;

forming a source region in a region of the substrate below the second opening;

removing a portion of the oxide layer on the source region and depositing polysilicon on the source region;

Etching the remaining portion of the hard mask layer;

forming an erase gate over the source polysilicon;

Aspect 26. The method of aspect 25, further comprising prior to depositing polysilicon on the source region:

forming a floating gate oxide structure on the sides of the second opening, and,

etching a portion of the floating gate oxide structure on the sides of the second opening to form a first floating gate spacer between the floating gate and the source polysilicon; and

A tunnel oxide structure is formed on the sides of the second opening and on the upper surface of the source polysilicon.

Aspect 27. The method of aspect 25, further comprising prior to forming a select gate on a side of the floating gate opposite the source polysilicon:

A second floating gate spacer is formed on the stack spacer and a side of the floating gate opposite the source polysilicon.

Aspect 28. The method of aspect 25, further comprising prior to forming a select gate on a side of the floating gate opposite the source polysilicon:

Aspect 29. The method of aspect 25, wherein forming a drain region in the substrate on a side of the select gate opposite the floating gate further includes:

Aspect 30. The method of aspect 25, further comprising after forming a drain region in the substrate on a side of the select gate opposite the floating gate:

A suicide structure is formed over the drain region, the select gate and the erase gate.

Aspect 31. The method of aspect 25, further comprising:

Logic devices are formed over logic areas of the substrate.

While the present disclosure has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative and illustrative rather than restrictive; the present disclosure is not limited to the disclosed embodiment. By studying the drawings, the disclosure, and the appended claims, those skilled in the art will be able to understand and implement variations to the disclosed embodiments in practicing the claimed subject matter. In the claims, the word "comprising" does not exclude other elements or steps not listed, the indefinite article "a" or "an" does not exclude a plurality, and the term "plurality" refers to two or more . The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

A semiconductor device including:

A substrate includes a memory cell region, wherein the memory cell region includes a first drain region, a first channel region, and a source region, wherein the first channel region is between the first drain region and extending between the source regions;

a first floating gate located above the first portion of the first channel region;

Source polysilicon, located above the source region;

an erase gate located above the source polysilicon;

a first select gate located over the second portion of the first channel region and on a side of the first floating gate opposite the source polysilicon;

A first programming channel extends from the first drain region to an edge of the first floating gate facing the first selection gate;

a second programming channel extending from the first drain region to the source region; and

A first erase channel extends from an edge portion of the first floating gate facing the erase gate to the erase gate.
The semiconductor device according to claim 1, further comprising:

A first hard mask or a first stacked spacer is located on the upper surface of the first floating gate.
The semiconductor device according to claim 1, further comprising:

a first control gate located above the first floating gate; and

A first hard mask is located on the upper surface of the first control gate.
The semiconductor device according to claim 3, further comprising:

a first dielectric structure located on the upper surface of the first floating gate,

Wherein, the first control gate is located on the upper surface of the first dielectric structure.
The semiconductor device according to claim 4, further comprising:

Control gate spacers are formed on both sides of the first dielectric structure, the first control gate, and the first hard mask.
The semiconductor device according to any one of claims 1-5, further comprising:

a first floating gate spacer between the first floating gate and the source polysilicon; and

A tunnel oxide structure is formed on the lower surface of the erase gate and the side facing the first floating gate.
The semiconductor device according to any one of claims 1-5, further comprising:

A second floating gate spacer is located between the first floating gate and the first selection gate.
The semiconductor device according to any one of claims 1-5, further comprising:

a first substrate oxide structure located between the first floating gate and the substrate; and

A second substrate oxide structure is located between the first selection gate and the substrate.
The semiconductor device according to any one of claims 1 to 5, wherein the first drain region further includes a lightly doped drain region and a heavily doped drain region, and the semiconductor device further includes:

A first lightly doped drain spacer is located above the first drain region and on a side of the first select gate opposite the first floating gate.
The semiconductor device according to any one of claims 1-5, further comprising:

A silicide structure is located above the first drain region, the first select gate and the erase gate.
The semiconductor device according to any one of claims 1 to 5, wherein the memory cell region further includes:

a second drain region and a second channel region, wherein the second channel region extends between the second drain region and the source region; and

The semiconductor device also includes:

a second floating gate located above the first portion of the second channel region;

a second select gate located over a second portion of the second channel region and on a side of the second floating gate opposite the source polysilicon;

A third programming channel extends from the second drain region to an edge of the second floating gate facing the second selection gate;

a fourth programming channel extending from the second drain region to the source region; and

A second erase channel extends from an edge portion of the second floating gate facing the second erase gate to the erase gate.
The semiconductor device according to claim 11, further comprising:

A second hard mask or a second stacked spacer is located on the upper surface of the second floating gate.
The semiconductor device according to claim 11, further comprising:

a second control gate located above the second floating gate; and

A second hard mask is located on the upper surface of the second control gate.
The semiconductor device according to any one of claims 1-5, wherein the substrate further includes a logic region, and the semiconductor device further includes:

A logic device is located over the logic area of the substrate.
A method for manufacturing a semiconductor device, including:

forming an oxide layer on the substrate;

forming a floating gate layer on the oxide layer;

forming the hard mask layer on the floating gate layer;

Etching the hard mask layer and the floating gate layer to form a first opening through the hard mask layer and the floating gate layer;

forming a source region in a region of the substrate below the first opening; removing a portion of the oxide layer on the source region, and depositing polysilicon on the source region;

etching a remaining portion of the hard mask layer to form the hard mask;

etching remaining portions of the floating gate layer and the polysilicon to form the floating gate and the source polysilicon;

forming an erase gate over the source polysilicon;

forming a select gate on a side of the floating gate opposite the source polysilicon; and

A drain region is formed in the substrate on a side of the select gate opposite the floating gate.
The method of claim 15, further comprising before said etching said hard mask layer and said floating gate layer:

forming the control gate layer over the floating gate layer; and

forming the hard mask layer on the control gate layer, and,

The etching of the hard mask layer and the floating gate layer includes:

Etching the hard mask layer and the control gate layer to form a second opening through the hard mask layer and the control gate layer; and

etching a portion of the floating gate layer below the second opening to form the first opening, and

The etching the remaining portion of the hard mask layer includes:

Remaining portions of the hard mask layer and the control gate layer are etched to form the hard mask and the control gate.
The method of claim 16, further comprising before forming the control gate layer on the floating gate layer:

forming a dielectric layer on the floating gate layer, and,

The etching of the hard mask layer and the control gate layer includes:

etching the hard mask layer, the control gate layer, and the dielectric layer to form the second opening, and

Etching remaining portions of the hard mask layer and the control gate layer includes:

Remaining portions of the hard mask layer, the control gate layer, and the dielectric layer are etched to form the hard mask, the control gate layer, and the dielectric structure.
The method of claim 17, further comprising before etching a portion of the floating gate layer located below the second opening:

forming a first portion of a first control gate spacer on a side of the second opening, and,

The method also includes before etching the remaining portion of the floating gate layer and the polysilicon:

A second portion of the first control gate spacer is formed on the hard mask, the control gate, and the side of the dielectric structure opposite the source polysilicon.
The method of any one of claims 15-18, further comprising before depositing polysilicon on the source region:

forming a floating gate oxide structure on the side of the first opening, and,

The method further includes prior to forming an erase gate over the source polysilicon:

etching a portion of the floating gate oxide structure on the sides of the first opening to form a first floating gate spacer between the floating gate and the source polysilicon; and

A tunnel oxide structure is formed on the sides of the first opening and on the upper surface of the source polysilicon.
The method of any one of claims 15-18, further comprising prior to forming a select gate on a side of the floating gate opposite the source polysilicon:

A second floating gate spacer is formed on the hard mask and the side of the floating gate opposite the source polysilicon.
The method of any one of claims 15-18, further comprising prior to forming a select gate on a side of the floating gate opposite the source polysilicon:

Etching a portion of the oxide layer on a side of the floating gate opposite the source polysilicon to form a first substrate oxide between the floating gate and the substrate physical structure; and

A second oxide is deposited on the substrate on the side of the floating gate opposite the source polysilicon to form a second oxide between the select gate and the substrate. Bottom oxide structure.
The method of any one of claims 15-18, wherein forming a drain region in the substrate on a side of the select gate opposite the floating gate further includes:

performing a lightly doped implant in the substrate on a side of the select gate opposite the floating gate to form a lightly doped drain region;

Forming a lightly doped drain spacer on the side of the select gate opposite the floating gate; and

A heavily doped implant is performed in the substrate on a side of the lightly doped drain spacer opposite the select gate to form a heavily doped drain region.
The method of any one of claims 15-18, further comprising after forming a drain region in the substrate on a side of the select gate opposite the floating gate:

A silicide structure is formed over the drain region, the select gate and the erase gate.
The method according to any one of claims 15-18, further comprising:

Logic devices are formed over logic areas of the substrate.
A method for manufacturing a semiconductor device, including:

forming an oxide layer on the substrate;

forming a floating gate layer on the oxide layer;

forming the hard mask layer on the floating gate layer;

etching the hard mask layer to form a first opening through the hard mask layer;

forming stacked spacers on both sides of the first opening;

Etching a portion of the floating gate layer between the stacked spacers to form a second opening through the stacked spacers and the floating gate layer;

forming a source region in a region of the substrate below the second opening;

removing a portion of the oxide layer on the source region and depositing polysilicon on the source region;

Etching the remaining portion of the hard mask layer;

etching remaining portions of the floating gate layer and the polysilicon to form the floating gate and the source polysilicon;

forming an erase gate over the source polysilicon;

forming a select gate on a side of the floating gate opposite the source polysilicon; and

A drain region is formed in the substrate on a side of the select gate opposite the floating gate.
The method of claim 25, further comprising before depositing polysilicon on the source region:

forming a floating gate oxide structure on the sides of the second opening, and,

The method further includes prior to forming an erase gate over the source polysilicon:

etching a portion of the floating gate oxide structure on the sides of the second opening to form a first floating gate spacer between the floating gate and the source polysilicon; and

A tunnel oxide structure is formed on the sides of the second opening and on the upper surface of the source polysilicon.
The method of claim 25, further comprising prior to forming a select gate on a side of the floating gate opposite the source polysilicon:

A second floating gate spacer is formed on the stack spacer and a side of the floating gate opposite the source polysilicon.
The method of claim 25, further comprising prior to forming a select gate on a side of the floating gate opposite the source polysilicon:

Etching a portion of the oxide layer on a side of the floating gate opposite the source polysilicon to form a first substrate oxide between the floating gate and the substrate physical structure; and

A second oxide is deposited on the substrate on the side of the floating gate opposite the source polysilicon to form a second oxide between the select gate and the substrate. Bottom oxide structure.
The method of claim 25, wherein forming a drain region in the substrate on a side of the select gate opposite the floating gate further includes:

performing a lightly doped implant in the substrate on a side of the select gate opposite the floating gate to form a lightly doped drain region;

Forming a lightly doped drain spacer on the side of the select gate opposite the floating gate; and

A heavily doped implant is performed in the substrate on a side of the lightly doped drain spacer opposite the select gate to form a heavily doped drain region.
The method of claim 25, further comprising after forming a drain region in the substrate on a side of the select gate opposite the floating gate:

A silicide structure is formed over the drain region, the select gate and the erase gate.
The method of claim 25, further comprising:

Logic devices are formed over logic areas of the substrate.