JP4159849B2 - Floating gate memory array manufacturing method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile memory, and more particularly, to a flash EPROM cell using a floating gate transistor, an array device, and a method for manufacturing the same.
[0002]
[Prior art]
Flash EPROM is a growing field in nonvolatile charge storage semiconductor integrated circuits. These flash EPRQMs have the ability to electrically erase, program and read memory cells in the chip. Flash EPROM memory cells are formed using so-called floating gate transistors in which data is stored in the cells by charging or discharging the floating gate. The floating gate is made of a conductive material, typically poly-Si, insulated from the transistor channel by an oxide or other insulating thin film, and by a second insulating film of the transistor. Isolated from control gate or word line.
[0003]
The operation of charging the floating gate is referred to as the “program” step of the flash EPROM. This step is performed by applying a positive voltage of about 12 volts between the gate and the source, and applying a positive voltage between the drain and the source, for example, a voltage of 7 volts.・ It is done by injection of electrons.
The operation of discharging the floating gate is called the “erase” function of the flash EPROM. This erase function is typically accomplished by a FN tunneling mechanism between the floating gate and the source of the transistor (source erase) or between the floating gate and the semiconductor substrate (channel erase). For example, the source erase action is achieved by applying a large positive voltage from the source to the gate while floating the drain of each memory cell. This positive voltage can be as high as 12 volts.
[0004]
Details regarding the structure and function of a conventional flash EPROM can be found in the following U.S. Pat. S. You can know by patent.
Mukherjee, et al., US Patent No. 4,698,787 issued October 6, 1987; Holler, et al., US Patent No. 4,780,423 issued October 25, 1988. More advanced technologies related to flash EPROM ICs are described in the following document: It has been.
Woo, et al., "A Novel Memory Cell Using Flash Array Contactless EPROM (FACE) Technology", IEDM 1990, Published by the IEEE, Pages 91-94 and Woo, et al., "A Poly-Buffered" FACE "Technology for High Density Memories "1991 SYMPOSIUM ON VLS1 TECHNOLOGY, page 73-74
An example of a prior art contactless array EPROM device is described below.
Kazerounian et al. "Alternate Metal Virtual Ground EPROM Array Implemented In A 0.8 (M Process for Very High Density Applications" IEDM, Published by IEEE 1991, pages 11.5.1-11.5.4.
[0005]
[Patent Document 1]
Mukherjee, et al., US Patent No. 4,698,787 issued October 6, 1987
[Patent Document 2]
Holler, et al., US Patent NO.4,780,423 issued October 25, 1988.
[Non-Patent Document 1]
Woo, et al., "A Novel Memory Cell Using Flash Array Contactless EPROM (FACE) Technology", IEDM 1990, Published by the IEEE, Pages 91-94
[Non-Patent Document 2]
Woo, et al., "A Poly-Buffered" FACE "Technology for High Density Memories" 1991 SYMPOSIUM ON VLS1 TECHNOLOGY, page 73-74
[Non-Patent Document 3]
Kazerounian et al. "Alternate Metal Virtual Ground EPROM Array Implemented In A 0.8 (M Process for Very High Density Applications" IEDM, Published by IEEE 1991, pages 11.5.1-11.5.4
[0006]
[Problems to be solved by the invention]
Woo et al. And as is evident by Kazerounian et al publications, there is growing interest in the design of contactless array non-volatile memories. A so-called contactless array is formed by an array of storage cells that are coupled to each other by a buried diffusion layer, and the buried diffusion layer is intermittently coupled to a metal bit line by a contact. Only.
Mukherjee et al. Early flash EPROM designs such as these systems require "half" metal contacts for each memory cell. This is because metal contacts occupy a considerable area in a semiconductor integrated circuit, which is a great obstacle to designing a high-density memory. Furthermore, attempts to make the device even smaller and reduce the area are limited by the metal covering the adjacent drain and source bit line contacts used to access the storage cells in the array. Become.
[0007]
The present invention has been made in view of the above, and relates to an improvement of a nonvolatile memory cell including a floating gate transistor, and more particularly, a flash EPROM cell capable of high density integration and an array device thereof. The purpose is to provide a manufacturing method thereof.
It is another object of the present invention to provide a memory circuit using an improved flash EPROM cell.
[0008]
[Means for Solving the Problems]
The present invention is based on a unique drain-source-drain configuration in which a non-volatile memory cell (flash EPROM cell) is based on a unique drain-source-drain configuration in which a single source diffusion layer is shared by two floating gate transistors. First 1 The second drain diffusion region and the source diffusion region are formed along the semiconductor substrate. The field oxide region is formed outside the first and second drain diffusion regions. The floating gate and control gate word line are formed to be orthogonal to the drain-source-drain structure formed from two rows of storage cells with shared source regions. The shared source region is coupled to a virtual ground terminal by a lower block select transistor. Each drain diffusion region is coupled to a wide area bit line by an upper block select transistor. The cell structure according to the present invention is for a virtual ground supply that couples a plurality of column transistors to a virtual ground and a final through horizontal conductors such as a drain, a source and drain diffusion region, and a buried diffusion line. , Using two wide area bit lines extending substantially in parallel. In this way, only two metal contact pitches are required for a cell consisting of two transistors.
[0009]
According to another aspect of the present invention, these multiple drain-source-drain structures are arranged in one large IC, and a high-density nonvolatile charge storage semiconductor integrated circuit is obtained. This nonvolatile charge storage type semiconductor integrated circuit can be divided along the boundary of the block by using the upper and lower block select transistors, and enables individual erasing operations. The block select feature couples a single block of memory cells to a wide area bit line at a time. This provides an improvement over the leakage current to the transistors along a given column of the array.
[0010]
Thus, one memory circuit is provided as K subarrays having storage cells each consisting of N columns and M rows. Each storage cell in the storage cell array has a first terminal, a second terminal, and a control terminal. There are a number of word lines coupled to the control terminals of the storage cells corresponding to each row. N wide-area bit lines consisting of bit lines corresponding to each column of storage cells, and each of which is coupled to a first terminal of M storage cells in each column within a respective sub-array. There are local bit lines. The upper block select transistor selectively connects a local bit line in the storage cell sub-array to a corresponding wide-area bit line in response to the sub-array select signal. In addition, a number of local virtual ground lines and means for connecting the local virtual ground lines in the sub-array to the local virtual ground terminal are included. Each of the local virtual ground lines is coupled to a second evening terminal of storage cells in a column at a respective subarray. A column select transistor coupled to the global bit line is capable of selectively accessing N columns of storage cells.
[0011]
In addition to the memory cells and array devices described above, a method of manufacturing an array of floating gate devices is provided.
The first method is configured as follows.
Defining a number of drain diffusion regions extending in a first direction;
Doping the drain diffusion region;
Forming a tunnel insulating film on the main surface of the semiconductor substrate at least in a region adjacent to the drain diffusion region;
Providing a floating gate conductive material in the tunnel insulating film at least in a region adjacent to the drain diffusion region;
Forming a control gate insulating material on the floating gate conductive film;
Exposing the extended source diffusion region in alignment with the floating gate conductive material by a floating gate conductive material formed on the main surface of the semiconductor substrate;
Doping the source diffusion region;
Providing an insulating layer also on the source diffusion region and the exposed floating gate conductive material; and
Form rows of multiple conductive materials to cover the control insulating material and the floating gate conductive material.
The second method is configured as follows:
Forming a tunnel insulating material so that at least the extended channel region covers the main surface of the semiconductor substrate;
Providing a floating gate conductive material to cover at least the tunnel insulating material in the extended channel region;
Providing a control gate insulating material to cover the floating gate conductive material;
Exposing the source and drain diffusion regions extending to the semiconductor substrate by aligning them with a floating gate conductive material;
Doping the drain diffusion region with a dopant in a first distribution; doping the source diffusion region with a dopant in a second distribution;
Growing an insulating layer over the source and drain diffusion regions and also on top of the exposed floating 'gate conductive material; and
Form rows of multiple conductive materials to cover the control insulating material and the floating gate conductive material.
[0012]
[Action]
There are several distinct features in the floating gate transistor and non-volatile memory of the present invention.
First, the metal pitch of adjacent drain and source bit lines is relaxed by having a structure sharing the source (virtual ground) bit line. The bit line is a transistor. Etc. Are connected to a single metal source line along with metal drain contact lines or wide area bit lines. This makes it possible to obtain a very close core array.
Second, the flash EPROM array can perform sector erase while the flash EPROM array that is divided into sub-arrays is selected by a fully decoded block select line, and memory cell failure. Occurs only while its corresponding sub-array is selected. This greatly improves product operation and reliability.
Third, in the first cell type, the source side of the cell is not subjected to a number of oxidation processes, so the end of the source junction retains very good integrity. What is more characteristic is that the source junction edge is not subject to dopant depletion and the effect of increasing the thickness of the oxide edge that is common in cells designed according to the prior art. In the prior art, there is a more extensive oxidation process after source implantation. For this reason, a good source erasing action can be expected for a new cell. Furthermore, fairly high gade coupling ratios can be achieved with unique cell layout. In the layout, the floating gate poly-Si layer extends over the drain and field oxide regions, and the coupling area of the control gate to the floating gate poly-Si can be significantly increased.
[0013]
Further, according to the first manufacturing method, the source diffusion region in the cell structure is self-aligned with the floating gate transistor in the adjacent transistor row. Similarly, the drain diffusion region is self-aligned with the insulating region on the opposite side of each block. Furthermore, according to the second manufacturing method, both the drain and source diffusion regions are self-aligned to the floating gate. Thus, the drain-source-drain configuration can create a substantially uniform channel length for all memory cell transistors in the array. The source is also made by ion implantation with a dopant distribution that provides a graded junction, facilitating tunneling during the source erase operation.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described with reference to FIGS. 1 and 2 show circuit diagrams of a flash EPROM device according to the present invention. FIG. 3 shows a block diagram of a memory circuit of a flash EPROM device according to the present invention. 4, 5, 6 and 7 are cross-sectional views showing a method of manufacturing a flash EPROM cell according to the present invention. FIG. 8 is a plan view thereof.
FIG. 1 illustrates a drain-source-drain circuit configuration (a configuration including a pair of transistors having a common source) of a flash EPROM according to the present invention. This circuit configuration has a first local bit line 10 and a second local bit line 11. The first and second local bit lines 10 and 11 are obtained by a buried diffusion layer conductor as described below. Further, the local virtual ground line 12 is also obtained by the embedded diffusion layer. Many floating gate transistors having a gate, drain and source are coupled to local bit lines 10, 11 and local virtual ground line 12. The sources of the majority of transistors are coupled to the local virtual ground line 12. The drain of the transistor in the first column indicated by 13 is the second! And the drain of the second column of transistors, indicated at 14, is coupled to the second local bit line 11. The gate of the floating 'gate transistor is coupled to word lines WL0 through WLN. Here, each word line (for example, WLl) is connected to the first column of transistors (for example, transistors). 1 5) and coupled to the gates of the second row of transistors (eg, transistor 16). Thus, transistors 15 and 16 can be thought of as a cell consisting of two transistors sharing a source diffusion layer.
[0015]
The operation of charging the floating gate is called the flash EPROM cell program step. This can be done by hot electron injection by applying a positive voltage as great as 12 volts between the gate and source and a positive voltage of 6 volts between the drain and source.
The operation of discharging the floating gate is called the erase step of the flash EPROM cell. This is done by the FN tunnel mechanism (source erase) between the floating gate and the source or the FN tunnel mechanism (channel erase) between the floating gate and the semiconductor substrate. Source erase is done by grounding the gate or biasing it negatively as low as -8 port and applying a positive bias as high as 12 volts or 8 volts to the source. Channel erase is performed by applying a negative bias to the gate and / or applying a positive bias to the semiconductor substrate.
[0016]
As shown in FIG. 1, the first wide area bit line 17 and the second wide area bit line 18 are associated with cells of each drain-source-drain circuit configuration. The first wide area bit line 17 is coupled to the source of the upper block select transistor 19 via a metal diffusion contact 20. Similarly, the second wide area bit line 18 is coupled to the source of the upper block select transistor 21 via a metal diffusion contact 22. The drains of the upper block select transistors 19 and 21 are coupled to the first and second local bit lines 10 and 11, respectively. The gates of the upper block select transistors 19 and 21 are controlled by a block select signal TBSEL applied to the line 23.
[0017]
The local virtual ground line 12 is coupled through a lower block select transistor 25 through a conductor 24 to a virtual ground terminal. The drain of the lower block select transistor 25 is coupled to the local virtual ground line 12. The source of the lower block select transistor 25 is coupled to the conductor 24. The gate of the lower block select transistor 25 is controlled by a lower block select signal BBSEL applied to line 26. In the system proposed by the present invention, the conductor 24 is a conductor with an embedded diffusion layer, which extends horizontally through the array to the metal diffusion contact. This metal-diffusion contact makes contact with a vertically extending metal virtual ground bus.
[0018]
Wide area bit lines 17 and 18 extend vertically through the array to respective column select transistors 27 and 28. Transistors 27 and 28 couple the select wide bit line to a sense amplifier and program data circuit (not shown). Thus, the source of the column select transistor 27 is coupled to the global bit line 17, the gate of the column select transistor 27 is supplied with the column decode signal Yl, and the drain of the column select transistor 27 is connected to the conductor 29. Are combined.
[0019]
A large number of subarrays shown in FIG. 2 are constituted by blocks of the flash EPROM cell shown in FIG. FIG. 2 illustrates two subarrays of the entire IC. The subarray is divided along the alternate long and short dash line 50, and has a subarray 51 </ b> A at the upper part and a subarray 51 </ b> B at the lower part. The first block 52 is arranged with respect to the second block 53 along the bit lines (for example, the bit lines 70 and 71). Above and below the pair of bit lines 70, 71, these memory subarrays share the metal diffusion contacts 55, 56, 57, 58, and are like virtual ground conductors 54A, 54B (embedded or diffusion layers). It is divided into. The virtual ground conductors 54A, 54B extend horizontally beyond the array to the virtual ground'metal line 59 disposed vertically through the metal diffusion contacts 60A, 60B. The sub-array is formed on the opposite side of the metal / virtual ground line 59 so that adjacent sub-arrays share the metal virtual ground line 59. The metal virtual ground line 59 is coupled to the array ground and erase high voltage circuit via a virtual ground select transistor 79 controlled by a decode signal ZN. Virtual ground select transistor 79 can be used to isolate the array region sharing metal line 59 from high voltage erase. Thus, the arrangement of the subarrays includes two metal contact pitches per column of two transistor cells for the global bit lines and one metal contact per subarray for the metal virtual ground lines 59. A pitch is required.
[0020]
Further, the two subarrays shown in FIG. 2 may share word line signals since additional decoding is provided by block select signals TBSELA, TBSELB, BBSELA and BBSELB at their top and bottom, respectively. it can.
In one proposed system, each subarray consists of 8 blocks, consisting of 32 pairs of transistor cells and columns of word lines, 512 cell subarrays, a total of 16 wide area bits. There are lines and 32 word lines. As can be seen, the device according to the invention can form a sector flash EPROM array. This is advantageous because during the read, program or erase cycle, the source and drain of the transistors in the unselected subarray are isolated from the current and voltage applied to the bit lines and virtual ground lines. Thus, during a read operation, the read operation is improved because the leakage current from the unselected subarray is not related to the current applied to the bit line. During the program and erase operations, the high voltage of the virtual ground line and the bit line are separated from the unselected block. This allows a sector erase operation.
It can be determined that the lower block select transistors (eg, transistors 65A, 65B) are not required in some implementations. Also, these block select transistors can share a lower block select signal with adjacent subarrays, as illustrated below with respect to FIG. Alternatively, the lower block select transistors (eg, 65A, 65B) can replace the adjacent virtual ground evening terminals 60A, 60B with a single isolation transistor.
[0021]
FIG. 3 is a block diagram showing an outline of a flash EPROMIC according to the present invention. The flash EPROMIC has the memory array 100 shown in FIG. 2 and is provided in the system so that a large number of extra cells 101 can be replaced by a damaged memory array. In addition, the circuit includes a number of reference cells 102, a sense amplifier, a program data input circuit, a block 103 containing array ground and erase high voltage circuits, a block 104 containing word lines and a block select decoder, and A block 105 including a column decoder and a virtual ground decoder is provided. The reference cell 102 is coupled to a sense amplifier in block 103 for counting channel length changes, such as occurring during fabrication or reflected in the voltage and current applied to the bit line being read. . Reference cell 102 can also be used to generate programming and erase voltages. This redundant cell device is made possible by the split configuration of the flash EPROM array as discussed above.
The word line and block select decoder 104 array and virtual ground decoder 105 can be programmed after testing redundant cells to replace non-operating cells in the memory array 100. In addition, the circuit includes a mode control circuit 106 for controlling virtual ground, drain and word line voltages used during erase, program and read operations, and various operations.
[0022]
The flash EPROM cell according to the present invention and the method of manufacturing the cell used in the above-described circuit are shown in cross-sectional views according to FIGS. 4A to 4D and FIGS. 5A to 5D, and FIGS. It is shown. FIG. 8 is a plan view thereof.
A first cell type embodiment is illustrated in FIGS. 4A-4D and 5A-5D. The manufacturing process of the cell shown in this sectional view is an outline. FIG. 4A illustrates the first step process. To make an N-channel cell, P ^- A type Si semiconductor substrate 100 is prepared, and relatively thick field oxide regions 101 and 102 grown in a vertical direction are generated by a well-known LOCOS field oxidation process. Further, a thin oxide film 103 is formed on the main surface of the semiconductor substrate around the field oxides 101 and 102.
In the next step, as illustrated in FIG. 4B, a photoresist mask 104 is deposited between the field oxides 101, 102, which is essentially parallel to the field oxide regions 101, 102. Extends along. This defines a drain diffusion region between the field oxide 101 and the photoresist mask 104 and between the field oxide 102 and the photoresist mask unit 04. N-type dopants are ion implanted into the semiconductor substrate 100 through the thin oxide film 103 as schematically indicated by the arrows. Thus, the drain diffusion region is self-aligned by the element isolation field oxides 101 and 102.
[0023]
In the next step, as shown in FIG. 4C, the photoresist mask 104 is removed and the N-type dopant implanted into the semiconductor substrate 100 is annealed to form the active to form the local bit lines 105 and 106. Turn into. Further, drain oxides 107 and 108 are generated so as to cover the diffusion bit lines 105 and 106. FIG. 4D illustrates the next step in cell fabrication. In particular, a thin oxide 103 is removed by a blank wet etch and a tunnel oxide 110 is created between the drain diffusion bit lines 105,106. The thickness of the tunnel oxide film 110 is approximately 100 angstroms in the system of this embodiment. However, the tunnel oxide film 110 is about 120 angstroms or less in the flash EPROM cell. Thicker oxide films can be used for non-volatile cells such as UV-EPROM cells, but such thick oxide films are not used for tunnel oxide films for erase operations.
The oxide films 107 and 108 above the bit lines 105 and 106 due to the buried diffusion layer are about 1000 angstroms thick in this step.
[0024]
The next step shown in FIG. 5A is a step of depositing a first layer of a poly-Si layer 111 and doping an impurity element to make this poly-Si a conductor. Then, an oxide / nitride / oxide (ONO) layer 112 is created to provide a control gate dielectric on the first poly-Si layer 111. The poly-Si layer 111 by this step is about 1500 angstroms thick and the ONO layer is about 250 angstroms thick.
In FIG. 5B, a self-aligned source diffusion region is defined using a photomask process. After the photo mask process, the poly-Si layer 111 and the ONO insulating layer 112 are etched to expose the source diffusion region. Also, the floating gate poly-Si layer 111 and the ONO layer 112 are etched to define the width of the floating gate. Thus, one of the etched poly-Si layers 111 defines the source diffusion region and the other defines the width of the floating 'gate. In this embodiment, the latter is located on top of the field oxide region 101 or 102.
Thereafter, the source diffusion region extends in parallel with the drain diffusion regions 105 and 106. ⁺ / N ^- An N-type dopant is ion-implanted to form a double-diffused diffusion region. The dopant used is a combination of phosphorus and arsenic to form a double diffusion.
[0025]
As shown in FIG. 5C, the photoresist is removed and the semiconductor substrate is annealed. N ⁺ And N ^- The source diffusion region 115 is activated by diffusing and annealing the dopant. A source oxide film 116 is formed, and the oxide film 117 is formed along the side surface of the floating gate poly-Si layer 111 for separating the floating gate from a word line / poly-Si layer to be defined later. Generated.
FIG. 5D illustrates the next step in the manufacturing process of the flash EPROM cell. This includes depositing the second poly layer 118 and using a photomask process to define the word lines. In the photomask process, the etch that defines the word line is continued up to the floating gate poly-Si layer 111 to define the floating gate of each transistor. Word line 118 is approximately 4,500 angstroms thick. Finally, a passivation and metallization layer (not shown) is deposited on top of the cell.
[0026]
As shown in FIG. 5D, the first transistor is formed between the drain diffusion line 105 and the source diffusion line 115, and the second transistor is formed between the drain diffusion line 106 and the source diffusion line 115, respectively. A structure is obtained. The floating gate extends from the source diffusion line 115 across the drain diffusion line 105 and over the field oxide 101. In this embodiment, these floating gate oxides are approximately 2.4 microns long and 0.8 microns wide. On the other hand, the width of the tunnel oxide film 110 from one end of the drain oxide film 107 to one end of the source oxide film 116 in the upper part of the transistor is about 1.2 microns. The redundant region covering the drain diffusion line 105 and the field oxide 102 is used to increase the coupling ratio by a floating gate to a magnitude of about 50% or more. Because the ONO layer is about 250 angstroms thick and the tunnel oxide is about 100 angstroms thick, the coupling ratio must be improved by increasing the floating gate area. It is. Alternatively, the ONO layer may be made thinner to reduce the area required for the floating gate.
As will be appreciated, source diffusion is performed in a step independent of drain diffusion, and ion implantation is performed with a dopant with a different distribution to create a graded junction in the channel of each transistor to facilitate the source erase function. Is done. In channel erase type or UV erase type floating gates, no graded junction and source or diffusion are required.
[0027]
Next, FIGS. 6A to 6D and FIGS. 7A to 7C show sectional views of a second cell type embodiment according to the present invention. As illustrated in FIG. 6A, the first step is to generate field oxides 201, 202 as described in FIG. 4A. Unnecessary oxide film Generation The oxide film is removed to prepare a semiconductor substrate 200 for generating a tunnel oxide film. As shown in FIG. 6B, a thin tunnel oxide 203 is formed to a thickness of about 100 Å. In the next step of FIG. 6C, a poly-Si layer is deposited and doped with a dopant to produce a 120 Å thick ONO layer 205 so that the coupling ratio is greater than about 50%. A thicker oxide film 203 and ONO layer 205 are used in the UV-EPROM cell.
In FIG. 6D, a photo mask process is used to define the source and drain diffusion regions of the floating gate and N + layer. Thus, photo mask layers 206 and 207 are defined to protect the floating gate region. The poly Si layer 204 and the ONO 205 layer are etched except for the portions covered by the masks 206 and 207 to expose the drain, source and drain regions. N-type dopant is then ion implanted into the exposed region as illustrated by arrow 208. These regions are formed by self-alignment with a floating gate and a field insulating region.
The flash EPROM array is illustrated in the next step, FIG. 7A. According to this step, masks 210 and 211 are used in which the photo mask process covers the drain region and the element isolation region. In this step, N-type dopants are ion implanted as represented by arrow 212, and the source region will have N + and N-type dopants to form a graded junction. Note that the step in FIG. 7A can be omitted in the description of the manufacturing method of the UV erasing EPROM cell.
[0028]
As illustrated in FIG. 7B, the semiconductor substrate is annealed to activate the dopant and defines drain diffusion regions 213 and 214 and source diffusion region 215. Also, the drain oxide film 2 1 6 and 217 and the source oxide film 218 are formed to cover the side surfaces of the floating gate poly-Si.
Finally, as shown in FIG. 7C, a second poly-Si layer 219 is deposited and etched to define the transistor. In this embodiment, the ONO sandwich 205 has a thickness within ± 20% of the thickness of the tunnel oxide film, so the coupling ratio is high (in the range of about 40% to 60%, preferably about 50%). %), It is not necessary to use a floating gate extending over the drain and field isolation regions. Finally, a passivation and metallization layer (not shown) is applied to the device of FIG. 7C.
Thus, as seen in FIG. 7C, the cell structure according to the second type has the first transistor between the buried drain diffusion region 213 and the buried source diffusion region 215, and the second transistor between the buried drain diffusion region 215. It is formed between the diffusion region 214 and the buried source diffusion region 215. Each transistor has a floating gate made of a first poly-Si layer 204. The floating gate is insulated from the channel region of each transistor by the tunnel oxide film 203 and from the control gate in the word line / poly-Si layer 219 by the ONO layer 205. In the ONO layer 205, the thickness of the tunnel oxide film 203 is within a range of about ± 20% in order to ensure a sufficiently high coupling ratio for the flash EPROM operation.
[0029]
The thickness of the ON layer 205 in the cell types shown in FIGS. 6A to 6D and FIGS. 7A to 7C is sufficiently thin, so that the surface area of the floating gate is as shown in FIGS. 4A to 4D and FIGS. There is no need to extend as was done in the first type of cell structure illustrated in FIG. 5D.
Further, in the structure shown in FIG. 7C, the first and second drain diffusion regions 213 and 214 and the source diffusion region 215 are all floating by the first poly-Si layer 204 and the ONO insulating layer 205.・ Self-aligned with gate structure. This demonstrates that the channel length of each transistor is substantially equal.
[0030]
FIG. 8 shows a layout of the sub-array of the EPROM cell IC shown in FIGS. It is clear that this arrangement is substantially the same for the cell shown in FIG. 7C, except for the size of the floating gate. As can be seen in FIG. 8, the IC has a number of isolation regions 300-302 extending vertically through the subarray. These isolation regions correspond to the thick oxide film 10L102 illustrated in FIG. 5D. These field oxide films 300 and 301 define an isolation region, and there is a region 303 between them. In the region where the element is isolated, the diffusion line 105 of FIG. 1 There are a first buried diffusion line 304 and a second buried diffusion line 305 in the shape of a band corresponding to 06. Between the strip-shaped buried diffusion lines, there is a source diffusion line 306 corresponding to the diffusion line 115 of FIG. 5D. A number of word lines 307-309 traverse the isolation region that defines the control gates of the array device floating gate transistors. A floating gate (eg, see notch 310) covers the semiconductor substrate between the tunnel oxide and each word line.
[0031]
An upper select transistor is coupled to each of the buried diffusion lines 304, 305 defined by the local bit lines. For example, a block select transistor in the notched region 311 is coupled to a metal line (not shown) by a drain 312 coupled to an extended buried diffusion region 304 and a metal diffusion contact 314. A source 313 is included. The metal line extends parallel to the isolation region 300 at the top of the sub-array. Similarly, the second buried diffusion line 305 is coupled to the drain 315 of the upper select transistor. The transistor has a source 316 coupled to a metal diffusion contact 317 and coupled to a vertically extending metal line (not shown) that acts as a global bit line through the contact. The gate of the upper block select transistor is set by an upper select word line 318 that extends horizontally across the array. The upper block select transistor that couples the local bit line 304 to the metal diffusion contact 314 includes a field oxide region 319 from the block select transistor that couples the local bit line 305 to the metal-diffusion contact 317. Separated by. In this way, the transistors in each column can be selected independently for read and program operations.
[0032]
Local source diffusion 306 is coupled to a lower block select transistor having a buried diffusion source 320 and a buried diffusion drain 321. The buried diffusion drain is a conductor consisting of a strip of buried diffusion layer that extends horizontally across the array to the metal diffusion contact 322. The metal diffusion contacts are in turn coupled to a metal line 323 that provides a virtual ground voltage to the array. The lower block select transistor is controlled by a select line 324 in the poly-Si layer. As will be appreciated, the poly Si layer select line 324 is shared with the sub-array depicted in the figure and the sub-array 325 below the figure. The subarray 325 has a block select source region 326 that shares a buried diffusion drain 321 that connects the subarray to the virtual ground bus. Thus, the bottom block select signal of the poly-Si layer is supplied to the source region 326 in the second subarray 325 across the wide structure 324 extending from the source region 320 of the first subarray. In this manner, the bottom block select signal works so that the local virtual ground diffusion 306 can act on the subarrays on both sides of the drain diffusion region 321.
[0033]
Of course, other implementations may be implemented where the bottom block select signal is individually controlled for each subarray that requires a separate block select signal on the word line 324. In the above embodiment, the lower block select transistor can also be embodied such that there is one for each buried diffusion line in a manner similar to the upper block select transistor. In another embodiment, the lower block select transistor can be replaced with a conductor having one isolated transistor near the metal diffusion contact 322 that controls a number of local virtual ground bit lines. Element Isolation Region For example, the element isolation region 301 periodically extends through the lower block select source region 320 and the drain region 321 and isolates the lower block select transistor of the adjacent subarray.
As can be appreciated, the virtual ground metal bus 323 extends vertically beyond the figure. The bus 323 is coupled to the lower block select transistor by a metal-diffusion contact 322.
[0034]
The isolation region 301 separates the subarray on both sides of the field oxide 301 by isolating the lower block select transistor. As shown in FIG. 6, the sub-array thus has four (for example) columns of transistors 350, 351, 352, 353 that commonly share the lower block select transistor in region 354. A preferred system may have 16 columns of transistors (8 blocks with 2 transistor cells) per subarray. The transistors formed by diffusion regions 304, 305 will thus be in a separate subarray from the transistors in columns 350 and 351. The transistor to the right of the virtual ground metal line 323 will also be in a separate subarray. The shared lower block select transistor is controlled by the block signal applied to line 324, so it has four sub- A The arrays (two on each side of the metal 324) have their source diffusion regions, eg, 359, coupled to a virtual ground bus 323 that responds to the signal on line 324. This results in a sector erase for four subarrays at a time.
[0035]
In the present invention, the N channel of the flash EPROM array has been described. However, it is obvious that the P channel can be easily realized.
Further, the embodiments disclosed in the present invention and the description thereof are for explaining the present invention, and do not disclose all the gist of the present invention. Accordingly, it is not intended that the invention be limited to the disclosed embodiments, which may have been chosen in order to best explain the principles of the invention and its practical application and may be found in numerous modifications. It is clear that citations and variations can be made by experienced technicians.
[0036]
【The invention's effect】
As described above, the non-volatile memory cell and array device of the present invention can provide a flash EPROM cell composed of a novel floating gate transistor, its array device, and its memory circuit. It is as follows.
1. Two adjacent local drain bit lines share one source bit line, and one metal source bit line is formed parallel to all sub-arrays of the cell, The contactless structure provides an effect of obtaining a very dense nonvolatile memory core array.
2. Sector erasing has the advantage that it can be realized by using a separable array device constituted by floating gate transistors according to the present invention.
3. The non-volatile memory cell using the novel floating gate transistor of the present invention has an advantage that a flash memory array and a memory circuit having high operation and high reliability can be obtained.
[0037]
Furthermore, the non-volatile memory cell and array device of the present invention can provide flash EPROM cells and the device can be adapted to various memory circuit arrays. Thus, it is apparent that the storage cells in the memory array can be ROM, PROM / EPROM / UV erase EPROM, or other EPROM.
Further, it will be appreciated that the flash EPROM disclosed herein is for the purpose of a source erase operation and can be adapted to a channel erase operation if desired.
[Brief description of the drawings]
FIG. 1 is a circuit diagram for explaining a nonvolatile memory cell according to the present invention;
FIG. 2 is a circuit diagram illustrating an outline of an array device using nonvolatile memory cells according to the present invention, which is illustrated by two subarrays.
FIG. 3 is a block diagram showing an embodiment of a semiconductor integrated circuit using a nonvolatile memory cell according to the present invention.
FIGS. 4A to 4D are diagrams illustrating a method of manufacturing a nonvolatile memory cell according to an embodiment, and a cross section taken along a word line of an array device using the nonvolatile memory cell according to the present invention; FIG.
FIGS. 5A to 5D are cross-sectional views illustrating a method for manufacturing a nonvolatile memory cell following FIGS. 4A to 4D. FIGS.
FIGS. 6A to 6D are diagrams illustrating a method of manufacturing another embodiment of a nonvolatile memory cell, along a word line of an array device using the nonvolatile memory cell according to the present invention. FIGS. It is sectional drawing.
FIGS. 7A to 7C are cross-sectional views illustrating a method for manufacturing a nonvolatile memory cell following FIGS. 6A to 6D. FIGS.
8 is a plan view of an array device using nonvolatile memory cells obtained by the manufacturing method of FIGS. 4 (A) to (D) and FIGS. 5 (A) to (D). FIG.
[Explanation of symbols]
10 first local bit line
11 Second local bit line
12 Local virtual ground line
13, 15 transistors in the first row
14, 16 Second row transistors
17 First wide area bit line
18 Second wide area bit line
19, 21 Upper block select transistor
20,22 Metal diffusion contact
23, 26 lines
24, 29 conductors
25 Lower Block Select Transistor
27, 28 column select transistor
WL ₀ ~ WL _N Word line

Claims (13)

Defining a number of drain diffusion regions extending in a first direction, including first and second diffusion regions;
Doping the first and second drain diffusion regions;
Providing a first insulating material on the main surface of the semiconductor substrate at least in a region adjacent to the drain diffusion region;
Providing a floating gate conductive material covering at least the first insulating material in a region adjacent to the drain diffusion region;
Providing a control gate insulating material to cover the floating gate conductive material;
Exposing a source diffusion region extending through the floating gate conductive material on the semiconductor substrate aligned with the floating gate conductive material, the extended source diffusion region being a first extended source; A first extended source diffusion region, the first extended source diffusion region being spaced apart from the first drain diffusion region, the first channel region being separated from the first extended source diffusion region and the first drain diffusion region; Providing a second channel region spaced from the second drain diffusion region and between the first extended source diffusion region and the second drain diffusion region;
Doping the source diffusion region, which is performed separately from the drain diffusion doping step;
Providing an insulating layer covering the source diffusion region and the exposed floating gate conductive material, and forming a plurality of conductive material rows covering the control gate insulating material and the floating gate conductive material; A method of manufacturing a contactless floating gate memory array device comprising:   A step of exposing a number of extended source diffusion regions was provided spaced from the first side to define the width of the first side defining one side of the source diffusion region and the floating gate region. Defining an extended floating gate region having a second side and etching the floating gate conductive material such that the floating gate region is over at least a portion of the adjacent drain diffusion region. 2. The method of manufacturing a contactless floating gate memory array device according to claim 1, further comprising:   The method of claim 2, wherein the second side of the floating gate region is defined to be over an adjacent drain diffusion region.   2. The method of manufacturing a contactless floating gate memory array device according to claim 1, wherein the first insulating material is made of silicon dioxide.   5. The method of manufacturing a contactless floating gate memory array device according to claim 4, wherein the control gate insulating material is made of ONO.   2. The method of manufacturing a contactless floating gate memory array device according to claim 1, wherein the first insulating material is made of silicon dioxide having a film thickness of less than 120 angstroms.   The first insulating material is silicon dioxide having a thickness that does not reach the floating gate conductive material, and the control gate insulating material has an ONO with a thickness substantially greater than the thickness of the tunnel insulating material. The method of manufacturing a contactless floating gate memory array device according to claim 1, comprising:   The method of manufacturing a contactless floating gate memory array device according to claim 1, wherein the step of doping the source diffusion region sets the distribution of the dopant so as to have an inclined junction. Forming a number of insulating regions extending in the first direction on the main surface of the semiconductor substrate;
Forming a number of insulating regions extending in the first direction and spaced apart;
A plurality of drain diffusion regions including first and second diffusion regions extending in a first direction having at least two drain diffusion regions within each of the isolation regions in the plurality of isolation regions; Defining,
Doping the first and second drain diffusion regions;
Providing a first insulating material on the semiconductor substrate at least in a region adjacent to the drain diffusion region;
Providing at least a floating gate conductive material covering the first insulating material in a region adjacent to the drain diffusion region;
Providing a control gate insulating material to cover the floating gate conductive material;
Exposing a source diffusion region extending through the floating gate conductive material on the semiconductor substrate aligned with the floating gate conductive material, the extended source diffusion region being a first extended source; A first extended source diffusion region, the first extended source diffusion region being spaced apart from the first drain diffusion region, the first channel region being separated from the first extended source diffusion region and the first drain diffusion region; Providing a second channel region spaced from the second drain diffusion region and between the first extended source diffusion region and the second drain diffusion region;
Doping the source diffusion region, which is performed separately from the drain diffusion doping step;
Providing an insulating layer covering the source diffusion region and any exposed floating gate conductive material, and forming a plurality of conductive material rows covering the control gate insulating material and the floating gate conductive material; A method of manufacturing a floating gate memory array, comprising: Before the step of defining a drain diffusion region, the step of forming a plurality of insulating regions in a first direction Mashimasu extending to that board on provided, a large number of separate board that Mashimasu extending in a first direction 2. A method according to claim 1, characterized in that they are spaced apart to define a defined area.   2. The drain diffusion doping step is performed before the step of forming the floating gate conductive material, and the source diffusion doping step is performed subsequent to the step of forming the floating gate conductive material. the method of.   2. The invention of claim 1, wherein the drain diffusion and source diffusion steps are performed subsequent to the step of forming a floating gate conductive material.   2. The invention of claim 1, wherein the source diffusion region is doped in both the drain diffusion and source diffusion doping steps.

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