CN105161492A - Floating gate flash memory structure and preparation method thereof - Google Patents
Floating gate flash memory structure and preparation method thereof Download PDFInfo
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- CN105161492A CN105161492A CN201510470922.3A CN201510470922A CN105161492A CN 105161492 A CN105161492 A CN 105161492A CN 201510470922 A CN201510470922 A CN 201510470922A CN 105161492 A CN105161492 A CN 105161492A
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Abstract
The invention relates to the technical field of semiconductor manufacture and especially relates to a floating gate flash memory structure and a preparation method thereof. The structure includes a substrate layer comprising a first active layer, a channel layer and a second active layer arranged successively from bottom up. The structure also includes a groove penetrating the second active layer and the channel layer and extending to the first active layer and a floating gate structure arranged in the groove and including a control gate and at least two floating gates. One end part of the floating gate structure extends to the first active layer while the other end part is adjacent to the second active layer, so that a vertical channel is formed in the channel layer. Besides, the control gate and each floating gate form a storage unit, so that the storage density of the floating gate storage device can be improved effectively in the premise of not reducing channel length and drain/source electrode width. Moreover, since the control gate is shared, the device size is reduced further.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of floating gate flash memory structure and preparation method thereof.
Background technology
The feature of nonvolatile memory is, when power supply brief interruption or device are in off-position indefinitely, still can keep the information stored for a long time.Desirable nonvolatile memory should meet low cost, high density, the requirement such as arbitrary access, low-power consumption fast.At 20th century the mid-80, the new technology of one is called as " quick flashing " memory (Flash) is developed, its low cost and programme fast, erasing ability makes it become the leading force in semiconductor device market fast.And the density of data storage and every cost are the necessary conditions promoting memory development.
At present, the substrate of traditional floating gate type flash memory adopts standard MOSFET architectures.Substantially be all horizontal channel and leakage/floating boom/source, the device of this structure needs extra region to leakage/source, thus have impact on the storage density of device, want the storage density improving this device, generally need the width reducing channel length and leakage/source, but short-channel effect and drain-source breakdown voltage step-down can be brought; This is that those skilled in the art are reluctant to see.
Summary of the invention
For above-mentioned Problems existing, the present invention discloses a kind of floating gate flash memory structure, comprising:
Substrate layer, comprises the first active layer, channel layer and the second active layer according to sequentially setting gradually from bottom to up;
Groove, runs through described second active layer, described channel layer extend in described first active layer;
Floating gate structure, is arranged in described groove, and an end of described floating gate structure extends in described first active layer, and the other end of described floating gate structure is closed on described second active layer and arranged, to form vertical-channel in described channel layer;
Wherein, described floating gate structure comprises control gate, ONO layer and at least two floating booms, and the sidewalls orthogonal that each described floating boom all closes on described groove runs through described channel layer in the direction that described channel layer extends and extends among described first active layer, described control gate to be arranged in described groove central region and to be arranged in parallel with described floating boom and run through described channel layer, described control gate and each described floating boom are all isolated by described ONO layer, are all formed a memory cell to make described control gate and each described floating boom.
Above-mentioned floating gate flash memory structure, wherein, described floating gate flash memory structure also comprises the first oxide layer covering described groove inner wall, closes between the described floating gate structure of described groove inner wall and described substrate layer by described first oxide layer isolation.
Above-mentioned floating gate flash memory structure, wherein, the conduction type of described first active layer and described second active layer is N-type, and the conduction type of described channel layer is P type.
Above-mentioned floating gate flash memory structure, wherein, the upper surface flush of described floating boom and described control gate.
Above-mentioned floating gate flash memory structure, wherein, described floating gate flash memory structure also comprises sidewall structure, and described sidewall structure covers the upper surface of described floating boom and described groove and is positioned at sidewall on described floating boom.
Above-mentioned floating gate flash memory structure, wherein, described floating gate flash memory structure also comprises the second oxide layer, and described second oxide layer covers the upper surface of described second active layer, described sidewall structure, described ONO layer and described control gate.
Present invention also offers a kind of preparation method of floating gate flash memory structure, comprise the steps:
There is provided a tool reeded semiconductor structure, described semiconductor structure comprises first substrate layer with the first conduction type set gradually according to order from bottom to up, second substrate layer with the second conduction type, the first oxide layer and is positioned at the second oxide layer of described bottom portion of groove;
In the sidewall growth tunneling oxide layer of described groove, and form floating gate polysilicon layer on described second oxide layer, and the upper surface of described floating gate polysilicon layer is lower than the upper surface of described second substrate layer;
Form the sidewall structure covering described floating gate polysilicon layer upper surface both sides respectively, covered with the sidewall that described groove is exposed;
With described sidewall structure for floating gate polysilicon layer described in mask etching forms at least two floating booms;
Between described at least two floating booms, form ONO layer and be arranged in groove central region and the control gate be arranged in parallel with described floating boom, and each described floating boom and described control gate are by described ONO layer isolation;
Carry out ion doping to form the 3rd substrate layer with the first conduction type in the top of described second substrate layer.
The preparation method of above-mentioned floating gate flash memory structure, wherein, described semiconductor structure also comprises the silicon nitride layer covering described first oxide layer upper surface.
The preparation method of above-mentioned floating gate flash memory structure, wherein, the method forming described semiconductor structure comprises the steps:
The Semiconductor substrate that one has the first conduction type is provided;
In described Semiconductor substrate, grow one deck oxide form described first oxide layer;
The ion of the second conduction type is injected described Semiconductor substrate to be divided into described first substrate layer and described second substrate layer to described semiconductor substrate section;
The silicon nitride layer with opening is formed on described first oxide layer;
According to order from top to bottom with described silicon nitride layer be mask etches successively described first oxide layer, described second substrate layer be parked in described first substrate layer and form described groove;
Described second oxide layer is formed in described bottom portion of groove.
The preparation method of above-mentioned floating gate flash memory structure, wherein, described floating boom is concordant with the upper surface of described control gate.
The preparation method of above-mentioned floating gate flash memory structure, wherein, described first conduction type is N-type, and described second conduction type is P type.
The preparation method of above-mentioned floating gate flash memory structure, wherein, after described 3rd substrate layer of formation, described method also comprises: continue deposition oxide, to be covered by the upper surface of described control gate.
Foregoing invention tool has the following advantages or beneficial effect:
The invention provides a kind of floating gate flash memory structure and preparation technology thereof, run through the second active layer, channel layer extend in the groove in the first active layer to arrange and comprise the floating gate structure of control gate and at least two floating booms; One end of this floating gate structure extends in the first active layer, and the other end is closed on the second active layer and arranged, to form vertical-channel in channel layer; And this control gate and each described floating boom all form a memory cell, thus under the prerequisite of width that can not reduce channel length and leakage/source, the storage density of effective raising floating gate memory device, and due to shared control gate, thus reduce the size of device further.
Accompanying drawing explanation
By reading the detailed description done non-limiting example with reference to the following drawings, the present invention and feature, profile and advantage will become more apparent.Mark identical in whole accompanying drawing indicates identical part.Proportionally can not draw accompanying drawing, focus on purport of the present invention is shown.
Fig. 1 is the structural representation of floating gate flash memory in the embodiment of the present invention;
Fig. 2-13 is the flowage structure schematic diagrames of the method preparing floating gate flash memory structure in the embodiment of the present invention;
Figure 14 is the flow chart of the method preparing floating gate flash memory structure in the embodiment of the present invention.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment, the present invention is further illustrated, but not as limiting to the invention.
Embodiment one:
As shown in Figure 1, the present invention relates to a kind of floating gate flash memory structure, comprise substrate layer and be arranged on the groove in this substrate layer, this substrate layer comprises the first active layer 201, is positioned at the channel layer 202 on the first active layer 201 and covers the second active layer 203 of this channel layer 202 upper surface, and this groove runs through the second active layer 203, channel layer 202 extend in the first active layer 201, namely the bottom of this groove is arranged in the first active layer 201, this floating gate flash memory structure also comprises the floating gate structure be arranged in groove, one end of floating gate structure extends to (namely the one end part of floating gate structure is in the position that groove is arranged in the first active layer 201) in the first active layer 201, the other end of floating gate structure is closed on the second active layer 203 and is arranged, to form vertical-channel in channel layer 202, concrete, this floating gate structure comprises control gate 209, ONO layer 208 and at least two floating booms 206, and the sidewalls orthogonal that each floating boom 206 all closes on groove runs through channel layer 202 in the direction that channel layer 202 extends and extends among the first active layer 201, this control gate 209 to be arranged in described groove central region and to be arranged in parallel with floating boom 206 and run through channel layer 202, control gate 209 and each floating boom 206 are all isolated by ONO layer 208, a memory cell is all formed to make control gate 209 and each floating boom 206, namely some memory cell share a control gate, thus reduce device size further.
Fig. 1 illustrate only and arranges a floating gate structure in a groove, this floating gate structure comprises control gate 209, ONO layer 208 and two floating booms 206, and two or more floating gate structure also can be set according to the actual requirements in a groove, each floating gate structure also can comprise plural floating boom 206, only otherwise affect object of the present invention.
In the present invention's preferred embodiment, above-mentioned floating gate flash memory structure also comprises the first oxide layer 205 covering groove inner wall, closes between the floating gate structure of groove inner wall and substrate layer and is isolated by the first oxide layer 205.
In the present invention's preferred embodiment, the upper surface flush of above-mentioned floating boom 206 and control gate 209.
In the present invention's preferred embodiment, above-mentioned floating gate structure also comprises sidewall structure 207, and this sidewall structure 207 covers the upper surface of two floating booms 206, also covers above-mentioned groove simultaneously and is positioned at sidewall on two floating booms 206.
On this basis, further, the material of sidewall structure 207 is silicon nitride.
In the present invention's preferred embodiment, floating gate flash memory structure also comprises the second oxide layer 205, and this second oxide layer 205 covers the upper surface of the second active layer 203, sidewall structure 207, ONO layer 208 and control gate 209.
In the present invention's preferred embodiment, the conduction type of above-mentioned first active layer and the second active layer is N-type, the conduction type of above-mentioned channel layer is P type, to form the floating gate type flash memory of vertical-channel, thus under the prerequisite of width that can not reduce channel length and leakage/source, effectively improve the storage density of floating gate memory device.
The floating gate flash memory of this vertical-channel, when drain terminal adds high pressure, can produce hot carrier at drain terminal, then utilize the malleation of control gate that hot carrier is drawn in floating boom, thus realize the write of device; When control gate adds higher negative pressure, the electronics in floating boom will be pushed out, thus realize the erase feature of device.
Embodiment two:
The present embodiment relates to a kind of preparation method of floating gate flash memory structure, and the method specifically comprises the steps:
Step S1, provides the Semiconductor substrate 100 that has the first conduction type; Preferably, in an embodiment of the present invention, this Semiconductor substrate 100 for having the silicon chip of N-type conduction type, structure as shown in Figure 2.
Step S2, grows one deck oxide to form the first oxide layer 101 in Semiconductor substrate 100; And the ion injecting the second conduction type to Semiconductor substrate 100 part is to be divided into first substrate layer 1001 with the first conduction type and second substrate layer 1002 with the second conduction type, structure as shown in Figure 3 by Semiconductor substrate 100.
In the present invention's preferred embodiment, the ion of above-mentioned second conduction type is P type ion.
Step S3, forms the silicon nitride layer 102 with opening on the first oxide layer 101; In the preferred embodiment of the invention, on the first oxide layer 101, form the concrete technology with the silicon nitride layer 102 of opening is: first deposit the upper surface that one deck silicon nitride covers the first oxide layer 101; It is inferior to spin coating one deck photoresist above this layer of silicon nitride, and through overexposure and developing process, forms the photoresistance figure with opening; The photoresistance figure again having opening with this carries out dry etch process for mask, and the upper surface etching this layer of silicon nitride to the first oxide layer 101 stops forming the silicon nitride layer 102 with opening, structure as shown in Figure 4.
Step S4, a groove is formed with silicon nitride layer 102 for mask etches the first oxide layer 101, second substrate layer 1002 successively and is parked in the first substrate layer 1001 according to order from top to bottom, preferably, dry etch process is adopted to form this groove, structure as shown in Figure 5.
Step S5, the second oxide layer 103 is formed in bottom portion of groove, in the present invention's preferred embodiment, the method forming the second oxide layer 103 in bottom portion of groove is specially: deposition oxide on the semiconductor structure formed in above-mentioned steps S4, with cmp flatening process carried out to this oxide again and be parked on silicon nitride layer 102, then carry out oxide and return quarter, certain thickness oxide layer is left at bottom portion of groove, form this second oxide layer 103, in an embodiment of the present invention, the upper surface of this second oxide layer 103 is lower than the upper surface of the first substrate layer 1001, structure as shown in Figure 6.
Step S6, in the sidewall growth tunneling oxide layer 104 of groove, the technique of growth tunneling oxide layer 104 can adopt technique well-known to those skilled in the art, and at this, just it will not go into details, structure as shown in Figure 7.
Step S7, one deck polysilicon is deposited on the semiconductor structure that above-mentioned steps S6 is formed, and carry out chemical mechanical milling tech by after this layer of polysilicon grinding to silicon nitride layer 102 plane, carry out polysilicon and return quarter, form the floating gate polysilicon layer 105 of covering second oxide layer 103 upper surface, and the upper surface of floating gate polysilicon layer 105 is lower than the upper surface certain thickness (occurrence of this thickness can be set according to the actual requirements by those skilled in the art) of the second substrate layer 1002, wet-etching technology is adopted to remove silicon nitride layer 102 afterwards, structure as shown in Figure 8.
Step S8, form the sidewall structure 106 covering above-mentioned floating gate polysilicon layer 105 upper surface both sides respectively, covered with the sidewall that groove is exposed, in the present invention's preferred embodiment, the material of this sidewall structure 106 is silicon nitride, concrete, is full of groove in above-mentioned floating gate polysilicon layer 105 disposed thereon silicon nitride, partial etching silicon nitride afterwards, forms this sidewall structure 106; Structure as shown in Figure 9.
Step S9, with above-mentioned sidewall structure 106 for barrier layer, etching floating gate polysilicon layer 105, forms two floating boom 105 ＇ laying respectively at groove both sides, structure as shown in Figure 10.
Step S10, ONO layer 107 is formed between above-mentioned two floating boom 105 ＇, this ONO layer 107 covers sidewall, the sidewall of sidewall structure 106 exposure and the upper surface of the second oxide layer 103 that two floating boom 105 ＇ expose, because deposition forms the technique of this ONO layer 107 and the emphasis of non-invention improvement, at this, just it will not go into details, structure as shown in figure 11.
Step S11, in groove, depositional control room polysilicon layer is to being full of this groove, and adopt dry etch process this control room polysilicon layer to be returned the position formation control grid 108 carved to two floating boom 105 ＇ upper surface flush, the i.e. upper surface of control gate 108 and the upper surface flush of two floating boom 105 ＇, all lower than the second substrate layer 1002 certain thickness, and floating boom 105 ＇ and control gate 108 are isolated by ONO layer 107; Structure as shown in figure 12.
Step S12, ion doping is carried out to form the 3rd substrate layer 10022 with the first conduction type in the top of the second substrate layer 1002 to part second substrate layer 1002, namely the 3rd substrate layer 10022 is identical with the conduction type of the first substrate layer 1001, and continue at define the 3rd substrate layer 10022 semiconductor structure on deposition oxide, and carry out flatening process, form the 3rd oxide layer 109 of Coverage Control grid 108; Structure as shown in fig. 13 that.
In the present invention's preferred embodiment, the material of above-mentioned first oxide layer 101, second oxide layer 103, tunneling oxide layer 104 and the 3rd oxide layer 109 is silica.
Be not difficult to find, the present embodiment is the embodiment of the method corresponding with the embodiment of above-mentioned floating gate flash memory structure, and the present embodiment can be worked in coordination with the embodiment of above-mentioned floating gate flash memory structure and be implemented.The relevant technical details mentioned in the embodiment of above-mentioned floating gate flash memory structure is still effective in the present embodiment, in order to reduce repetition, repeats no more here.Correspondingly, the relevant technical details mentioned in present embodiment also can be applicable in the embodiment of above-mentioned floating gate flash memory structure.
To sum up, a kind of floating gate flash memory structure disclosed by the invention and preparation method thereof comprises substrate layer, and this substrate layer comprises the first active layer, channel layer and the second active layer according to sequentially setting gradually from bottom to up; Also comprise and run through the second active layer, channel layer the groove extended in the first active layer and the floating gate structure comprising control gate and at least two floating booms be arranged in groove, and an end of this floating gate structure extends in the first active layer, the other end is closed on the second active layer and is arranged, to form vertical-channel in channel layer; And control gate and each floating boom all form a memory cell, thus under the prerequisite of width that can not reduce channel length and leakage/source, effectively improve the storage density of floating gate memory device, and owing to sharing a control gate, thus reduce further device size.
It should be appreciated by those skilled in the art that those skilled in the art are realizing change case in conjunction with prior art and above-described embodiment, do not repeat at this.Such change case does not affect flesh and blood of the present invention, does not repeat them here.
Above preferred embodiment of the present invention is described.It is to be appreciated that the present invention is not limited to above-mentioned particular implementation, the equipment wherein do not described in detail to the greatest extent and structure are construed as to be implemented with the common mode in this area; Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or being revised as the Equivalent embodiments of equivalent variations, this does not affect flesh and blood of the present invention.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (12)
1. a floating gate flash memory structure, is characterized in that, comprising:
Substrate layer, comprises the first active layer, channel layer and the second active layer according to sequentially setting gradually from bottom to up;
Groove, runs through described second active layer, described channel layer extend in described first active layer;
Floating gate structure, is arranged in described groove, and an end of described floating gate structure extends in described first active layer, and the other end of described floating gate structure is closed on described second active layer and arranged, to form vertical-channel in described channel layer;
Wherein, described floating gate structure comprises control gate, ONO layer and at least two floating booms, and the sidewalls orthogonal that each described floating boom all closes on described groove runs through described channel layer in the direction that described channel layer extends and extends among described first active layer, described control gate to be arranged in described groove central region and to be arranged in parallel with described floating boom and run through described channel layer, described control gate and each described floating boom are all isolated by described ONO layer, are all formed a memory cell to make described control gate and each described floating boom.
2. floating gate flash memory structure as claimed in claim 1, it is characterized in that, described floating gate flash memory structure also comprises the first oxide layer covering described groove inner wall, closes between the described floating gate structure of described groove inner wall and described substrate layer by described first oxide layer isolation.
3. floating gate flash memory structure as claimed in claim 1, it is characterized in that, the conduction type of described first active layer and described second active layer is N-type, and the conduction type of described channel layer is P type.
4. floating gate flash memory structure as claimed in claim 1, is characterized in that, the upper surface flush of described floating boom and described control gate.
5. floating gate flash memory structure as claimed in claim 1, it is characterized in that, described floating gate flash memory structure also comprises sidewall structure, and described sidewall structure covers the upper surface of described floating boom and described groove and is positioned at sidewall on described floating boom.
6. floating gate flash memory structure as claimed in claim 1, it is characterized in that, described floating gate flash memory structure also comprises the second oxide layer, and described second oxide layer covers the upper surface of described second active layer, described sidewall structure, described ONO layer and described control gate.
7. a preparation method for floating gate flash memory structure, is characterized in that, comprises the steps:
There is provided a tool reeded semiconductor structure, described semiconductor structure comprises first substrate layer with the first conduction type set gradually according to order from bottom to up, second substrate layer with the second conduction type, the first oxide layer and is positioned at the second oxide layer of described bottom portion of groove;
In the sidewall growth tunneling oxide layer of described groove, and form floating gate polysilicon layer on described second oxide layer, and the upper surface of described floating gate polysilicon layer is lower than the upper surface of described second substrate layer;
Form the sidewall structure covering described floating gate polysilicon layer upper surface both sides respectively, covered with the sidewall that described groove is exposed;
With described sidewall structure for floating gate polysilicon layer described in mask etching forms at least two floating booms;
Between described at least two floating booms, form ONO layer and be arranged in groove central region and the control gate be arranged in parallel with described floating boom, and each described floating boom and described control gate are by described ONO layer isolation;
Carry out ion doping to form the 3rd substrate layer with the first conduction type in the top of described second substrate layer.
8. the preparation method of floating gate flash memory structure as claimed in claim 7, it is characterized in that, described semiconductor structure also comprises the silicon nitride layer covering described first oxide layer upper surface.
9. the preparation method of floating gate flash memory structure as claimed in claim 8, it is characterized in that, the method forming described semiconductor structure comprises the steps:
The Semiconductor substrate that one has the first conduction type is provided;
In described Semiconductor substrate, grow one deck oxide form described first oxide layer;
The ion of the second conduction type is injected described Semiconductor substrate to be divided into described first substrate layer and described second substrate layer to described semiconductor substrate section;
The silicon nitride layer with opening is formed on described first oxide layer;
According to order from top to bottom with described silicon nitride layer be mask etches successively described first oxide layer, described second substrate layer be parked in described first substrate layer and form described groove;
Described second oxide layer is formed in described bottom portion of groove.
10. the preparation method of floating gate flash memory structure as claimed in claim 7, it is characterized in that, described floating boom is concordant with the upper surface of described control gate.
The preparation method of 11. floating gate flash memory structures as described in any one of claim 7-10, it is characterized in that, described first conduction type is N-type, and described second conduction type is P type.
The preparation method of 12. floating gate flash memory structures as claimed in claim 7, is characterized in that, after described 3rd substrate layer of formation, described method also comprises: continue deposition oxide, to be covered by the upper surface of described control gate.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108447866A (en) * | 2018-03-06 | 2018-08-24 | 武汉新芯集成电路制造有限公司 | Floating-gate device and preparation method thereof |
| CN109216465A (en) * | 2018-09-20 | 2019-01-15 | 武汉新芯集成电路制造有限公司 | Floating gate type flash memory and preparation method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1189919A (en) * | 1995-07-05 | 1998-08-05 | 西门子公司 | Method of producing a read-only storage cell arrangement |
| US20070069275A1 (en) * | 2005-09-29 | 2007-03-29 | Felix Tsui | Bi-directional read/program non-volatile floating gate memory array, and method of formation |
| CN1979810A (en) * | 2005-12-06 | 2007-06-13 | 力晶半导体股份有限公司 | Non-volatile memory and production method |
| TW200802816A (en) * | 2006-06-27 | 2008-01-01 | Powerchip Semiconductor Corp | Non-volatile memory and manufacturing method thereof |
-
2015
- 2015-08-04 CN CN201510470922.3A patent/CN105161492A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1189919A (en) * | 1995-07-05 | 1998-08-05 | 西门子公司 | Method of producing a read-only storage cell arrangement |
| US20070069275A1 (en) * | 2005-09-29 | 2007-03-29 | Felix Tsui | Bi-directional read/program non-volatile floating gate memory array, and method of formation |
| CN1979810A (en) * | 2005-12-06 | 2007-06-13 | 力晶半导体股份有限公司 | Non-volatile memory and production method |
| TW200802816A (en) * | 2006-06-27 | 2008-01-01 | Powerchip Semiconductor Corp | Non-volatile memory and manufacturing method thereof |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108447866A (en) * | 2018-03-06 | 2018-08-24 | 武汉新芯集成电路制造有限公司 | Floating-gate device and preparation method thereof |
| CN108447866B (en) * | 2018-03-06 | 2019-03-26 | 武汉新芯集成电路制造有限公司 | Floating-gate device and preparation method thereof |
| CN109216465A (en) * | 2018-09-20 | 2019-01-15 | 武汉新芯集成电路制造有限公司 | Floating gate type flash memory and preparation method thereof |
| CN109216465B (en) * | 2018-09-20 | 2021-08-20 | 武汉新芯集成电路制造有限公司 | Floating gate type flash memory and manufacturing method thereof |
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