CN113410291A - Manufacturing method of shielded gate trench power device - Google Patents
Manufacturing method of shielded gate trench power device Download PDFInfo
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- CN113410291A CN113410291A CN202110672190.1A CN202110672190A CN113410291A CN 113410291 A CN113410291 A CN 113410291A CN 202110672190 A CN202110672190 A CN 202110672190A CN 113410291 A CN113410291 A CN 113410291A
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Abstract
The invention provides a manufacturing method of a shielded gate trench power device, which comprises the following steps: providing a substrate with an epitaxial layer, wherein a plurality of grooves are formed in the epitaxial layer, and the angle between the side wall of each groove and the surface of the substrate is 87-93 degrees; performing a wet oxygen oxidation process to form at least part of a first dielectric layer to cover the inner wall of the groove; forming a shielding grid in the groove; forming a second dielectric layer and a first gate oxide layer; forming a second gate oxide layer, wherein the second gate oxide layer covers the inner wall of the first gate oxide layer, and the bottom corner of the second gate oxide layer is arc-shaped; and forming a gate in the trench. The first dielectric layer is formed by utilizing a wet oxidation process, the problem that a vertical groove is difficult to fill is solved, electric field distribution is improved by utilizing the vertical groove, breakdown voltage is improved, the bottom corner of the first gate oxide layer is covered by utilizing the second gate oxide layer, the gate oxide thickness of the position is increased, electric leakage between gate sources is improved, loss is reduced, the body resistance of the epitaxial layer is reduced, the thickness of the epitaxial layer is reduced, and on-resistance is reduced.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a shielded gate trench power device.
Background
Due to the fact that the shielding grid groove structure has a charge coupling effect, a horizontal depletion layer is introduced on the basis of vertical depletion of a traditional groove power device, and the electric field of the device is changed from triangular distribution to approximately rectangular distribution. With the same doping concentration of the epitaxial specification, the device can obtain higher breakdown voltage, and the structure is widely applied.
With the reduction of the key technology node, that is, the size of the trench for forming the shield gate is reduced, the aspect ratio of the trench is further increased, so that a plurality of problems exist in the shield gate trench power device formed by continuously using the existing method, and the breakdown voltage of the shield gate trench power device cannot be increased or even is correspondingly reduced.
In a prior art shielded gate trench power device such as that shown in fig. 1, the opening of the trench 11 ' is enlarged to make the sidewall of the trench more inclined with respect to the surface of the substrate 10 ', thereby facilitating the filling of the dielectric layer 21 '. However, the bottom corners of the inclined trenches 11 ' and the gate 31 ' are protruded outwards (the dielectric layer 21 ' at the corners is recessed outwards), which results in uneven electric field distribution or weak points, resulting in lower breakdown voltage and larger leakage current. The inventors have tried to increase the bulk resistance of the epitaxial layer 10a ', i.e. greater than 0.15 ohm per cm (conventional range is greater than 0.15 ohm per cm), or increase the thickness of the epitaxial layer 10 a', i.e. greater than 7 μm (conventional range is greater than 7 μm), based on the above structure, to meet the requirement of the corresponding breakdown voltage, while at the same time, the on-resistance of the shielded gate trench power device is increased, and the loss is increased, so that the conventional shielded gate trench power device cannot achieve the compromise between the breakdown voltage and the on-resistance.
Disclosure of Invention
The invention aims to provide a manufacturing method of shielding grid groove power, which improves the breakdown voltage and reduces the on-resistance of the shielding grid groove power.
In order to solve the above technical problem, the present invention provides a method for manufacturing a shield gate trench power, including: providing a substrate, wherein an epitaxial layer is formed on the surface of the substrate, a plurality of grooves are formed in the epitaxial layer, the angle between the side wall of each groove and the surface of the substrate is 87-93 degrees, the thickness of the epitaxial layer is 3-9 microns, and the bulk resistance of the epitaxial layer is 0.01-0.2 ohm per centimeter; forming a first dielectric layer, wherein the first dielectric layer covers the inner wall of the groove and the surface of the substrate, and at least part of the first dielectric layer is formed by utilizing a wet oxygen oxidation process; forming a first conductive layer, wherein the first conductive layer fills the groove, and etching part of the first conductive layer to form a shielding grid by using the rest first conductive layer; forming a second dielectric layer and a first gate oxide layer, wherein the second dielectric layer covers the shielding gate, and the first gate oxide layer covers the side wall of the groove and the second dielectric layer; forming a second gate oxide layer, wherein the second gate oxide layer covers the inner wall of the first gate oxide layer, and the bottom corner of the second gate oxide layer is arc-shaped; and forming a gate in the trench.
Optionally, the shielded gate trench power device is a shielded gate trench MOSFET power device.
Optionally, an angle between the sidewall of the trench and the surface of the substrate is 87 ° to 90 °.
Optionally, the trench is formed by a deep trench etching process.
Optionally, the epitaxial layer is a single-layer epitaxial layer, the thickness of the single-layer epitaxial layer is 3 to 7 micrometers, and the bulk resistance is 0.05 to 0.15 ohms per centimeter.
Optionally, the epitaxial layer is a double-layer epitaxial layer and comprises a first epitaxial layer and a second epitaxial layer which are connected, the first epitaxial layer is far away from the surface of the substrate, the thickness of the first epitaxial layer is 1 mm-4 mm, the body resistance of the first epitaxial layer is 0.01 ohm per centimeter-0.1 ohm per centimeter, the second epitaxial layer is close to the surface of the substrate, the thickness of the second epitaxial layer is 2 mm-5 mm, and the body resistance of the second epitaxial layer is 0.1 ohm per centimeter-0.2 ohm per centimeter.
Optionally, a wet oxygen oxidation process is performed to form a first dielectric layer with a partial thickness, and then a CVD method is used to form the first dielectric layer with the remaining thickness.
Optionally, the forming method of the second dielectric layer comprises: forming a second dielectric layer and filling the groove; and etching back the second dielectric layer and the first dielectric layer, and removing the second dielectric layer and the first dielectric layer with set depth to partially expose the side wall of the groove.
Optionally, the first gate oxide layer is formed by a dry oxygen oxidation process.
Optionally, a PECVD method is used to form the second gate oxide layer.
In summary, the manufacturing method of the shielded gate trench power device provided by the invention has the following beneficial effects:
1) the first dielectric layer formed by the wet oxidation process covers the groove with the side wall vertical to the surface of the substrate, so that the problem that the vertical groove is difficult to fill is solved, the vertical groove is used for improving electric field distribution and improving breakdown voltage, and the second gate oxide layer covers the inner wall of the first gate oxide layer, particularly the bottom corner of the first gate oxide layer, so that the gate oxide thickness at the position is increased, the leakage between gate sources is improved, and the loss is reduced;
2) and on the basis that the power device of the shielding grid groove has high breakdown voltage, the body resistance of the epitaxial layer is reduced to 0.01 ohm per centimeter to 0.2 ohm per centimeter or the thickness of the epitaxial layer is reduced to 3 micrometers to 9 micrometers, so that the on-resistance of the power device of the shielding grid groove is reduced.
Drawings
It will be appreciated by those skilled in the art that the drawings are provided for a better understanding of the invention and do not constitute any limitation to the scope of the invention. Wherein:
FIG. 1 is a schematic diagram of a prior art shielded gate trench power device;
fig. 2a to fig. 2i are schematic structural diagrams corresponding to the manufacturing method of the shielded gate trench power device according to the embodiment of the present application;
fig. 3 is a flowchart of a method for manufacturing a shielded gate trench power device according to an embodiment of the present disclosure.
In fig. 1:
10' -a substrate; 10 a' -an epitaxial layer; 10 b' -a substrate; 11' -a trench; 21' -a dielectric layer; 22' -a shielding grid; 31' -a gate.
In fig. 2a to 2 i:
10-a substrate; 11-a trench; 10 a-an epitaxial layer; 10 b-a substrate; 21-a first dielectric layer; 22-a first conductive layer; 221-a shielding grid; 23-a second dielectric layer;
31-a first gate oxide layer; 311-bottom corner of first gate oxide layer; 32-a second gate oxide layer; 322-bottom corner of second gate oxide layer; 33-grid.
Detailed Description
To further clarify the objects, advantages and features of the present invention, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. It is to be noted that the drawings are in greatly simplified form and are not to scale, but are merely intended to facilitate and clarify the explanation of the embodiments of the present invention. Further, the structures illustrated in the drawings are often part of actual structures. In particular, the drawings may have different emphasis points and may sometimes be scaled differently.
As used in this application, the singular forms "a", "an" and "the" include plural referents, the term "or" is generally employed in a sense including "and/or," the terms "a" and "an" are generally employed in a sense including "at least one," the terms "at least two" are generally employed in a sense including "two or more," and the terms "first", "second" and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit to the number of technical features indicated. Thus, features defined as "first," "second," and "third" may explicitly or implicitly include one or at least two of the features unless the content clearly dictates otherwise.
The embodiment of the application provides a manufacturing method of a shielded gate trench power device, which is used for improving the breakdown voltage of the shielded gate trench power device and reducing the on-resistance of the shielded gate trench power device.
Fig. 3 is a flowchart of a method for manufacturing a shielded gate trench power device according to an embodiment of the present disclosure.
As shown in fig. 3, the method for manufacturing a shielded gate trench power device provided in this embodiment includes:
s01: providing a substrate, wherein an epitaxial layer is formed on the surface of the substrate, a plurality of grooves are formed in the epitaxial layer, the angle between the side wall of each groove and the surface of the substrate is 87-93 degrees, the thickness of the epitaxial layer is 3-9 microns, and the bulk resistance of the epitaxial layer is 0.01-0.2 ohm per centimeter;
s02: forming a first dielectric layer, wherein the first dielectric layer covers the inner wall of the groove and the surface of the substrate, and at least part of the first dielectric layer is formed by utilizing a wet oxygen oxidation process;
s03: forming a first conductive layer, wherein the first conductive layer fills the groove, and etching part of the first conductive layer to form a shielding grid by using the rest first conductive layer;
s04: forming a second dielectric layer and a first gate oxide layer, wherein the second dielectric layer covers the shielding gate, and the first gate oxide layer covers the side wall of the groove and the second dielectric layer;
s05: forming a second gate oxide layer, wherein the second gate oxide layer covers the inner wall of the first gate oxide layer, and the bottom corner of the second gate oxide layer is arc-shaped; and the number of the first and second groups,
s06: and forming a gate in the groove.
Fig. 2a to fig. 2i are schematic structural diagrams corresponding to corresponding steps of a manufacturing method of a shielded gate trench power device according to an embodiment of the present application, and the manufacturing method of the shielded gate trench power device according to the embodiment will be described in detail below with reference to fig. 2a to fig. 2 i.
The shielded gate trench power device may be a shielded gate trench MOSFET power device, or may also be a power device including a MOSFET structure, such as a MOS Controlled Thyristor (MCT), an IGBT, and the like. In this embodiment, the shielded gate trench power device is described by taking a shielded gate trench MOSFET power device with an upper and lower structure as an example.
Referring to fig. 2a, step S01 is executed to provide a substrate, an epitaxial layer 10a is formed on a surface of the substrate 10, a plurality of trenches 11 are formed in the epitaxial layer 10a, an angle between sidewalls of the trenches 11 and the surface of the substrate 10 is 87 to 93 °, a thickness of the epitaxial layer 10a is 3 to 9 micrometers, and a bulk resistance is 0.01 to 0.2 ohm per centimeter.
The substrate 10 may be a silicon-based semiconductor or silicon-on-insulator (SOI) substrate 10, and the substrate 10 is illustrated as a silicon substrate in this embodiment. The substrate 10 includes a base 10b and an epitaxial layer 10a covering the base 10b, for example, an N-type MOSFET power device, the doping types of the substrate 10 and the epitaxial layer are both N-type, and the doping concentration of the base 10b is higher than that of the epitaxial layer 10 a.
In this embodiment, the bulk resistance of the epitaxial layer 10a is 0.01 ohm per centimeter to 0.2 ohm per centimeter, the thickness of the epitaxial layer 10a is 3 micrometers to 9 micrometers, and both the bulk resistance and the thickness are smaller than the bulk resistance and the thickness range of the epitaxial layer of the conventional shielded gate trench power device, so that the shielded gate trench power device provided by this embodiment has a smaller on-resistance. It should be understood that in the conventional shielded gate trench power device, if the body resistance (the body resistance of the conventional epitaxial layer is greater than 0.15 ohm per centimeter) or the thickness (the thickness of the conventional epitaxial layer is greater than 7 micrometers) of the epitaxial layer is reduced, the breakdown voltage and the leakage current are difficult to guarantee. In practice, the thickness of the substrate 10b is much larger than that of the epitaxial layer 10a, and the relationship between the thicknesses of the substrate 10b and the epitaxial layer 10a is provided in the drawings of this embodiment for illustrative purposes only.
Preferably, in this embodiment, the epitaxial layer 10a may be a single-layer epitaxial layer, the thickness of the single-layer epitaxial layer is 3 to 7 microns, and the bulk resistance is 0.05 to 0.15 ohms per centimeter, so as to reduce the on-resistance of the shielded gate trench power device.
Furthermore, the epitaxial layer 10a may also be a plurality of sequentially connected epitaxial layers, the doping types of the plurality of epitaxial layers are the same (both N-type and P-type), but the doping concentration is gradually changed along the depth direction, and the doping concentration of the portion of the epitaxial layer 10a close to the substrate 10b (far from the surface of the substrate 10) is higher, while the doping concentration of the portion of the epitaxial layer far from the substrate 10b (near the surface of the substrate 10) is lower, so that the on-resistance of the shielded gate trench power device can be reduced while the electric field distribution is improved and the breakdown voltage is increased. Preferably, the epitaxial layer 10a is a double-layer epitaxial layer, and includes a first epitaxial layer and a second epitaxial layer connected to each other, the first epitaxial layer is far from the surface of the substrate 10 (i.e., located at the lower layer of the epitaxial layer 10 a) and has a thickness of 1mm to 4mm, the bulk resistance is 0.01 ohm per centimeter to 0.1 ohm per centimeter, the second epitaxial layer is close to the surface of the substrate 10 (i.e., located at the upper layer of the epitaxial layer 10 a) and has a thickness of 2mm to 5mm, and the bulk resistance is 0.1 ohm per centimeter to 0.2 ohm per centimeter.
It should be noted that the angle α between the sidewall of the trench 11 and the surface of the substrate 10 in this embodiment is 87 ° to 93 °, so as to further improve the electric field distribution and increase the breakdown voltage. Preferably, the angle α between the sidewall of the trench 11 and the surface of the substrate 10 is 87 ° to 90 °, so as to facilitate the filling of the film layer in the subsequent trench 11. In this embodiment, the trench 11 with vertical sidewall can be formed by deep trench etching process. The grooves 11 can be formed simultaneously, the depth and the opening of the grooves can be the same, and the corners at the bottom can be arc-shaped or right-angled. In this embodiment, the bottom corner of the trench 11 is arc-shaped.
Referring to fig. 2b, step S02 is performed to form a first dielectric layer 21, where the first dielectric layer 21 covers the inner wall of the trench 11 and the surface of the substrate 10, and at least a portion of the first dielectric layer 21 is formed by a wet oxidation process.
The first dielectric layer 21 may be silicon oxide. The formation of the dense and uniform first dielectric layer 21 in the trench 11 with the vertical sidewall (aspect ratio) formed by the wet oxidation process is one of the important steps in this embodiment. On one hand, the first dielectric layer 21 formed by the wet oxidation process has a faster formation rate, so that the advance sealing (closing) of the trench 11 caused by a slower formation mode (such as dry oxidation) can be prevented while the manufacturing efficiency is improved, and the problem that the first dielectric layer 21 is difficult to form in the existing trench 11 with a vertical sidewall is solved. On the other hand, the first dielectric layer 21 formed by the wet oxygen oxidation process has a relatively high film formation quality, and can satisfy the isolation requirement in this embodiment. It should be appreciated that in the conventional method for manufacturing the shielded gate trench power device, in order to solve the problem of early closing-in when the (aspect ratio) trench is formed with silicon oxide, the angle between the sidewall of the trench and the substrate surface is set to be relatively inclined, for example, less than 85 °, so as to facilitate trench filling, and the breakdown voltage of the shielded gate trench power device is sacrificed (reduced).
Furthermore, when the first dielectric layer 21 is formed, a wet oxidation process may be performed to form a partial thickness of the first dielectric layer 21, and then a CVD method is used to form the remaining thickness of the first dielectric layer 21, so as to reduce the consumption of silicon in the sidewall of the trench 11 when the first dielectric layer 21 is formed. The thickness and thickness relationship formed by the two process methods can be determined by combining the aspect ratio of the trench 11 and the breakdown voltage requirement of the power device.
Referring to fig. 2c and 2d, step S03 is performed to form a first conductive layer 22, the first conductive layer 22 fills the trench 11 and covers the surface of the substrate 10, a portion of the first conductive layer 22 is etched, and the shield gate 221 is formed by the remaining first conductive layer 22 in the trench 11.
The first conductive layer 22 may be made of polysilicon, and the formation process of the shielding gate 221 includes: as shown in fig. 2c, a first conductive layer 22 may be formed by LPCVD to cover and fill the trench 11 and cover the surface of the substrate 10, and then the first conductive layer 22 with a set depth in the trench 11 and the surface of the substrate 10 are etched away to form a shield gate 221 with the first conductive layer 22 remaining in the trench 11, as shown in fig. 2 d.
Referring to fig. 2e and fig. 2f, step S04 is performed to form a second dielectric layer 23, and the second dielectric layer 23 covers the shielding gate to serve as a shielding dielectric layer.
The second dielectric layer 23 may be silicon oxide, for example, formed by LPCVD, and the forming method may be as shown in fig. 2e and fig. 2 f: forming a second dielectric layer 23, wherein the second dielectric layer 23 fills the groove 11; and etching back the second dielectric layer 23 and the first dielectric layer 21, and removing the second dielectric layer 23 and the first dielectric layer 21 with a set depth to partially expose the side wall of the trench 11. Since in the present embodiment, the first dielectric layer 21 and the second dielectric layer 23 are both made of silicon oxide, the first dielectric layer 21 at the corresponding position can be removed simultaneously when the second dielectric layer 23 is removed. It should be understood that the second dielectric layer 23 is formed to cover the surface of the substrate 10 (not shown), and when the second dielectric layer 23 is removed, the first dielectric layer 21 on the surface of the substrate 10 is also removed accordingly.
Next, referring to fig. 2g, a first gate oxide layer 31 is formed, and the first gate oxide layer 31 covers the sidewall of the trench 11 and the second dielectric layer 23.
Wherein, a dry oxidation process can be performed to form the first gate oxide layer 31, so as to form a gate oxide layer with higher film quality. Due to the difference between the side wall of the trench 11 and the upper surface of the second dielectric layer 23, the bottom corner 311 of the first gate oxide layer is recessed towards the outer side of the trench 11, and further the first gate oxide layer 31 at the position is thinner, so that the shielded gate trench power device generates larger leakage at the weak position, and the loss is increased.
Referring to fig. 2h, step S05 is performed to form a second gate oxide layer 32, where the second gate oxide layer 32 covers the inner wall of the first gate oxide layer 31, including the sidewall and the bottom of the first gate oxide layer 31, and the bottom corner 322 of the second gate oxide layer is shaped as an arc.
Specifically, the second gate oxide layer 32 may be formed by a PECVD method, where the second gate oxide layer 32 has better adhesion and step coverage, covers the sidewall and the bottom of the first gate oxide layer 31, and fills the bottom corner 311 of the first gate oxide layer more, so as to form a circular arc-shaped bottom corner 322 of the second gate oxide layer, thereby solving the problem that the bottom corner 311 of the first gate oxide layer is prone to generate larger leakage, and facilitating to reduce the on-resistance of the shielded gate trench power device on the premise of increasing the breakdown voltage and reducing the leakage. It should be understood that other processes are also feasible to form the second gate oxide layer 32 with better adhesion and step coverage, such as HDP-CVD.
Referring to fig. 2i, step S06 is performed to form a gate 33 in the trench 11.
Specifically, the gate may be made of polysilicon, and the forming method includes: and forming a second conductive layer, wherein the second conductive layer fills the trench 11 and covers the surface of the substrate 10, and then, etching back or CMP the second conductive layer until the height difference between the second conductive layer and the surface of the substrate 10 is within a preset range, so as to form a gate 33 by using the remaining second conductive layer in the trench 11.
Finally, the method for manufacturing the shielded gate trench power device further includes the subsequent formation of a base region, a source metal pad layer and a gate 33 metal pad layer, and the steps are formed by methods commonly used in the art, for example, the steps may sequentially include P-body implantation, diffusion, N-source implantation, diffusion, ID deposition, contact hole lithography, etching, front metal deposition and patterning, back thinning, metallization, and the like, thereby completing the entire device manufacturing process, which is not described in detail herein.
In summary, the manufacturing method of the shielded gate trench power device provided by the invention has the following beneficial effects:
1) the first dielectric layer formed by the wet oxidation process covers the groove with the side wall vertical to the surface of the substrate, so that the problem that the vertical groove is difficult to fill is solved, the vertical groove is used for improving electric field distribution and improving breakdown voltage, the second gate oxide layer covers the inner wall of the first gate oxide layer, particularly the bottom corner of the first gate oxide layer, the thickness of the gate oxide layer at the bottom corner is increased, the leakage between gate sources is improved, and the loss is reduced;
2) the high breakdown voltage of the shielding grid groove power device can be used for reducing the body resistance of the epitaxial layer to 0.01-0.2 ohm per centimeter or reducing the thickness of the epitaxial layer to 3-9 micrometers so as to reduce the on resistance of the shielding grid groove power device.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (10)
1. A method for manufacturing a shielded gate trench power device, comprising:
providing a substrate, wherein an epitaxial layer is formed on the surface of the substrate, a plurality of grooves are formed in the epitaxial layer, the angle between the side wall of each groove and the surface of the substrate is 87-93 degrees, the thickness of the epitaxial layer is 3-9 microns, and the bulk resistance of the epitaxial layer is 0.01-0.2 ohm per centimeter;
forming a first dielectric layer, wherein the first dielectric layer covers the inner wall of the groove and the surface of the substrate, and at least part of the first dielectric layer is formed by utilizing a wet oxygen oxidation process;
forming a first conductive layer, wherein the first conductive layer fills the groove, and etching part of the first conductive layer to form a shielding grid by using the rest first conductive layer;
forming a second dielectric layer and a first gate oxide layer, wherein the second dielectric layer covers the shielding gate, and the first gate oxide layer covers the side wall of the groove and the second dielectric layer;
forming a second gate oxide layer, wherein the second gate oxide layer covers the inner wall of the first gate oxide layer, and the bottom corner of the second gate oxide layer is arc-shaped; and the number of the first and second groups,
and forming a gate in the groove.
2. The method of manufacturing a shielded gate trench power device of claim 1 wherein said shielded gate trench power device is a shielded gate trench MOSFET power device.
3. The method of claim 1 wherein the angle between the sidewall of the trench and the surface of the substrate is 87 ° to 90 °.
4. The method of claim 3, wherein the trench is formed using a deep trench etch process.
5. The method of claim 1, wherein the epitaxial layer is a single layer epitaxial layer having a thickness of 3 to 7 microns and a bulk resistance of 0.05 to 0.15 ohms per centimeter.
6. The method of claim 1, wherein the epitaxial layer is a double-layer epitaxial layer and comprises a first epitaxial layer and a second epitaxial layer which are connected, the first epitaxial layer is far away from the surface of the substrate and has a thickness of 1mm to 4mm, the bulk resistance is 0.01 ohm per centimeter to 0.1 ohm per centimeter, the second epitaxial layer is close to the surface of the substrate and has a thickness of 2mm to 5mm, and the bulk resistance is 0.1 ohm per centimeter to 0.2 ohm per centimeter.
7. The method of claim 1, wherein a wet oxidation process is performed to form a partial thickness of the first dielectric layer, and then a CVD process is used to form a remaining thickness of the first dielectric layer.
8. The method for manufacturing a shielded gate trench power device according to claim 1, wherein the method for forming the second dielectric layer comprises:
forming a second dielectric layer and filling the groove; and the number of the first and second groups,
and etching back the second dielectric layer, and removing the second dielectric layer and the first dielectric layer with set depth to partially expose the side wall of the groove.
9. The method of claim 8, wherein the first gate oxide layer is formed using a dry oxygen oxidation process.
10. The method of claim 9, wherein the second gate oxide layer is formed by a PECVD process.
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