CN114005756A - Manufacturing method of shielded gate trench power device - Google Patents
Manufacturing method of shielded gate trench power device Download PDFInfo
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- CN114005756A CN114005756A CN202111276210.XA CN202111276210A CN114005756A CN 114005756 A CN114005756 A CN 114005756A CN 202111276210 A CN202111276210 A CN 202111276210A CN 114005756 A CN114005756 A CN 114005756A
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
Abstract
The invention provides a manufacturing method of a shielded gate trench power device, which comprises the following steps: providing a substrate, wherein a first groove is formed in the substrate, and the inner wall of the first groove is covered with a field oxide layer; forming a shielding gate in the first trench; etching the field oxide layer in the first groove to form a second groove, wherein the second groove surrounds the shielding gate; forming a gate oxide layer, wherein the gate oxide layer covers the inner wall of the second groove, at least part of the gate oxide layer is formed by using an ISSG (integrated standard deviation set) process, and the corner of the bottom of the gate oxide layer is in an arc shape; and forming a gate in the second trench. In the invention, the gate oxide layer with partial thickness is formed by using the ISSG process, the gate oxide layer formed by the ISSG process has better filling property and step coverage property, and the corner at the bottom of the formed gate oxide layer is in a circular arc shape so as to improve the thickness uniformity of the gate oxide layer, thereby reducing the gate leakage current and improving the reliability of the power device of the shielded gate groove.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a shielded gate trench power device.
Background
Due to the fact that the shielding grid groove structure has a charge coupling effect, a horizontal depletion layer is introduced on the basis of vertical depletion of a traditional groove power device, and the electric field of the device is changed from triangular distribution to approximately rectangular distribution. With the same doping concentration of the epitaxial specification, the device can obtain higher breakdown voltage, and the structure is widely applied.
With the reduction of key technology nodes, namely, the size of a trench for forming a shielding gate is reduced, the depth-to-width ratio of the trench is further increased, so that the leakage current of a shielding gate trench power device formed by continuously using the conventional method is increased, and the performance of the shielding gate trench power device in a high-temperature reverse bias test is poor.
In a conventional shielded gate trench power device such as that shown in fig. 1, a gate oxide layer 30 'is overlaid in a trench 11' formed by a substrate 10 'and a shielded gate 20' to fill and form a gate 40 'on the gate oxide layer 30'. However, in the process of forming the gate oxide layer 30 ', the gate oxide layer 30 ' at the bottom wall corner is thinner due to the difference in the growth rate of the gate oxide layer 30 ' caused by the difference in the interface between the bottom and the sidewall, which causes the above problem.
Disclosure of Invention
The invention aims to provide a manufacturing method of shielded gate trench power, which is used for reducing leakage current of the shielded gate trench power.
In order to solve the above technical problem, the present invention provides a method for manufacturing a shield gate trench power, including: providing a substrate, wherein a first groove is formed in the substrate, and the inner wall of the first groove is covered with a field oxide layer; forming a shielding grid in the first groove, wherein the shielding grid covers the field oxide layer and fills the first groove; etching the field oxide layer in the first groove to expose the substrate and the side wall of the shielding grid and form a second groove, wherein the second groove surrounds the shielding grid; forming a gate oxide layer, wherein the gate oxide layer covers the inner wall of the second groove, at least part of the gate oxide layer is formed by using an ISSG (integrated standard deviation set) process, and the corner of the bottom of the gate oxide layer is in an arc shape; and forming a grid electrode in the second groove, wherein the grid electrode covers the grid oxide layer and fills the second groove.
Optionally, the second trench is formed by etching the field oxide layer in the first trench by wet etching. .
Optionally, the depth of the second trench is smaller than the depth of the first trench, and smaller than the depth of the shield gate.
Optionally, after forming the second trench and before forming the gate oxide layer, the method further includes: forming a sacrificial layer, wherein the sacrificial layer covers the inner wall of the second groove; and removing the sacrificial layer.
Optionally, the gate oxide layer includes a first gate oxide layer and a second gate oxide layer, the first gate oxide layer covers an inner wall of the second trench, and the second gate oxide layer covers the first gate oxide layer.
Optionally, the first gate oxide layer is formed by using a wet oxygen oxidation process, and the second gate oxide layer is formed by using a low-pressure ISSG process.
Optionally, the second gate oxide layer is formed by using a wet oxygen oxidation process, and the first gate oxide layer is formed by using a low-pressure ISSG process.
Optionally, the thickness of the gate oxide layer formed by using the low-pressure ISSG process is 40% to 60% of the thickness of the gate oxide layer.
Optionally, the ISSG process is a low-pressure ISSG process, and the cavity pressure of the ISSG process is 5torr to 15 torr.
Optionally, the process gas of the ISSG process includes oxygen, hydrogen, and nitrogen.
In summary, the manufacturing method of the shielded gate trench power device provided by the invention has the following beneficial effects:
1) the gate oxide layer with partial thickness is formed by using an ISSG (integrated single-gate silicon-oxide) process, the gate oxide layer formed by the ISSG process has better filling property and step coverage property, and the corner at the bottom of the formed gate oxide layer is in a circular arc shape so as to improve the thickness uniformity of the gate oxide layer, thereby reducing the leakage current of a grid electrode, improving the reliability of a power device of a shielding grid groove and improving the performance of the power device in a high-temperature reverse bias test;
2) only a part of the gate oxide layer is formed by the ISSG process, and the gate oxide layer with the residual thickness can be formed by a conventional method so as to reduce the cost for forming the gate oxide layer and manufacturing the device.
Drawings
It will be appreciated by those skilled in the art that the drawings are provided for a better understanding of the invention and do not constitute any limitation to the scope of the invention. Wherein:
FIG. 1 is a schematic diagram of a prior art shielded gate trench power device;
fig. 2a to fig. 2f are schematic structural diagrams corresponding to the manufacturing method of the shielded gate trench power device according to the embodiment of the present application;
fig. 3a to fig. 3b are schematic structural diagrams corresponding to another method for manufacturing a shielded gate trench power device according to an embodiment of the present application;
fig. 4 is a flowchart of a method for manufacturing a shielded gate trench power device according to an embodiment of the present application.
In fig. 1:
10' -a substrate; 11' -a trench; 21' -field oxide layer; 22' -a shielding grid; 30' -a gate oxide layer; 40' -grid electrode.
In fig. 2a to 3 b:
10-a substrate; 11-a first trench; 21-field oxygen layer; 22-a shielding grid; 23-a second trench;
30-a gate oxide layer; 31-a first gate oxide layer; 32-a second gate oxide layer;
40-grid electrode.
Detailed Description
To further clarify the objects, advantages and features of the present invention, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. It is to be noted that the drawings are in greatly simplified form and are not to scale, but are merely intended to facilitate and clarify the explanation of the embodiments of the present invention. Further, the structures illustrated in the drawings are often part of actual structures. In particular, the drawings may have different emphasis points and may sometimes be scaled differently.
As used in this application, the singular forms "a", "an" and "the" include plural referents, the term "or" is generally employed in a sense including "and/or," the terms "a" and "an" are generally employed in a sense including "at least one," the terms "at least two" are generally employed in a sense including "two or more," and the terms "first", "second" and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit to the number of technical features indicated. Thus, features defined as "first," "second," and "third" may explicitly or implicitly include one or at least two of the features unless the content clearly dictates otherwise.
Fig. 4 is a flowchart of a method for manufacturing a shielded gate trench power device according to an embodiment of the present application.
As shown in fig. 4, the method for manufacturing a shielded gate trench power device provided in this embodiment includes:
s01: providing a substrate, wherein a first groove is formed in the substrate, and the inner wall of the first groove is covered with a field oxide layer;
s02: forming a shielding grid in the first groove, wherein the shielding grid covers the field oxide layer and fills the first groove;
s03: etching the field oxide layer in the first groove to expose the substrate and the side wall of the shielding grid and form a second groove, wherein the second groove surrounds the shielding grid;
s04: forming a gate oxide layer, wherein the gate oxide layer covers the inner wall of the second groove, at least part of the gate oxide layer is formed by using an ISSG (integrated standard deviation SG) process, and the corner of the bottom of the gate oxide layer is in an arc shape; and the number of the first and second groups,
s05: and forming a grid electrode in the second groove, wherein the grid electrode covers the grid oxide layer and fills the second groove.
Fig. 2a to fig. 2f are schematic structural diagrams corresponding to corresponding steps of a manufacturing method of a shielded gate trench power device according to an embodiment of the present application, and the manufacturing method of the shielded gate trench power device according to the embodiment will be described in detail below with reference to fig. 2a to fig. 2 f.
The shielded gate trench power device may be a shielded gate trench MOSFET power device, or may also be a power device including a MOSFET structure, such as a MOS Controlled Thyristor (MCT), an IGBT, and the like. In this embodiment, a shielded gate trench MOSFET power device having a left-right structure is taken as an example for description.
Referring to fig. 2a, step S01 is performed to provide a substrate 10, form a plurality of first trenches 11 in the substrate 10, and form a field oxide layer 21, wherein the field oxide layer 21 covers inner walls of the first trenches 11 and a surface of the substrate 10.
The substrate 10 may be a silicon-based semiconductor or a silicon-on-insulator (SOI) substrate, and the substrate 10 is illustrated as a silicon substrate in this embodiment. An epitaxial layer is formed on the surface of the substrate 10, and the first trench 11 is formed in the epitaxial layer. Taking an N-type MOSFET power device as an example, the doping types of the substrate 10 and the epitaxial layer are both N-type, and the doping concentration of the substrate 10 is higher than that of the epitaxial layer.
The sidewall of the first trench 11 is perpendicular to the surface of the substrate 10, for example, at an angle of 80 ° to 90 °, and the bottom corner of the first trench 11 is shaped as a right angle or a circular arc. A plurality of first trenches 11 are formed in the epitaxial layer and arranged at intervals for forming a shield gate and a gate. It is understood that there may be other trenches in the epitaxial layer of the substrate 10 for forming other structures, such as conductive electrodes or ESD protection structures, and the like, and the present embodiment is not limited thereto.
The field oxide layer 21 is, for example, silicon oxide, and the field oxide layer 21 may be formed on the surface of the substrate 10 and the inner wall of the first trench 11 by a thermal oxidation process or a CVD method. In practice, the field oxide layer 21 with a partial thickness may be formed by a thermal oxidation process, and then the field oxide layer 21 with a residual thickness may be formed by a CVD method, so as to achieve both the forming speed and the forming quality when forming the thicker field oxide layer 21.
Next, referring to fig. 2b, step S02 is performed to form a shield gate 22 in the first trench 11, wherein the shield gate 22 covers the field oxide layer 21 and fills the first trench 11. The material of the shielding gate 22 may be polysilicon, aluminum, tantalum, tungsten, titanium, or the like, and may be formed by deposition. In this embodiment, the material of the shield gate 22 is polysilicon, and the shield gate can be formed by LPCVD, the formed polysilicon fills the first trench 11 and extends to cover the field oxide layer 21 on the substrate 10, the polysilicon is etched back to make the top surface of the polysilicon substantially on the same plane as the surface of the substrate 10 or slightly lower than the surface of the substrate 10, and the polysilicon on the field oxide layer 21 of the substrate 10 is simultaneously removed, and the remaining polysilicon in the first trench 11 is used as the shield gate 22.
Next, referring to fig. 2c, in step S03, the field oxide layer 21 in the first trench 11 is etched to expose the sidewalls of the substrate 10 and the shield gate 22, so as to form a second trench 23, wherein the second trench 23 surrounds the shield gate 22.
The field oxide layer 21 on the substrate 10 and in the first trench 11 can be removed by wet etching, which utilizes the high selectivity and low cost of wet etching to improve the removal quality and reduce the damage to the substrate 10, and has better removal rate and cost. In the present embodiment, the field oxide layer 21 is silicon oxide, and the etching solution for wet etching may be buffered silicon oxide etching solution (BOE) or buffered hydrofluoric acid (BHF), for example.
Wherein the second trench 23 is located in the first trench 11 and disposed around the shielding gate 22, two sidewalls of the second trench 23 are respectively the exposed substrate 10 and the shielding gate 22, and in the cross-sectional view in the depth direction as shown in fig. 2c, the second trench 23 is respectively located at two sides of the shielding gate. The depth of the second trench 23 is smaller than the depth of the first trench 11 and lower than the depth of the shield gate 22.
In practice, the depth of the bottom of the second trench 23 is not the same, but the depth of the bottom near the shield gate is slightly deeper than the depth of the bottom near the substrate.
Preferably, after forming the second trench 23, the method may further include: a sacrificial layer is formed to cover the inner walls of the second trenches 23 and the surface of the substrate 10, and then the sacrificial layer is wet etched. The sacrificial layer may be a silicon oxide formed by dry oxidation, and the thickness of the sacrificial layer is thin, such as 100-150 angstroms. When the sacrificial layer is removed, the sacrificial layer covering the profile abnormality (e.g., outward recess) in the sidewall of the second trench 23 is removed less and partially remains, so that the sidewall of the second trench 23 can be repaired.
Referring to fig. 2d and fig. 2e, step S04 is performed to form the gate oxide layer 30, in which the gate oxide layer 30 covers the inner wall of the second trench 23, wherein the gate oxide layer 30 with at least a partial thickness is formed by using an ISSG process, and the bottom corner of the gate oxide layer 30 is arc-shaped. Specifically, the gate oxide layer 30 includes a first gate oxide layer 31 and a second gate oxide layer 32 formed in a row, the first gate oxide layer 31 covers an inner wall of the second trench 23, and the second gate oxide layer 32 covers the first gate oxide layer 31.
Referring to fig. 2d, a first gate oxide layer 31 is formed, and the first gate oxide layer 31 covers the inner wall of the second trench 23. The material of the first gate oxide layer 31 is, for example, silicon oxide, and may be formed by a dry oxidation process or a wet oxidation process. In the present embodiment, the first gate oxide layer 31 is preferably formed using a wet oxygen oxidation process to increase the formation rate.
It should be noted that, because the material (or structure) of the bottom and the two side walls of the first trench 11 is different, and the rate and the shape of the first gate oxide layer 31 correspondingly formed between the bottom and the two side walls are different, the bottom corner of the first gate oxide layer 31 is easily protruded outward relative to the second trench 23, that is, the thickness of the first gate oxide layer 31 at the bottom corner is relatively thin, and further the leakage current at the bottom corner is relatively large, so that the shielded gate trench power device performs poorly in the high temperature reverse bias test. In the present embodiment, the thickness of the first gate oxide layer 31 is only a partial thickness of the gate oxide layer 30, and accordingly, the degree of protrusion or thinning of the first gate oxide layer 31 at the bottom corner is relatively reduced. It is to be understood that the first gate oxide layer 31 is formed to extend over the surface of the substrate 10 (not shown) in addition to the inner wall of the second trench 23.
Referring to fig. 2e, an ISSG process is performed to form a second gate oxide layer 32, and the second gate oxide layer 32 covers the surface of the first gate oxide layer 31. The material of the second gate oxide layer 32 is, for example, silicon oxide, and the second gate oxide layer 32 is formed in an RTP (rapid thermal processing) tool, unlike the first gate oxide layer 31 formed by using a furnace tool for oxidation.
Preferably, the ISSG process may be a low pressure ISSG process, and the overall pressure of the chamber is 5torr to 15 torr. Specifically, the process gas introduced for performing the ISSG process includes nitrogen, oxygen and hydrogen, wherein the oxygen and the hydrogen are used as the reaction gas, and the nitrogen is used for diluting the reaction gas, so as to improve the uniformity of forming the second gate oxide layer 32. Experiments show that the second gate oxide layer 32 formed under the conditions that the reaction temperature is 1000-1100 ℃, the oxygen gas introduction flow rate is 5 slm-12 slm, the hydrogen gas introduction flow rate is 0.5 slm-6 slm, and the nitrogen gas introduction flow rate is 0.5 slm-5 slm has a better bottom corner filling effect. Due to the better step coverage and filling property of the second gate oxide layer 32 formed by the low-pressure ISSG process, the second gate oxide layer 32 forms a circular arc-shaped bottom corner as shown in fig. 2e, so that the weak part of the bottom corner of the gate oxide layer 30 is eliminated, the gate leakage current of the shielded gate trench power device can be reduced, the performance in a high-temperature reverse bias test is improved, and the reliability of the shielded gate trench power device is also improved.
Further, through experiments, the thickness of the gate oxide layer (the second gate oxide layer 32) formed by using the low-pressure ISSG process accounts for 40% -60% of the total thickness of the gate oxide layer, so as to consider the filling effect of the bottom corner of the gate oxide layer and the manufacturing cost. It should be understood that it is also feasible to form the entire gate oxide layer by using the ISSG process, but the consumption of the RTP apparatus is large when the ISSG process is used to form a thicker film layer, which is not favorable for cost control, and it is difficult to ensure the filling effect of the bottom corner of the gate oxide layer when the gate oxide layer formed by using the low-pressure ISSG process is too thin.
Referring to fig. 2f, step S05 is performed to form a gate 40 in the second trench 23, wherein the gate 40 covers the gate oxide layer and fills the second trench 23. The gate electrode 40 may be made of any suitable conductive layer. In this embodiment, the gate electrode 40 is made of polysilicon and can be formed by LPCVD.
The present embodiment further provides another method for manufacturing a shielded gate trench power device, which is similar to the aforementioned method for manufacturing a shielded gate trench power device, and only differs when the first gate oxide layer 31 and the second gate oxide layer 32 of the gate oxide layer 30 are formed.
Referring to fig. 3a, the first gate oxide layer 31 covering the inner wall of the second trench 23 is formed by using an ISSG process, and specifically, the method is referred to in the process of forming the first gate oxide layer 31 by using the ISSG process, and the bottom corner of the first gate oxide layer 31 is in a circular arc shape.
Referring to fig. 3b, a second gate oxide layer 32 covering the first gate oxide layer 31 is formed by a wet oxidation process, wherein a bottom corner of the first gate oxide layer 31 is arc-shaped, and a bottom corner of the second gate oxide layer 32 is also arc-shaped.
Finally, the method for manufacturing the shielded gate trench power device according to this embodiment further includes the subsequent formation of the base region, the source metal pad layer, and the gate metal pad layer, and the steps are formed by methods commonly used in the art, for example, the steps may sequentially include P-body implantation, diffusion, N-source implantation, diffusion, ID deposition, contact hole lithography, etching, front metal deposition and patterning, back thinning, and metallization, and the like, so as to complete the entire device manufacturing process, which is not described in detail herein.
In summary, the manufacturing method of the shielded gate trench power device provided by the invention has the following beneficial effects:
1) the gate oxide layer with partial thickness is formed by using an ISSG (integrated single-gate silicon-oxide) process, the gate oxide layer formed by the ISSG process has better filling property and step coverage property, and the corner at the bottom of the formed gate oxide layer is in a circular arc shape so as to improve the thickness uniformity of the gate oxide layer, thereby reducing the leakage current of a grid electrode, improving the reliability of a power device of a shielding grid groove and improving the performance of the power device in a high-temperature reverse bias test;
2) only a part of the gate oxide layer is formed by the ISSG process, and the gate oxide layer with the residual thickness can be formed by a conventional method so as to reduce the cost for forming the gate oxide layer and manufacturing the device.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (10)
1. A method for manufacturing a shielded gate trench power device, comprising:
providing a substrate, wherein a first groove is formed in the substrate, and the inner wall of the first groove is covered with a field oxide layer;
forming a shielding grid in the first groove, wherein the shielding grid covers the field oxide layer and fills the first groove;
etching the field oxide layer in the first groove to expose the substrate and the side wall of the shielding grid and form a second groove, wherein the second groove surrounds the shielding grid;
forming a gate oxide layer, wherein the gate oxide layer covers the inner wall of the second groove, at least part of the gate oxide layer is formed by using an ISSG (integrated standard deviation set) process, and the corner of the bottom of the gate oxide layer is in an arc shape; and the number of the first and second groups,
and forming a grid electrode in the second groove, wherein the grid electrode covers the grid oxide layer and fills the second groove.
2. The method of claim 1, wherein the second trench is formed by etching the field oxide layer in the first trench using a wet etch.
3. The method of claim 2, wherein the depth of the second trench is less than the depth of the first trench and less than the depth of the shield gate.
4. The method of claim 1, further comprising, after forming the second trench and before forming the gate oxide layer:
forming a sacrificial layer, wherein the sacrificial layer covers the inner wall of the second groove;
and removing the sacrificial layer.
5. The method of any of claims 1-4, wherein the gate oxide layer comprises a first gate oxide layer and a second gate oxide layer, the first gate oxide layer covers an inner wall of the second trench, and the second gate oxide layer covers the first gate oxide layer.
6. The method of claim 5, wherein the first gate oxide layer is formed using a wet oxygen oxidation process and the second gate oxide layer is formed using an ISSG process.
7. The method of claim 5, wherein the first gate oxide layer is formed using an ISSG process and the second gate oxide layer is formed using a wet oxygen oxidation process.
8. The method of claim 6 or 7, wherein the gate oxide layer formed by ISSG process has a thickness of 40-60% of the gate oxide layer.
9. The method of claim 1, wherein the ISSG process is a low-pressure ISSG process, and a cavity pressure of the ISSG process is 5-15 torr.
10. The method of claim 9, wherein the process gases of the ISSG process comprise oxygen, hydrogen, and nitrogen.
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