CN109830526A - A kind of power semiconductor and preparation method thereof - Google Patents
A kind of power semiconductor and preparation method thereof Download PDFInfo
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- CN109830526A CN109830526A CN201910144989.6A CN201910144989A CN109830526A CN 109830526 A CN109830526 A CN 109830526A CN 201910144989 A CN201910144989 A CN 201910144989A CN 109830526 A CN109830526 A CN 109830526A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 238000002360 preparation method Methods 0.000 title claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 claims description 25
- 239000002184 metal Substances 0.000 claims description 25
- 238000000926 separation method Methods 0.000 claims description 23
- 239000003989 dielectric material Substances 0.000 claims description 21
- 239000000758 substrate Substances 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 229920005591 polysilicon Polymers 0.000 claims description 13
- 239000004020 conductor Substances 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 8
- 150000004767 nitrides Chemical class 0.000 claims description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 210000000746 body region Anatomy 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 230000005669 field effect Effects 0.000 abstract description 22
- 238000004519 manufacturing process Methods 0.000 abstract description 10
- 125000006850 spacer group Chemical group 0.000 abstract description 5
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 239000012535 impurity Substances 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- 238000000407 epitaxy Methods 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000011669 selenium Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000002305 electric material Substances 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229910052711 selenium Inorganic materials 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052714 tellurium Inorganic materials 0.000 description 1
- PORWMNRCUJJQNO-UHFFFAOYSA-N tellurium atom Chemical compound [Te] PORWMNRCUJJQNO-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of power semiconductor and preparation method thereof, in order to further increase the switching speed of the groove-shaped field-effect tube of shield grid and reduce switching loss, the present invention provides a kind of groove-shaped field-effect tube device architecture of the simple shield grid of manufacture craft and its manufacturing method, it is respectively formed gate oxide and interpolar spacer medium layer by successively different steps, so that the interpolar spacer medium layer formed is relatively thick.Reach the gate source capacitance for being effectively reduced device, increase the switching speed of device, reduces the beneficial effect of switching loss.
Description
Technical field
The present invention relates to a kind of structure of power semiconductor and its manufacturing method, especially a kind of shielding gate groove
The knot and its manufacturing method of type field-effect tube device.
Background technique
The background of related of the groove-shaped field-effect tube of existing shield grid will be illustrated below.It is noted that
Corresponding position word described in this document such as "upper", "lower", "left", "right", "front", "rear", " vertical ", "horizontal" correspond to
The relative position of referenced in schematic.Fixed-direction is not intended to limit in specific implementation.
The groove-shaped field-effect tube of shield grid has conducting resistance low, the fast spy of switching speed as a kind of power device
Point.Fig. 1 show a kind of cross-sectional structure schematic diagram of the groove-shaped field-effect tube of N-type shield grid of traditional structure, in shield grid
In groove-shaped field-effect tube device, interpolar isolating oxide layer (104) has gate electrode (106) (grid) and the shielding of isolating device
The effect of gate electrode (105) (source electrode).Grid when interpolar spacer medium layer is relatively thin, in the groove-shaped field-effect tube device of shield grid
Biggish gate source capacitance will be present between electrode (106) and shielding gate electrode (105).The gate source capacitance can limit
The switching speed of device processed, and increase the switching loss of device.
It in the above-mentioned existing groove-shaped field-effect tube process for making of shield grid, is formed simultaneously by a thermal oxide
Interpolar isolating oxide layer (104) and gate oxide (103), are formed by gate oxide (103) and interpolar isolating oxide layer (104)
Thickness it is equal.However in general, between 2 to 4 volts, therefore the nominal threshold voltages of the groove-shaped field-effect tube of shield grid are about
It is required that the thickness of gate oxide (103) be about between 0.02um to 0.1um.Due to being limited by gate oxide (103) thickness,
Interpolar isolating oxide layer (104) thickness is also within the scope of corresponding.Therefore, the groove-shaped field-effect tube manufacture of existing shield grid
Technical process be formed by interpolar isolating oxide layer (104) usually it is relatively thin, cause the switching speed of device lower and increase out
Close loss.
Summary of the invention
In order to further increase the switching speed of the groove-shaped field-effect tube of shield grid and reduce switching loss, for above
In be previously mentioned the problem of interpolar spacer medium thickness is spent, it is desirable to provide a kind of groove-shaped field-effect of simple shield grid of manufacture craft
Tube device structure and its manufacturing method.
To solve the above problems, the present invention proposes that a kind of structure of novel shielding gate groove type field-effect tube is as follows:
A kind of power semiconductor, the semiconductor devices includes:
Drain metal layer positioned at bottom；
First semiconductor substrate layer of the first conductive type on drain metal layer；
Second semiconductor epitaxial layers of the second conductive type on first semiconductor substrate layer；
More than one extends into the groove in the second semiconductor epitaxial layers from the upper surface of the second semiconductor epitaxial layers；It is described
Groove in filled with shielding gate electrode, the shielding gate electrode two sides are equipped with gate electrode,
The gate electrode is isolated with respective groove inner wall by gate oxide, and
The first medium layer being located in the groove below gate electrode is equipped in groove, and
It is isolated between gate electrode and the shielding gate electrode in respective groove by interpolar separation layer, and first medium layer compares grid oxygen
Change thickness, the interpolar separation layer is than gate oxidation thickness；
Second dielectric layer, between first medium layer and respective groove inner shield gate electrode；
Medium of oxides layer above the second semiconductor epitaxial layers；
The source metal on surface on the device, the source metal pass through through-hole on medium of oxides layer and described
Shielding gate electrode connection；
The gate metal on surface on the device, the gate metal pass through through-hole on medium of oxides layer and described
Gate electrode connection.
Further, the first medium layer and second dielectric layer are prepared by different materials respectively.
Further, second dielectric layer and first medium layer are by conductor oxidate, dielectric materials and/or dielectric
Material is constituted.
Further, interpolar separation layer is made of conductor oxidate.
The present invention also provides a kind of preparation method of power semiconductor, the preparation method includes following step
It is rapid:
The first step gets out substrate, and is formed on epitaxial layer；
Second step by being lithographically formed groove on epitaxial layer, and forms first medium layer in the trench；
Third step forms second dielectric layer in first medium layer surface, then depositing polysilicon and time quarter, makes polysilicon
It fills up groove and forms shielding gate electrode；
4th step returns and carves second dielectric layer, and when etching ensures that trenched side-wall is covered with first medium layer；
5th step, the separation layer between polysilicon surface growing pullets；
6th step performs etching the first medium layer of trenched side-wall, so that exposing the semiconductor on trenched side-wall top；
7th step forms gate oxide；
8th step, again depositing polysilicon and return carve form device gate electrode；
9th step carries out active area doping, carries out P-type ion and N+Type ion implanting forms p-type doped body region and N+Type
Doping source region；
Tenth step, deposition oxide dielectric layer etching through hole and form upper surface metal on it；
11st step carries out thinned and deposits back metal in substrate layer bottom, forms device to rear substrate layer.
Further, in second step, first medium layer is by semi-conducting nitride, dielectric materials or other insulation
Dielectric material is constituted, or is made of the combination layer of above-mentioned material；
Further, in the third step, second dielectric layer is by conductor oxidate, different from the low dielectric of first medium layer
Material or other insulating dielectric materials for being different from first medium layer are constituted, or by being different from the upper of first medium layer
The combination layer for stating material is constituted；
Further, in the 4th step, the etch rate of second dielectric layer is faster than first medium layer；
Further, in the 5th step, interpolar separation layer is made of conductor oxidate；
Further, in the 7th step, the method for forming gate oxide is thermal oxide or deposit.
The beneficial effects of the present invention are, compared with traditional handicraft, the groove-shaped field-effect tube of shield grid of the present invention
Process is respectively formed gate oxide and interpolar spacer medium layer by successively different step, be formed by interpolar every
It is relatively thick from dielectric layer.Therefore, it can be effectively reduced the gate source capacitance of device, increase the switching speed of device, dropped
Low switching losses.
Detailed description of the invention
Fig. 1 is the diagrammatic cross-section of tradition shielding gate groove type field-effect tube；
Fig. 2 is the diagrammatic cross-section of the groove-shaped field-effect tube of shield grid of the present invention；
Fig. 3-Fig. 9 is each step process schematic diagram of the present invention.
Specific embodiment
Below in conjunction with drawings and examples, the present invention is described in detail.It should be pointed out that below to the present invention
The groove-shaped field-effect tube device of shield grid and its manufacturing method explanation in, the groove-shaped field-effect tube device of shield grid is partly led
Body substrate is considered being made of silicon (Si) material.But the substrate also can be by other any suitable groove-shaped field-effects of shield grid
The material of pipe manufacture is constituted, such as gallium nitride (GaN), silicon carbide (SiC) etc..In the following description, the conduction type of semiconductor region
It is divided into p-type (the first conductive type) and N-type (the second conductive type).The semiconductor region of one P-type conduction can be by original half
Conductor region mixes one or more of impurity and constitutes, these impurity can be but be not limited to: boron (B), aluminium (Al), gallium (Ga)
Deng.The semiconductor region of one N-shaped conduction can also be constituted by mixing one or more of impurity to original semiconductor area, these impurity
It can be but be not limited to: phosphorus (P), arsenic (As), tellurium (Sb), selenium (Se), proton (H+) etc..In the following description, severe is mixed
The semiconductor region of miscellaneous p-type electric-conducting is marked as P+The semiconductor region in area, heavily doped N-type conduction is marked as N+Area.Example
Such as, in silicon materials substrate, if the impurity concentration in a heavily doped region is generally 1 × 10 without particularly pointing out19cm-3Extremely
1×1021cm-3Between.
It is the cross-sectional structure schematic diagram of the groove-shaped field-effect tube device of shield grid of the embodiment of the present invention shown in Fig. 2.
Device architecture includes: the drain metal layer (213) for being located at bottom；One N being located on drain metal layer+
Type substrate layer (200)；One is located at N+Type substrate layer (the N-type epitaxy layer (201) on 200；And surface on the device
P-type doped body region (208) and N+Type doping source region (207)；There are a series of grooves, filling in groove on N-type epitaxy layer (201)
There are three electrodes, are to be located at the gate electrode (206) of the left and right sides and be located in the middle to shield gate electrode (205) respectively.Shield grid
Electrode (205) is connected by the through-hole on medium of oxides layer (214) with the source metal (211) on surface on the device；Grid
Electrode (206) is connected by the through-hole on medium of oxides layer (214) with the gate metal (212) on surface on the device；
Meanwhile N+The source metal that type doping source region (207) passes through through-hole and surface on the device on medium of oxides layer (214)
(210) it is connected.
In the device architecture, it is isolated between gate electrode (206) and corresponding trenched side-wall by gate oxide (203).Grid
It is isolated between electrode (206) and shielding gate electrode (205) by interpolar separation layer (204).The interpolar separation layer (204) compares grid oxygen
It is thick to change layer (203).The interpolar separation layer (204) is generally made of conductor oxidate, such as silica, it is also possible to partly by other
Conducting oxide, nitride or other insulating dielectric materials are constituted, and the combination layer for being also possible to above-mentioned substance is constituted.?
In the specific embodiment of one practical application, the gate oxide thickness of device is 500-1000A, interpolar separation layer be silica and
It is with a thickness of 2000-5000A.
It shields between gate electrode (205) and corresponding trenched side-wall, under gate electrode (206), there is one layer of first medium layer
(209) and one layer of second dielectric layer (202).Wherein first medium layer is between trenched side-wall and second dielectric layer；Second is situated between
Matter layer is located between first medium layer and shielding gate electrode (205).First medium layer and second dielectric layer are respectively by different materials
Material is constituted.Wherein, first medium layer can be made of semi-conducting nitride, dielectric materials or other insulating dielectric materials,
It can be made of the combination layer of above-mentioned material.Second dielectric layer can be by conductor oxidate, different from low Jie of first medium layer
Electric material or other insulating dielectric materials for being different from first medium layer are constituted, can also be by being different from first medium layer
The combination layer of above-mentioned material is constituted.The possible combination of one kind is: first medium layer is semi-conducting nitride, and second dielectric layer is half
Conducting oxide；Alternatively possible combination is: first medium layer is dielectric materials, and second dielectric layer is semiconductor oxide
Object；Alternatively possible combination is: first medium layer is semi-conducting nitride, and second dielectric layer is dielectric materials.
Fig. 3-14 show the specific process step of the groove-shaped field-effect tube device of shield grid of the embodiment of the present invention:
The first step provides N+Type substrate (200), and it is formed on N-type epitaxy layer (201).
A series of second step, by being lithographically formed grooves in N-type epitaxy layer.Then first medium layer is formed in the trench
(209), as shown in Figure 3.
The photoetching of groove may be needed to form hard mask in epitaxial layer upper surface in advance.The hard mask can be semiconductor
Oxide or nitride, or a combination thereof.The hard mask may be removed (as shown in Figure 3) after etching groove, it is also possible to
The upper surface of epitaxial layer is still remained in after etching groove.After etching groove, before first medium layer is formed, it is possible to first with heat
The mode of oxidation forms relatively thin oxide sacrificial layer in the trench, and then oxide sacrificial layer is etched away again.In groove
First medium layer (209) can be by semi-conducting nitride, and dielectric materials or other insulating dielectric materials are constituted, can also be by
The combination layer of above-mentioned material is constituted.When the first medium layer in groove is silicon nitride, the forming method of first medium layer may
It is chemical vapor deposition (CVD).
Third step forms second dielectric layer (202) in first medium layer surface, then depositing polysilicon and time quarter, makes more
Crystal silicon fills up groove and forms shielding gate electrode (205).
Second dielectric layer (202) can by conductor oxidate, dielectric materials different from first medium layer or other
It is constituted different from the insulating dielectric materials of first medium layer, it can also be by the combination layer of the above-mentioned material different from first medium layer
It constitutes.When the second dielectric layer in groove be silica when, the forming method of second dielectric layer may be chemical vapor deposition or
Person's high density plasma CVD (HDP-CVD).It, can during returning quarter polysilicon or after completing at the quarter of returning
Also the first medium layer and second dielectric layer of upper semiconductor can be removed can in whole or in part.
Returning the method for carving polysilicon may be chemical-mechanical planarization (CMP), when this method is used, may be situated between first
Matter layer or second dielectric layer are as polish stop layer (Grinding stopper Layer), it is also possible to need to be pre-formed volume
Outer polish stop layer, which may be silicon nitride.
4th step returns and carves second dielectric layer, as shown in Figure 4.In this step, the etch rate of first medium layer is situated between than second
Matter layer is slow.After the completion of second dielectric layer etching, trenched side-wall is still covered by first medium layer.
5th step, separation layer (204) between polysilicon surface growing pullets, as shown in Figure 5.
Between growing pullets during separation layer (204), semiconductor trench side wall is by first medium layer covering protection.Interpolar
Separation layer can be formed by the growth of long period, therefore the thickness of interpolar separation layer can be controlled preferably, can be than tradition
Technique is thicker.Interpolar separation layer is insulating materials, may be conductor oxidate.When interpolar separation layer is silica, shape
It may be thermal oxide at method.
6th step performs etching the first medium layer of trenched side-wall.Etching until first medium layer in the trench height
It is lower than or equal with second dielectric layer, exposes the semiconductor on trenched side-wall top, as shown in Figure 6.
7th step is formed gate oxide (203).The method for forming gate oxide may be thermal oxide, it is also possible to deposit.
8th step deposits and returns and carve polysilicon, forms the gate electrode (206) of device, as shown in Figure 7.
9th step completes active area doping.It is taken up in order of priority and carries out P-type ion injection, N+Type ion implanting forms p-type and mixes
The area Za Ti (208), N+Type doping source region (207), as shown in Figure 7.
Tenth step, as shown in figure 8, deposition oxide dielectric layer (214), etching through hole on it, and form upper surface gold
Belong to (210,211,212).Wherein, gate electrode (206) passes through the through-hole and table on the device on medium of oxides layer (214)
The gate metal (212) in face is connected；Meanwhile N+Type doping source region (207) by through-hole on medium of oxides layer (214) with
The source metal (210) on surface on the device is connected.It, may be advanced before upper surface metal is formed after etching through hole
Row P+Type ion implanting.
11st step, rear substrate layer is carried out it is thinned, and substrate layer bottom deposit back metal-drain metal layer
(213), device is formed, as shown in Figure 9.
In the device technology manufacturing process of the embodiments of the present invention, interpolar separation layer (204) and gate oxide (203)
It is successively formed by different step respectively.Therefore, the thickness of interpolar separation layer (204) is not limited by gate oxide (203), can be with
Thicker interpolar separation layer (204) is formed gate electrode (206) and shielding gate electrode (205) is isolated, device is effectively reduced
Gate source capacitance promotes the switching speed of device and reduces switching loss.
Claims (10)
1. a kind of power semiconductor, which is characterized in that the semiconductor devices includes:
Drain metal layer positioned at bottom；
First semiconductor substrate layer of the first conductive type on drain metal layer；
Second semiconductor epitaxial layers of the second conductive type on first semiconductor substrate layer；
More than one extends into the groove in the second semiconductor epitaxial layers from the upper surface of the second semiconductor epitaxial layers；The ditch
Filled with shielding gate electrode in slot, the shielding gate electrode two sides are equipped with gate electrode,
The gate electrode is isolated with respective groove inner wall by gate oxide, and
The first medium layer being located in the groove below gate electrode is equipped in groove, and
It is isolated between gate electrode and the shielding gate electrode in respective groove by interpolar separation layer, and first medium layer compares gate oxide
Thickness, the interpolar separation layer is than gate oxidation thickness；
Second dielectric layer, between first medium layer and respective groove inner shield gate electrode；
Medium of oxides layer above the second semiconductor epitaxial layers；
The source metal on surface on the device, the source metal pass through the through-hole and the screen on medium of oxides layer
Cover gate electrode connection；
The gate metal on surface on the device, the gate metal pass through the through-hole and the grid on medium of oxides layer
Electrode connection.
2. power semiconductor as described in claim 1, which is characterized in that the first medium layer and second dielectric layer
It is prepared respectively by different materials.
3. power semiconductor as claimed in claim 2, which is characterized in that second dielectric layer and first medium layer are by partly leading
Oxide body, dielectric materials and/or insulating dielectric materials are constituted.
4. power semiconductor as described in claim 1, which is characterized in that interpolar separation layer is by conductor oxidate structure
At.
5. a kind of preparation method of power semiconductor, which is characterized in that the preparation method comprises the following steps that
The first step gets out substrate, and is formed on epitaxial layer；
Second step by being lithographically formed groove on epitaxial layer, and forms first medium layer in the trench；
Third step forms second dielectric layer in first medium layer surface, then depositing polysilicon and time quarter, fills up polysilicon
Groove forms shielding gate electrode；
4th step returns and carves second dielectric layer, and when etching ensures that trenched side-wall is covered with first medium layer；
5th step, the separation layer between polysilicon surface growing pullets；
6th step performs etching the first medium layer of trenched side-wall, so that exposing the semiconductor on trenched side-wall top；
7th step forms gate oxide；
8th step, again depositing polysilicon and return carve form device gate electrode；
9th step carries out active area doping, carries out P-type ion and N+Type ion implanting forms p-type doped body region and N+Type doping
Source region；
Tenth step, deposition oxide dielectric layer etching through hole and form upper surface metal on it；
11st step carries out thinned and deposits back metal in substrate layer bottom, forms device to rear substrate layer.
6. preparation method as claimed in claim 5, which is characterized in that in second step, first medium layer is by semiconducting nitride
Object, dielectric materials or other insulating dielectric materials are constituted, or are made of the combination layer of above-mentioned material.
7. preparation method as claimed in claim 5, which is characterized in that in the third step, second dielectric layer is by semiconductor oxide
Object, dielectric materials or other insulating dielectric materials for being different from first medium layer different from first medium layer are constituted, again
Or it is made of the combination layer for the above-mentioned material for being different from first medium layer.
8. preparation method as claimed in claim 5, which is characterized in that in the 4th step, the etch rate of second dielectric layer is than
One dielectric layer is fast.
9. preparation method as claimed in claim 5, which is characterized in that in the 5th step, interpolar separation layer is by conductor oxidate
It constitutes.
10. preparation method as claimed in claim 5, which is characterized in that in the 7th step, the method for forming gate oxide is hot oxygen
Change or deposits.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022099786A1 (en) * | 2020-11-12 | 2022-05-19 | 苏州东微半导体有限公司 | Method for manufacturing semiconductor power device |
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