CN113690143A - Process method for solving polysilicon etching punch-through of SGT-MOSFET grid - Google Patents
Process method for solving polysilicon etching punch-through of SGT-MOSFET grid Download PDFInfo
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- CN113690143A CN113690143A CN202110900618.3A CN202110900618A CN113690143A CN 113690143 A CN113690143 A CN 113690143A CN 202110900618 A CN202110900618 A CN 202110900618A CN 113690143 A CN113690143 A CN 113690143A
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 97
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 88
- 238000005530 etching Methods 0.000 title claims abstract description 76
- 238000000034 method Methods 0.000 title claims abstract description 40
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 91
- 230000000873 masking effect Effects 0.000 claims abstract description 67
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 45
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 45
- 238000000151 deposition Methods 0.000 claims abstract description 40
- 238000005468 ion implantation Methods 0.000 claims abstract description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 19
- 239000010703 silicon Substances 0.000 claims abstract description 19
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 230000003647 oxidation Effects 0.000 claims abstract description 5
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 5
- 238000001259 photo etching Methods 0.000 claims abstract description 4
- 150000002500 ions Chemical class 0.000 claims description 11
- 238000011049 filling Methods 0.000 claims description 10
- 238000002955 isolation Methods 0.000 claims description 8
- 239000000126 substance Substances 0.000 claims description 8
- 238000000227 grinding Methods 0.000 claims description 4
- 238000007517 polishing process Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 8
- 230000008021 deposition Effects 0.000 description 5
- 239000002184 metal Substances 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
The invention discloses a process method for solving polysilicon etching punch-through of an SGT-MOSFET grid, which comprises the following steps of: epitaxially growing an epitaxial layer on the substrate, and growing a masking layer on the epitaxial layer; depositing a layer of photoresist, performing groove photoetching, and etching a groove etching window; etching the deep trench, performing sacrificial oxidation, and growing a field oxide layer; depositing a shield grid polysilicon, etching the masking layer, depositing a silicon dioxide isolating layer in the groove, etching the silicon dioxide isolating layer in the groove, and removing the masking layer; growing a gate oxide layer, depositing grid polysilicon, depositing an ion implantation silicon dioxide masking layer, ion implantation grid polysilicon, removing the ion implantation silicon dioxide masking layer, and etching the grid polysilicon back to be flush with the silicon surface. The invention can eliminate the V shape of the grid polysilicon and effectively solve the problem that the grid polysilicon is penetrated through due to the etching of the contact hole.
Description
Technical Field
The invention relates to a process method, in particular to a process method for solving polysilicon etching punch-through of an SGT-MOSFET grid.
Background
The process steps of the SGT-MOSFET with the upper structure and the lower structure are as follows: etching an epitaxial layer to form a deep groove, growing a field oxide layer in the deep groove, filling a shield gate polysilicon and etching back, wherein the surface of the shield gate is lower than the surface of the silicon by a certain distance; then, wet etching the field oxide layer to form a gate trench, and then growing a gate oxide layer and filling polysilicon to form a gate; and finally, performing well region ion implantation and source region ion implantation to form a source electrode.
When the grid polycrystalline silicon fills the grid groove, the grid polycrystalline silicon above the groove is in a V shape all the time, the grid polycrystalline silicon on the surface of the epitaxial layer silicon is removed completely after dry etching back, and the residual thickness of the grid polycrystalline silicon in the middle of the grid polycrystalline silicon in the groove becomes very thin due to the V shape; the specific structure of the SGT is shown in FIG. 1. Because the source contact hole needs to be etched to a certain depth of the silicon substrate, generally 3000A-5000A, the contact hole on the gate can also etch the gate polysilicon to a certain depth, and at this time, if the residual thickness of the gate polysilicon at the V-shaped tip position is not enough, the gate polysilicon is easily penetrated through by the subsequent contact hole etching process, which causes the problem of device reliability, as shown in fig. 2 and 3.
Therefore, it is desired to solve the above problems.
Disclosure of Invention
The purpose of the invention is as follows: the invention aims to provide a process method for solving the problem of etching and punch-through of the gate polysilicon of the SGT-MOSFET, which can eliminate the V shape of the gate polysilicon and effectively solve the problem of etching and punch-through of the gate polysilicon due to a contact hole.
The technical scheme is as follows: in order to achieve the purpose, the invention discloses a process method for solving polysilicon etching punch-through of an SGT-MOSFET gate, which comprises the following steps:
(1) selecting an epitaxial wafer according to the characteristic requirements of the MOSFET, wherein the wafer consists of a substrate with low-range resistivity and an epitaxial layer with constant-value resistivity, carrying out epitaxial growth on the substrate to form an epitaxial layer, and growing a masking layer on the epitaxial layer;
(2) depositing a layer of photoresist on the masking layer, carrying out groove photoetching, etching the photoresist and the masking layer, and etching a groove etching window;
(3) removing the photoresist, performing deep trench etching on the trench etching window by using the masking layer, and forming a deep trench under the masking action of the masking layer;
(4) carrying out sacrificial oxidation on the surface of the epitaxial layer, and removing the oxide layer; growing a layer of field oxide layer on the side wall and the bottom of the deep groove;
(5) depositing a shielding grid polysilicon, filling the deep trench with the shielding grid polysilicon, and simultaneously depositing a layer of shielding grid polysilicon on the surface of the masking layer;
(6) etching the shielding grid polysilicon, etching the shielding grid polysilicon in the deep groove to be below the surface of the silicon, and etching away a layer of shielding grid polysilicon on the surface of the masking layer;
(7) the masking layer is etched back, so that the boundary of the masking layer is vertically aligned with the boundary of the groove;
(8) depositing a silicon dioxide isolation layer in the groove, and then thinning the silicon dioxide isolation layer to be flush with the masking layer by adopting a chemical mechanical grinding process;
(9) etching the silicon dioxide isolation layer in the groove to a position above the shielding grid by a certain distance, forming a grid groove, and then removing the masking layer;
(10) growing a gate oxide layer, and forming gate oxide on the side walls of two sides of the gate trench and the silicon surface;
(11) depositing grid polysilicon, wherein the grid polysilicon at the groove is in a V shape;
(12) depositing an ion implantation silicon dioxide masking layer, exposing the surface of the grid polysilicon by adopting a chemical mechanical polishing process, and keeping and filling silicon dioxide at the V-shaped position;
(13) implanting ions into the grid polysilicon;
(14) and removing the ion-implanted silicon dioxide masking layer, and etching back the grid polysilicon to be flush with the silicon surface.
Wherein, the MOSFET in the step (1) is a 100V NMOS, the low-range resistivity is 0.001-0.003 ohm.cm, and the constant resistivity of the epitaxial layer is 0.3 ohm.cm.
Preferably, the thickness of the field oxide layer in the step (4) is 5000-6000A.
And (4) etching the shield grid polysilicon to a position 1.0-1.3 um below the silicon surface in the step (6).
Further, in the step (9), the silicon dioxide isolation layer in the groove is etched to a position 2000A-3000A above the shielding grid.
Preferably, the thickness of the gate oxide in the step (10) is 600A to 800A.
In addition, in the step (13), when the MOSFET is an NMOS, N-type ions are implanted.
Further, in the step (13), when the MOSFET is a PMOS, P-type ions are implanted.
Has the advantages that: compared with the prior art, the invention has the following remarkable advantages: according to the invention, a silicon dioxide layer is deposited in a V shape, silicon dioxide does not exist on other grid polysilicon planes, then ion implantation is carried out, the thickness of the silicon dioxide above the V-shaped grid polysilicon is different, the thickness of the silicon dioxide at the V-shaped tip position, namely the silicon dioxide at the thinnest position of the grid polysilicon, is the thickest, the ion implantation depth and concentration are the smallest, the concentration of the ion implantation is larger along with the reduction of the thickness of the silicon dioxide above the grid polysilicon, the other grid polysilicon planes are not covered by the silicon dioxide, and the concentration of the ion implantation is the largest; by utilizing the proportional relation between the doping concentration of the polycrystalline silicon and the etching rate, the higher the ion implantation concentration is, the higher the etching speed of the grid polycrystalline silicon is, so that the etching speed of the V-shaped position is V-shaped, and the position of the tip is the slowest.
Drawings
FIG. 1 is a schematic diagram of a SGT in the prior art;
FIG. 2 is a cross-sectional view of a prior art gate contact hole;
FIG. 3 is a cross-sectional view of a prior art source contact hole;
FIG. 4 is a schematic illustration of the deposition of a masking layer in accordance with the present invention;
FIG. 5 is a schematic diagram of masking layer etching in the present invention;
FIG. 6 is a schematic diagram of deep trench etching in the present invention;
FIG. 7 is a schematic diagram of the growth of a field oxide layer in the present invention;
FIG. 8 is a schematic illustration of the deposition of a shield gate polysilicon in accordance with the present invention;
FIG. 9 is a schematic diagram of the poly back etching of the shield gate of the present invention;
FIG. 10 is a schematic diagram of forming a gate trench in the present invention;
FIG. 11 is a schematic illustration of the deposition of a spacer layer in accordance with the present invention;
FIG. 12 is a schematic view of a back-etched isolation layer in accordance with the present invention;
FIG. 13 is a schematic illustration of growing a gate oxide layer in accordance with the present invention;
FIG. 14 is a schematic illustration of the deposition of gate polysilicon in accordance with the present invention;
FIG. 15 is a schematic illustration of the deposition of a masking layer in accordance with the present invention;
FIG. 16 is a schematic diagram of gate polysilicon ion implantation in accordance with the present invention;
FIG. 17 is a schematic diagram of gate poly etch back in the present invention.
Detailed Description
The technical scheme of the invention is further explained by combining the attached drawings.
The invention relates to a process method for solving polysilicon etching punch-through of an SGT-MOSFET grid, which comprises the following steps of:
(1) selecting an epitaxial wafer according to the characteristic requirements of the MOSFET, wherein the wafer consists of a substrate with low-range resistivity and an epitaxial layer with constant-value resistivity, carrying out epitaxial growth on the substrate to form an epitaxial layer 1, and growing a masking layer 2 on the epitaxial layer; wherein the masking layer is made of silicon oxide, silicon nitride or a combination of the two, and the masking layer is used for masking the following trench etching, as shown in fig. 4;
(2) depositing a layer of photoresist 3 on the masking layer 2, performing trench lithography, etching the photoresist and the masking layer to form a trench etching window 4, as shown in fig. 5;
(3) removing the photoresist, performing deep trench etching on the trench etching window by using the masking layer, and forming a deep trench 5 under the masking action of the masking layer; wherein the depth of the deep groove is 3-6 um, as shown in figure 6;
(4) carrying out sacrificial oxidation on the surface of the epitaxial layer, and removing an oxide layer, wherein the sacrificial oxide layer generally grows to be about 500A and mainly plays a role in eliminating lattice damage of a silicon wall caused by etching and removing surface impurities; growing a layer of field oxide layer 6 on the side wall and the bottom of the deep trench, wherein the thickness of the field oxide layer 6 is 5000-6000A, as shown in figure 7;
(5) depositing a shielding gate polysilicon 7, filling the deep trench with the shielding gate polysilicon, and depositing a layer of shielding gate polysilicon on the surface of the masking layer, as shown in fig. 8;
(6) etching the shielding gate polysilicon, etching the shielding gate polysilicon in the deep trench to a position 1.0-1.3 um below the silicon surface, and etching away a layer of shielding gate polysilicon on the surface of the masking layer, as shown in fig. 9;
(7) etching back the masking layer to make the boundary of the masking layer and the boundary of the trench aligned up and down, as shown in fig. 10;
(8) depositing a silicon dioxide isolating layer 8 in the groove, and then thinning the silicon dioxide isolating layer to be flush with the masking layer 2 by adopting a chemical mechanical grinding process, as shown in figure 11;
(9) etching the silicon dioxide isolation layer in the groove to 2000A-3000A above the shielding gate, forming a gate groove 9, and then removing the masking layer 2, as shown in FIG. 12;
(10) growing a gate oxide layer, and forming gate oxide 10 on the side walls of the two sides of the gate trench and the silicon surface, wherein the thickness of the gate oxide is 600-800A, as shown in FIG. 13;
(11) depositing gate polysilicon 11, wherein the gate polysilicon at the groove is in a V shape, as shown in FIG. 14;
(12) depositing an ion implantation silicon dioxide masking layer 12, exposing the surface of the grid polysilicon by adopting a chemical mechanical polishing process, and keeping silicon dioxide at the V-shaped position and filling the silicon dioxide, as shown in figure 15;
(13) injecting grid polysilicon by ions, and injecting N-type ions when the MOSFET is an NMOS; when the MOSFET is PMOS, P-type ions are implanted, as shown in FIG. 16;
(14) removing the ion-implanted silicon dioxide masking layer, and etching back the gate polysilicon to be flush with the silicon surface, as shown in fig. 17;
(15) and performing ion implantation in the well region/source region, depositing a dielectric layer, etching the contact hole, depositing metal, depositing a passivation layer, and forming a drain electrode by using a back metal coating.
Example 1
The process method for solving the problem of polysilicon etching punch-through of the SGT-MOSFET gate comprises the following steps of:
(1) selecting an epitaxial wafer according to the characteristic requirements of the MOSFET, wherein the wafer consists of a substrate with low-range resistivity and an epitaxial layer with constant-value resistivity, carrying out epitaxial growth on the substrate to form an epitaxial layer 1, and growing a masking layer 2 on the epitaxial layer; the MOSFET is a 100V NMOS, the low-range resistivity is 0.001-0.003 ohm.cm, and the constant value resistivity of the epitaxial layer is 0.3 ohm.cm;
(2) depositing a layer of photoresist 3 on the masking layer 2, performing groove photoetching, etching the photoresist and the masking layer, and etching a groove etching window 4;
(3) removing the photoresist, performing deep trench etching on the trench etching window by using the masking layer, and forming a deep trench 5 under the masking action of the masking layer;
(4) carrying out sacrificial oxidation on the surface of the epitaxial layer, and removing the oxide layer; growing a layer of field oxide layer 6 on the side wall and the bottom of the deep groove, wherein the thickness of the field oxide layer 6 is 5000A;
(5) depositing a shielding grid polysilicon 7, filling the deep trench with the shielding grid polysilicon, and simultaneously depositing a layer of shielding grid polysilicon on the surface of the masking layer;
(6) etching the shielding grid polysilicon, etching the shielding grid polysilicon in the deep groove to a position 1.2um below the silicon surface, and etching away a layer of shielding grid polysilicon on the surface of the masking layer;
(7) the masking layer is etched back, so that the boundary of the masking layer is vertically aligned with the boundary of the groove;
(8) depositing a silicon dioxide isolating layer 8 in the groove, and then thinning the silicon dioxide isolating layer to be flush with the masking layer 2 by adopting a chemical mechanical grinding process;
(9) etching the silicon dioxide isolation layer in the groove to 3000A above the shielding gate, forming a gate groove 9, and then removing the masking layer 2;
(10) growing a gate oxide layer, and forming gate oxide 10 on the side walls of two sides of the gate trench and the silicon surface, wherein the thickness of the gate oxide is 600A;
(11) depositing grid polysilicon 11, wherein the grid polysilicon at the groove is in a V shape;
(12) depositing ion implantation silicon dioxide masking layer 12, exposing the surface of the grid polysilicon by adopting a chemical mechanical polishing process, and keeping silicon dioxide at the V-shaped position and filling;
(13) implanting ions into the grid polysilicon and implanting N-type ions;
(14) removing the ion-implanted silicon dioxide masking layer, and etching back the grid polysilicon to be flush with the silicon surface;
(15) and performing ion implantation in the well region/source region, depositing a dielectric layer, etching the contact hole, depositing metal, depositing a passivation layer, and forming a drain electrode by using a back metal coating.
According to the invention, a silicon dioxide layer is deposited in a V shape, silicon dioxide does not exist on other grid polysilicon planes, then ion implantation is carried out, the thickness of the silicon dioxide above the V-shaped grid polysilicon is different, the thickness of the silicon dioxide at the V-shaped tip position, namely the silicon dioxide at the thinnest position of the grid polysilicon, is the thickest, the ion implantation depth and concentration are the smallest, the concentration of the ion implantation is larger along with the reduction of the thickness of the silicon dioxide above the grid polysilicon, the other grid polysilicon planes are not covered by the silicon dioxide, and the concentration of the ion implantation is the largest; by utilizing the proportional relation between the doping concentration of the polycrystalline silicon and the etching rate, the higher the ion implantation concentration is, the higher the etching speed of the grid polycrystalline silicon is, so that the etching speed of the V-shaped position is V-shaped, and the position of the tip is the slowest.
Claims (8)
1. A process method for solving polysilicon etching punch-through of an SGT-MOSFET grid is characterized by comprising the following steps:
(1) selecting an epitaxial wafer according to the characteristic requirements of the MOSFET, wherein the wafer consists of a substrate with low-range resistivity and an epitaxial layer with constant-value resistivity, carrying out epitaxial growth on the substrate to form an epitaxial layer (1), and growing a masking layer (2) on the epitaxial layer;
(2) depositing a layer of photoresist (3) on the masking layer (2), carrying out groove photoetching, etching the photoresist and the masking layer, and etching a groove etching window (4);
(3) removing the photoresist, performing deep trench etching on the trench etching window by using the masking layer, and forming a deep trench (5) under the masking action of the masking layer;
(4) carrying out sacrificial oxidation on the surface of the epitaxial layer, and removing the oxide layer; growing a layer of field oxide layer (6) on the side wall and the bottom of the deep groove;
(5) depositing a shielding grid polysilicon (7), filling the deep trench with the shielding grid polysilicon, and simultaneously depositing a layer of shielding grid polysilicon on the surface of the masking layer;
(6) etching the shielding grid polysilicon, etching the shielding grid polysilicon in the deep groove to be below the surface of the silicon, and etching away a layer of shielding grid polysilicon on the surface of the masking layer;
(7) the masking layer is etched back, so that the boundary of the masking layer is vertically aligned with the boundary of the groove;
(8) depositing a silicon dioxide isolating layer (8) in the groove, and then thinning the silicon dioxide isolating layer to be flush with the masking layer (2) by adopting a chemical mechanical grinding process;
(9) etching the silicon dioxide isolation layer in the groove to a position above the shielding grid by a certain distance, forming a grid groove (9), and then removing the masking layer (2);
(10) growing a gate oxide layer, and forming gate oxide (10) on the side walls of two sides of the gate trench and on the silicon surface;
(11) depositing grid polysilicon (11), wherein the grid polysilicon at the groove is in a V shape;
(12) depositing an ion implantation silicon dioxide masking layer (12), exposing the surface of the grid polysilicon by adopting a chemical mechanical polishing process, and keeping and filling silicon dioxide at the V-shaped position;
(13) implanting ions into the grid polysilicon;
(14) and removing the ion-implanted silicon dioxide masking layer, and etching back the grid polysilicon to be flush with the silicon surface.
2. The process method for solving polysilicon etch punch-through of an SGT-MOSFET gate according to claim 1, wherein: in the step (1), the MOSFET is a 100V NMOS, the low-range resistivity is 0.001-0.003 ohm.cm, and the constant resistivity of the epitaxial layer is 0.3 ohm.cm.
3. The process method for solving polysilicon etch punch-through of an SGT-MOSFET gate according to claim 1, wherein: the thickness of the field oxide layer (6) in the step (4) is 5000-6000A.
4. The process method for solving polysilicon etch punch-through of an SGT-MOSFET gate according to claim 1, wherein: and (5) etching the shield grid polysilicon to a position 1.0-1.3 um below the silicon surface in the step (6).
5. The process method for solving polysilicon etch punch-through of an SGT-MOSFET gate according to claim 1, wherein: and (5) etching the silicon dioxide isolating layer in the groove to 2000-3000A above the shielding grid in the step (9).
6. The process method for solving polysilicon etch punch-through of an SGT-MOSFET gate according to claim 1, wherein: the thickness of the gate oxide in the step (10) is 600-800A.
7. The process method for solving polysilicon etch punch-through of an SGT-MOSFET gate according to claim 1, wherein: and (3) when the MOSFET is an NMOS, injecting N-type ions.
8. The process method for solving polysilicon etch punch-through of an SGT-MOSFET gate according to claim 1, wherein: and (3) when the MOSFET is a PMOS, injecting P-type ions in the step (13).
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115621201A (en) * | 2022-10-31 | 2023-01-17 | 上海功成半导体科技有限公司 | Manufacturing method of shielded gate power device and shielded gate power device |
| CN115692319A (en) * | 2022-10-31 | 2023-02-03 | 上海功成半导体科技有限公司 | Manufacturing method of shielded gate power device and shielded gate power device |
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2021
- 2021-08-06 CN CN202110900618.3A patent/CN113690143A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115621201A (en) * | 2022-10-31 | 2023-01-17 | 上海功成半导体科技有限公司 | Manufacturing method of shielded gate power device and shielded gate power device |
| CN115692319A (en) * | 2022-10-31 | 2023-02-03 | 上海功成半导体科技有限公司 | Manufacturing method of shielded gate power device and shielded gate power device |
| CN115692319B (en) * | 2022-10-31 | 2023-07-21 | 上海功成半导体科技有限公司 | Manufacturing method of shielded gate power device and shielded gate power device |
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