CN111785619A - Process method for shielding trench of gate trench type MOSFET - Google Patents
Process method for shielding trench of gate trench type MOSFET Download PDFInfo
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- CN111785619A CN111785619A CN202010608772.9A CN202010608772A CN111785619A CN 111785619 A CN111785619 A CN 111785619A CN 202010608772 A CN202010608772 A CN 202010608772A CN 111785619 A CN111785619 A CN 111785619A
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- 238000000034 method Methods 0.000 title claims abstract description 65
- 230000008569 process Effects 0.000 title claims abstract description 41
- 239000010410 layer Substances 0.000 claims abstract description 125
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 60
- 229920005591 polysilicon Polymers 0.000 claims abstract description 46
- 238000000151 deposition Methods 0.000 claims abstract description 26
- 238000005530 etching Methods 0.000 claims abstract description 23
- 230000001681 protective effect Effects 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000004065 semiconductor Substances 0.000 claims abstract description 15
- 239000011229 interlayer Substances 0.000 claims abstract description 7
- 238000011049 filling Methods 0.000 claims abstract description 6
- 238000002955 isolation Methods 0.000 claims abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 7
- 150000004767 nitrides Chemical class 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 3
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 claims description 3
- 238000000227 grinding Methods 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 238000000407 epitaxy Methods 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 claims 1
- 230000006872 improvement Effects 0.000 description 9
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000001000 micrograph Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 210000000746 body region Anatomy 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
Abstract
The invention discloses a process method for shielding a trench of a gate trench MOSFET, which comprises the following steps: depositing a hard mask layer on a semiconductor substrate, etching to form a plurality of grooves, forming a dielectric layer in the grooves, depositing and filling polycrystalline silicon, and forming a lower electrode in the grooves after back etching is finished; depositing a protective dielectric layer on the upper half part of the groove; step three, a layer of polycrystalline silicon interlayer oxide layer is integrally deposited in the groove; step four, performing a CMP process on the deposited inter-polysilicon oxide layer; and step five, continuing to perform an etching process on the inter-polysilicon oxide layer to enable the remaining inter-polysilicon oxide layer in the trench to reach the designed thickness and become an isolation medium layer between the upper polysilicon and the lower polysilicon. The process method of the invention protects the side wall of the groove, especially the corner of the top of the groove, by a layer of protective oxide layer, can obtain the nearly vertical side wall appearance of the groove, and improves the problem of short channel of the groove.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a process method for shielding a trench of a gate trench type MOSFET.
Background
The groove type double-layer grid MOS is used as a power device and has the characteristics of high breakdown voltage, low on-resistance and high switching speed. The structure of the shielded gate trench type MOSFET is divided into an upper part and a lower part, the lower part of the trench is filled with polysilicon as a source electrode, the upper part of the trench is filled with polysilicon as a gate electrode, and the gate electrode, the source electrode and the trench are isolated by oxide layers. The method is characterized in that polycrystalline silicon filled in the source electrode groove only occupies about half of the inner space of the groove, so that a source electrode contact hole can be contacted with the polycrystalline silicon filled at the lower part of the groove only by being made deeper. Depositing an oxide layer on a silicon substrate as a hard mask, defining a pattern on the hard mask by using photoresist, removing the photoresist, etching the substrate by using the pattern defined by the hard mask to form a groove, chamfering the groove, depositing an oxide layer, filling the groove with a first layer of polycrystalline silicon, performing back etching to form a source electrode, depositing a thick oxide layer, and forming an inter-polycrystalline silicon oxide film after CMP and wet process etching; and depositing polysilicon, etching to form a grid, and finally performing subsequent processes such as body region injection and propulsion, source electrode injection and propulsion, interlayer dielectric deposition and the like.
When a 100V shielded gate trench type MOSFET product is used for manufacturing an inter-polysilicon dielectric layer, because a liner oxide layer on the side wall of a trench is thin, the top edge of the trench becomes rounded after the deposition of the inter-polysilicon dielectric layer, namely, the inner wall of the trench gradually and smoothly transitions upwards to the silicon surface at the top of the trench, as shown in FIG. 1, the top edge of the trench formed under the prior art process is microscopically schematic, and the corner rounding of the top of the trench and the vertical appearance are damaged are shown in a dotted frame in the figure. The feature is implanted into the junction deep and deep when the channel source region is implanted subsequently, so that the problems of short channel and the like are caused, and the saturated leakage current I of the display device is displayed when the probe test is carried out on the rear sectionDSSLarge and threshold voltage VthInstability and the like. Therefore, we need the top corner of the trench to be as close to 90 ° as possible to the ideal.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a process method for shielding a trench of a gate trench type MOSFET, so as to avoid the problem of chamfering the top of the trench.
In order to solve the above problems, the process method for shielding the trench of the gate trench MOSFET of the present invention comprises the following process steps:
step one, depositing a hard mask layer on a semiconductor substrate, etching and patterning the hard mask layer, etching the semiconductor substrate by taking the patterned hard mask layer as a shield to form a plurality of grooves, forming a dielectric layer in the grooves and depositing and filling polycrystalline silicon, and forming a lower electrode in the grooves after back etching is finished;
depositing a protective dielectric layer on the upper half part of the groove;
step three, a layer of polycrystalline silicon interlayer oxide layer is integrally deposited in the groove;
step four, performing a CMP process on the deposited inter-polysilicon oxide layer;
and step five, continuing to perform an etching process on the inter-polysilicon oxide layer to enable the remaining inter-polysilicon oxide layer in the trench to reach the designed thickness and become an isolation medium layer between the upper polysilicon and the lower polysilicon.
The further improvement is that the semiconductor substrate in the step one is a silicon substrate or a silicon epitaxy; the hard mask layer is an ONO layer.
The further improvement is that the protective dielectric layer in the second step is deposited by an APCVD method, and the formed protective dielectric layer is attached to the upper part of the groove, including the side wall of the hard mask layer and the upper surface of the polysilicon at the inner lower part of the groove.
In a further improvement, the thickness of the protective dielectric layer formed in the second step is
A thermal annealing step is also included after the deposition is completed.
In a further improvement, the inter-polysilicon oxide layer deposited in the third step fills the trench and is deposited entirely on the surface of the semiconductor substrate to cover the hard mask layer.
In a further improvement, in the fourth step, the deposited inter-polysilicon oxide layer is subjected to CMP, and a nitride layer in the hard mask layer is taken as a polishing stop point and polished to the surface of the nitride layer in the ONO layer.
The further improvement is that in the fifth step, a wet etching process is adopted to etch the residual silicon nitride layer and the residual oxide layer in the hard mask and the deposited oxide layer between the polycrystalline silicon layers, wherein the etching process comprises the step of removing the protective dielectric layer on the side wall of the groove; finally, the residual inter-polysilicon oxide layer above the lower polysilicon in the trench reaches a predetermined thickness.
In a further improvement, the method further comprises a subsequent process step of depositing a second layer of polysilicon in the trench and etching back to form the trench upper electrode.
According to the process method for the trench of the shielded gate trench type MOSFET, a protective oxide layer is formed before deposition of a polycrystalline silicon interlayer dielectric oxide layer, the side wall of the trench, particularly the corner of the top of the trench, is protected, the phenomenon that the corner of the top of the trench is chamfered and becomes rounded in the subsequent process is avoided, the nearly vertical side wall morphology of the trench can be obtained, and the problem of short trench is solved.
Drawings
Figure 1 is a micrograph of the top of a trench formed by a prior art process.
FIGS. 2 to 6 are schematic views of the process steps involved in the present invention.
Figure 7 is a micrograph of the top of a trench formed by the process of the present invention.
FIG. 8 is a flow chart of the process steps of the present invention.
Description of the reference numerals
The structure comprises a semiconductor substrate 1, a trench bottom dielectric layer 2, a trench lower polysilicon layer 3, a hard mask layer 4, a protective dielectric layer 5 and a polysilicon interlayer dielectric layer 6.
Detailed Description
The invention relates to a process method for a groove of a shielded gate groove type MOSFET, which mainly aims at a polysilicon filling process of the groove of the shielded gate groove type MOSFET and mainly solves the problem that the top of the groove is chamfered after a polysilicon interlayer dielectric layer of the groove is deposited.
The invention relates to a process method for shielding a groove of a grid groove type MOSFET, which comprises the following process steps:
first, as shown in fig. 2, a hard mask layer is deposited on a semiconductor substrate, such as a silicon substrate or an epitaxial layer, in this embodiment, an ONO layer is used as an example of the hard mask layer, i.e., an oxide layer-a nitride layer-an oxide layer are sequentially deposited on a surface of the semiconductor substrate to form an ONO composite layer. Etching and patterning the hard mask layer, etching the semiconductor substrate by taking the patterned hard mask layer as a shield to form a plurality of grooves (only one groove is shown in the figure of the embodiment), forming a dielectric layer in the grooves and depositing and filling polysilicon, and forming a lower electrode in the groove after back etching is completed;
step two, as shown in fig. 3, depositing a protective dielectric layer on the upper half part of the groove; preferably, APCVD is adopted for deposition, and the formed protective dielectric layer is attached to the upper surface of the polysilicon on the upper part of the groove, including the side wall of the hard mask layer and the inner lower part of the groove. Forming a protective dielectric layer with a thickness of
Such as
Some thermal annealing steps are also performed after the deposition is completed.
Step three, as shown in fig. 4, a layer of inter-polysilicon layer oxide is integrally deposited in the trench; the deposited inter-polysilicon oxide layer fills the trench and is deposited entirely on the surface of the semiconductor substrate, covering the ONO hard mask layer entirely.
Step four, as shown in fig. 5, a CMP process is performed on the deposited inter-polysilicon oxide layer; and grinding downwards from the surface of the deposited film to the surface of the nitride layer in the ONO layer by taking the nitride layer in the hard mask layer as a grinding termination point.
Step five, continuing to perform a wet etching process on the inter-polysilicon-layer oxide layer, and etching the remaining silicon nitride layer and the oxide layer in the hard mask and the deposited inter-polysilicon-layer oxide layer, including removing the protective dielectric layer on the side wall of the trench, as shown in fig. 6; the rest inter-polysilicon oxide layer in the trench reaches the designed thickness and becomes an isolation dielectric layer between the upper polysilicon and the lower polysilicon.
According to the process, before the inter-polysilicon oxide layer is deposited, a protective oxide layer is formed on the inner wall of the groove, the subsequent inter-polysilicon oxide layer deposition process is placed to enable the top corner of the groove to be rounded, and when a source region is injected due to the rounded corner, the injection junction is too deep, so that a short channel effect is caused. The invention deposits the protective layer to protect the side wall of the groove, and ensures that the shape of the top of the groove is not influenced, thereby obtaining the top of the groove with almost right angle and improving the performance of the device.
As shown in fig. 7, which is a cross-sectional micrograph of a trench formed after the inventive process, the dashed box in the figure shows that the top corner of the trench is nearly a 90 ° right angle, with a significant improvement in top topography compared to fig. 1.
After the process of the present invention, the process further includes the following conventional process steps, that is, the second layer of polysilicon is deposited in the trench and etched back to form the upper electrode of the trench, and then the processes of ion implantation to form the source region, etc. are well known technologies and will not be described herein again.
The above are merely preferred embodiments of the present invention, and are not intended to limit the present invention. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. A process method for shielding a trench of a gate trench MOSFET is characterized in that: comprises the following process steps:
step one, depositing a hard mask layer on a semiconductor substrate, etching and patterning the hard mask layer, etching the semiconductor substrate by taking the patterned hard mask layer as a shield to form a plurality of grooves, forming a dielectric layer in the grooves and depositing and filling polycrystalline silicon, and forming a lower electrode in the grooves after back etching is finished;
depositing a protective dielectric layer on the upper half part of the groove;
step three, a layer of polycrystalline silicon interlayer oxide layer is integrally deposited in the groove;
step four, performing a CMP process on the deposited inter-polysilicon oxide layer;
and step five, continuing to perform an etching process on the inter-polysilicon oxide layer to enable the remaining inter-polysilicon oxide layer in the trench to reach the designed thickness and become an isolation medium layer between the upper polysilicon and the lower polysilicon.
2. The process of forming a trench for a shielded gate trench MOSFET of claim 1 further comprising: the semiconductor substrate in the first step is a silicon substrate or a silicon epitaxy; the hard mask layer is an ONO layer.
3. The process of forming a trench for a shielded gate trench MOSFET of claim 1 further comprising: and depositing the protective dielectric layer in the second step by adopting an APCVD method, wherein the formed protective dielectric layer is attached to the upper part of the groove, including the side wall of the hard mask layer and the upper surface of the polycrystalline silicon at the inner lower part of the groove.
4. The process of forming a trench for a shielded gate trench MOSFET of claim 1 further comprising: in the second step, the thickness of the protective dielectric layer is formed
A thermal annealing step is also included after the deposition is completed.
5. The process of forming a trench for a shielded gate trench MOSFET of claim 1 further comprising: and filling the inter-polysilicon oxidation layer deposited in the third step into the groove and integrally depositing on the surface of the semiconductor substrate to cover the hard mask layer.
6. The process method of the trench of the shielded gate trench MOSFET of claim 1 or 2, characterized in that: and in the fourth step, CMP is carried out on the deposited inter-polysilicon oxide layer, and the nitride layer in the hard mask layer is taken as a grinding termination point and is ground to the surface of the nitride layer in the ONO layer.
7. The process of forming a trench for a shielded gate trench MOSFET of claim 1 further comprising: in the fifth step, a wet etching process is adopted to etch the residual silicon nitride layer and the residual oxide layer in the hard mask and the deposited oxide layer between the polycrystalline silicon layers, wherein the etching process comprises the step of removing the protective dielectric layer on the side wall of the groove; finally, the residual inter-polysilicon oxide layer above the lower polysilicon in the trench reaches a predetermined thickness.
8. The process of forming a trench for a shielded gate trench MOSFET of claim 1 further comprising: and the subsequent process step of depositing a second layer of polysilicon in the trench and etching back to form the upper electrode of the trench.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010608772.9A CN111785619A (en) | 2020-06-30 | 2020-06-30 | Process method for shielding trench of gate trench type MOSFET |
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| CN202010608772.9A CN111785619A (en) | 2020-06-30 | 2020-06-30 | Process method for shielding trench of gate trench type MOSFET |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112750696A (en) * | 2020-12-31 | 2021-05-04 | 广州粤芯半导体技术有限公司 | Preparation method of groove type power device |
| CN113725078A (en) * | 2021-09-11 | 2021-11-30 | 捷捷微电(上海)科技有限公司 | Manufacturing method of split gate MOSFET |
| CN115985954A (en) * | 2023-01-04 | 2023-04-18 | 深圳吉华微特电子有限公司 | Manufacturing method for improving polycrystalline morphology of SGT product |
| CN117393501A (en) * | 2023-12-07 | 2024-01-12 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
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| CN104022043A (en) * | 2014-06-16 | 2014-09-03 | 中航（重庆）微电子有限公司 | Groove type power MOSFET with split gates and manufacturing method |
| CN105448741A (en) * | 2015-12-31 | 2016-03-30 | 上海华虹宏力半导体制造有限公司 | Shield grid groove type MOSFET process method |
| CN108735605A (en) * | 2018-01-23 | 2018-11-02 | 西安龙腾新能源科技发展有限公司 | Improve the shield grid groove MOSFET manufacturing method of channel bottom field plate pattern |
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2020
- 2020-06-30 CN CN202010608772.9A patent/CN111785619A/en active Pending
Patent Citations (4)
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| US20120235229A1 (en) * | 2011-03-16 | 2012-09-20 | Probst Dean E | Inter-poly dielectric in a shielded gate mosfet device |
| CN104022043A (en) * | 2014-06-16 | 2014-09-03 | 中航（重庆）微电子有限公司 | Groove type power MOSFET with split gates and manufacturing method |
| CN105448741A (en) * | 2015-12-31 | 2016-03-30 | 上海华虹宏力半导体制造有限公司 | Shield grid groove type MOSFET process method |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112750696A (en) * | 2020-12-31 | 2021-05-04 | 广州粤芯半导体技术有限公司 | Preparation method of groove type power device |
| CN113725078A (en) * | 2021-09-11 | 2021-11-30 | 捷捷微电(上海)科技有限公司 | Manufacturing method of split gate MOSFET |
| CN115985954A (en) * | 2023-01-04 | 2023-04-18 | 深圳吉华微特电子有限公司 | Manufacturing method for improving polycrystalline morphology of SGT product |
| CN117393501A (en) * | 2023-12-07 | 2024-01-12 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN117393501B (en) * | 2023-12-07 | 2024-03-19 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
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Application publication date: 20201016 |