CN111564413A - Fin structure manufacturing method - Google Patents
Fin structure manufacturing method Download PDFInfo
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- CN111564413A CN111564413A CN202010138884.2A CN202010138884A CN111564413A CN 111564413 A CN111564413 A CN 111564413A CN 202010138884 A CN202010138884 A CN 202010138884A CN 111564413 A CN111564413 A CN 111564413A
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- fin structure
- oxide layer
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- active region
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 238000000151 deposition Methods 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000004140 cleaning Methods 0.000 claims abstract description 15
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 13
- 230000003647 oxidation Effects 0.000 claims abstract description 12
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 12
- 238000009966 trimming Methods 0.000 claims abstract description 7
- 230000007547 defect Effects 0.000 claims abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 41
- 238000005452 bending Methods 0.000 abstract description 10
- 238000010586 diagram Methods 0.000 description 6
- 238000000137 annealing Methods 0.000 description 4
- 208000032750 Device leakage Diseases 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a fin structure manufacturing method for FinFET manufacturing process, which comprises the steps of forming a fin structure graph; after etching the substrate to form a fin structure, removing the photoresist and cleaning; a hard mask oxidation layer, an active region liner silicon nitride layer and an active region liner oxidation layer are sequentially formed on the top of each fin structure from top to bottom; repairing defects caused by etching; depositing a first filling seed layer; the first filling covers the fin structure; the hard mask oxide layer is removed through first planarization until the silicon nitride layer is lined in the active area; trimming the fin structure to ensure that the fin structure only exists right above the active region; the second filling covers the fin structure; flattening for the second time; removing and cleaning the mask; etching back to expose the upper part of the fin structure; and forming a gate oxide layer on the fin structure. The filling structure at the lower part of the fin structure can effectively reduce the bending of the fin body of the fin transistor, can improve the stability of leakage current of the device, and further can improve the performance stability of the device.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a fin structure manufacturing method for FinFETs.
Background
FinFETs are fully known as Fin Field-Effect transistors, and are called FinFETs in Chinese, and are new CMOS transistors.
In recent years, finfets have become a popular and mature advanced CMOS technology due to their advantages of increased transistor density and increased electrical performance. As line widths shrink to 16nm or less, the critical dimensions and depth of fin structures are increasingly challenging, with fin structures having aspect ratios of 6: 1; in this case, mechanical and structural imbalances where the fin structure becomes less powerful than the planar structure will result in some unexpected failures. The existing fin structure manufacturing method mainly comprises the following steps: forming a fin structure pattern, forming a fin structure, forming a substrate oxidation layer, trimming the fin structure, depositing the oxidation layer on the substrate, filling the groove and flattening, removing the mask, and performing back etching to form gate oxide.
Fin bending (Fin bending) is one of the many failures encountered in technology development, and typical Fin bending may lead to electrical or physical failures; the inclination angle of the structure leads to an asymmetric depletion region, so that the leakage current is larger than expected; at the same time, the fin bending compresses the metal gate deposition process window and is highly likely to form voids.
Disclosure of Invention
In this summary, a series of simplified form concepts are introduced that are simplifications of the prior art in this field, which will be described in further detail in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
The technical problem to be solved by the present invention is to provide a method for fabricating a fin structure capable of avoiding the occurrence of fin bending,
in order to solve the above technical problem, the present invention provides a fin structure manufacturing method for a FinFET manufacturing process, including the steps of:
s1, forming a fin structure pattern;
s2, after etching the substrate to form a fin structure, removing the photoresist and cleaning; a hard mask oxidation layer, an active region liner silicon nitride layer and an active region liner oxidation layer are sequentially formed on the top of each fin structure from top to bottom;
s3, repairing defects caused by etching;
alternatively, step S3 includes the following sub-steps;
s3.1, pre-cleaning an oxide layer of the groove substrate;
and S3.2, forming a trench substrate oxidation layer in the trench.
S4, depositing a first filling seed layer;
alternatively, an ALD process is used to deposit an oxide layer as the first fill seed layer.
S5, covering the fin structure by first filling;
optionally, step S5 is performed by depositing a fill oxide layer and performing a thermal anneal to form the cap.
S6, flattening for the first time, removing the hard mask oxide layer until the active area is lined with the silicon nitride layer (mask);
in step S6, the FCVD process is planarized by depositing a fill oxide layer.
S7, trimming the fin structure to enable the fin structure to only exist right above the active region;
alternatively, step S7 includes the following sub-steps;
s7.1, removing two adjacent fin structures in the active region through the whole fin structure;
and S7.2, removing the part of the fin structure right above the active region, which is positioned outside the active region, and removing all the remaining fin structures positioned outside the active region.
S8, covering the fin structure by the second filling;
optionally, step S8 is performed by depositing a filling oxide layer and performing a thermal anneal to fill the trench for the HARP process.
S9, flattening for the second time;
optionally, step S9 is performed to planarize the deposited pad oxide layer of the HARP process.
S10, removing and cleaning the mask, and removing the active area pad silicon nitride layer until reaching the active area pad oxide layer;
s11, etching back to remove the pad oxide layer of the active area and part of the groove substrate oxide layer to expose the upper part of the fin structure;
and S12, forming a gate oxide layer on the fin structure.
The method comprises the steps of depositing a filling oxide layer by an FCVD (plasma chemical vapor deposition) process, carrying out thermal annealing and planarization, finishing a fin structure, depositing the filling oxide layer by an HARP (hydrogen-activated plasma) process, carrying out thermal annealing and planarization, removing and cleaning a mask, and carrying out back etching to form the fin structure. The filling structure arranged at the lower part of the fin structure can effectively reduce the bending of the fin body of the fin transistor. When typical fin bending occurs, the inclination angle of the fin structure leads to an asymmetric depletion region, so that the device leakage current is larger than expected, the device performance is reduced, the fin bending is reduced, the stability of the device leakage current can be improved, and the device performance stability can be improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention, are incorporated in and constitute a part of this specification. The drawings are not necessarily to scale, however, and may not be intended to accurately reflect the precise structural or performance characteristics of any given embodiment, and should not be construed as limiting or restricting the scope of values or properties encompassed by exemplary embodiments in accordance with the invention. The invention will be described in further detail with reference to the following detailed description and accompanying drawings:
fig. 1 is a flow chart illustrating a method for fabricating a fin structure according to the present invention.
Fig. 2 is a first structural schematic diagram of a fin structure fabrication method according to the present invention, which shows the formation of a fin structure on a substrate.
Fig. 3 is a structural diagram of a second fin structure fabrication method according to the present invention, which shows FCVD process deposition filling.
Fig. 4 is a third schematic structural diagram of the fin structure fabrication method of the present invention, which shows the planarization of the filling oxide layer deposited by the FCVD process.
Fig. 5 is a fourth structural schematic diagram of the fin structure fabrication method of the present invention, showing the fin structure after trimming.
Fig. 6 is a structural diagram of a fin structure manufacturing method according to a fifth embodiment of the present invention, which shows the deposition and filling by the HARP process.
Fig. 7 is a sixth structural view of the fin structure fabrication method of the present invention, which shows the planarization of the deposited filling oxide layer by HARP process.
Fig. 8 is a seventh structural diagram of the fin structure fabrication method of the present invention, showing the top of the fin structure exposed by the etch-back.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and technical effects of the present invention will be fully apparent to those skilled in the art from the disclosure in the specification. The invention is capable of other embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the general spirit of the invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict. The following exemplary embodiments of the present invention may be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein. It is to be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the technical solutions of these exemplary embodiments to those skilled in the art.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, parameters, components, regions, steps, layers and/or sections, these elements, parameters, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, parameter, component, region, step, layer or section from another element, parameter, component, region, layer or section. Thus, a first element, parameter, component, region, layer or section discussed below could be termed a second element, parameter, component, region, step, layer or section without departing from the teachings of exemplary embodiments according to the present invention.
As shown in fig. 1, the present invention provides a first possible embodiment of a method for fabricating a fin structure for a FinFET fabrication process, comprising the steps of:
s1, forming a fin structure pattern
S2, as shown in fig. 2, after etching the substrate to form a fin structure, removing the photoresist and cleaning;
the step is manufactured by adopting the prior art, and a hard mask oxide layer, an active area liner silicon nitride and an active area liner oxide layer are formed on the top of each fin structure from top to bottom at one time;
s3, repairing defects caused by etching;
and S4, depositing an oxide layer as a first filling seed layer by adopting an ALD process.
S5, as shown in FIG. 3, a FCVD process is used to deposit a fill oxide layer and a thermal anneal is used to form the cap.
S6, as shown in FIG. 4, the FCVD process is carried out to deposit a filling oxide layer for planarization, and the hard mask oxide layer is removed until the active area is lined with a silicon nitride layer (mask);
s7, trimming the fin structure to make the fin structure only exist right above the active region, as shown in fig. 5;
s8, as shown in fig. 6, the trench is filled by depositing a filling oxide layer and performing a thermal anneal for the HARP process.
S9, as shown in fig. 7, the HARP process is planarized by depositing a filling oxide layer.
S10, removing and cleaning the mask, and removing the active area pad silicon nitride layer until reaching the active area pad oxide layer;
s11, as shown in fig. 8, etching back to remove the pad oxide layer of the active region and a portion of the trench substrate oxide layer to expose the upper portion of the fin structure;
and S12, forming a gate oxide layer on the fin structure.
In the first embodiment of the present invention, the fin structure is trimmed by depositing the filling oxide layer through the FCVD process, performing thermal annealing and planarization, depositing the filling oxide layer through the HARP process, performing thermal annealing and planarization, removing and cleaning the mask, and performing etch back to form the fin structure. The second filling structure (depositing and filling an oxide layer for the HARP process) at the lower part of the fin structure can effectively reduce the bending of the fin body of the fin transistor. And then promote the stability of device leakage current, and then can promote device stability of performance.
The invention provides a second possible embodiment of a method for fabricating a fin structure for a FinFET fabrication process, comprising the steps of:
s1, forming a fin structure pattern
S2, as shown in fig. 2, after etching the substrate to form a fin structure, removing the photoresist and cleaning;
the step is manufactured by adopting the prior art, and a hard mask oxide layer, an active area liner silicon nitride and an active area liner oxide layer are formed on the top of each fin structure from top to bottom at one time;
s3, pre-cleaning the oxidation layer of the groove substrate to form the oxidation layer of the groove substrate, and further repairing the defect caused by etching;
and S4, depositing an oxide layer as a first filling seed layer by adopting an ALD process.
S5, as shown in FIG. 3, a FCVD process is used to deposit a fill oxide layer and a thermal anneal is used to form the cap.
S6, as shown in FIG. 4, the FCVD process is carried out to deposit a filling oxide layer for planarization, and the hard mask oxide layer is removed until the active area is lined with a silicon nitride layer (mask);
s7, firstly, removing two adjacent fin structures of the active region completely;
and removing the part of the fin structure right above the active region, which is positioned outside the active region, and removing all the remaining fin structures positioned outside the active region.
Finishing trimming the fin structure to ensure that the fin structure only exists right above the active region;
s8, as shown in fig. 6, the trench is filled by depositing a filling oxide layer and performing a thermal anneal for the HARP process.
S9, as shown in fig. 7, the HARP process is planarized by depositing a filling oxide layer.
S10, removing and cleaning the mask, and removing the active area pad silicon nitride layer until reaching the active area pad oxide layer;
s11, as shown in fig. 8, etching back to remove the pad oxide layer of the active region and a portion of the trench substrate oxide layer to expose the upper portion of the fin structure;
and S12, forming a gate oxide layer on the fin structure.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The present invention has been described in detail with reference to the specific embodiments and examples, but these are not intended to limit the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (8)
1. A fin structure manufacturing method is used for FinFET manufacturing process and is characterized by comprising the following steps:
s1, forming a fin structure pattern;
s2, after etching the substrate to form a fin structure, removing the photoresist and cleaning; a hard mask oxidation layer, an active region liner silicon nitride layer and an active region liner oxidation layer are sequentially formed on the top of each fin structure from top to bottom;
s3, repairing defects caused by etching;
s4, depositing a first filling seed layer;
s5, covering the fin structure by first filling;
s6, removing the hard mask oxide layer until the silicon nitride layer is lined in the active area by first planarization;
s7, trimming the fin structure to enable the fin structure to only exist right above the active region;
s8, covering the fin structure by the second filling;
s9, flattening for the second time;
s10, removing and cleaning the mask;
s11, etching back to expose the upper part of the fin structure;
and S12, forming a gate oxide layer on the fin structure.
2. The method of fabricating a fin structure of claim 1, wherein: step S3 includes the following substeps;
s3.1, pre-cleaning an oxide layer of the groove substrate;
and S3.2, forming a trench substrate oxidation layer in the trench.
3. The method of fabricating a fin structure of claim 1, wherein: step S4 is performed by depositing an oxide layer as a first seed fill layer using an ALD process.
4. The method of fabricating a fin structure of claim 1, wherein: in step S5, an FCVD process is used to deposit a fill oxide layer and a thermal anneal is used to form the cap.
5. The method of fabricating a fin structure of claim 1, wherein: in step S6, the FCVD process is planarized by depositing a fill oxide layer.
6. The method of fabricating a fin structure of claim 1, wherein: step S7 includes the following substeps;
s7.1, removing two adjacent fin structures in the active region through the whole fin structure;
and S7.2, removing the part of the fin structure right above the active region, which is positioned outside the active region, and removing all the remaining fin structures positioned outside the active region.
7. The method of fabricating a fin structure of claim 1, wherein: in step S8, the HARP process is performed to deposit a filling oxide layer and a thermal anneal is performed to fill the trench.
8. The method of fabricating a fin structure of claim 1, wherein: step S9 is performed to planarize the deposited pad oxide layer of the HARP process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010138884.2A CN111564413A (en) | 2020-03-03 | 2020-03-03 | Fin structure manufacturing method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010138884.2A CN111564413A (en) | 2020-03-03 | 2020-03-03 | Fin structure manufacturing method |
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| CN111564413A true CN111564413A (en) | 2020-08-21 |
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| CN202010138884.2A Pending CN111564413A (en) | 2020-03-03 | 2020-03-03 | Fin structure manufacturing method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112271161A (en) * | 2020-10-26 | 2021-01-26 | 上海华力集成电路制造有限公司 | Method for improving Fin size of Fin type transistor |
| CN114038755A (en) * | 2021-10-25 | 2022-02-11 | 上海华力集成电路制造有限公司 | Etching method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105097536A (en) * | 2014-05-12 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Forming method of semiconductor structure |
| CN105826193A (en) * | 2015-01-07 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Formation method of semiconductor device |
| CN106057671A (en) * | 2015-04-16 | 2016-10-26 | 台湾积体电路制造股份有限公司 | Process of manufacturing Fin-FET device |
| CN109585289A (en) * | 2017-09-28 | 2019-04-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
-
2020
- 2020-03-03 CN CN202010138884.2A patent/CN111564413A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105097536A (en) * | 2014-05-12 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Forming method of semiconductor structure |
| CN105826193A (en) * | 2015-01-07 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Formation method of semiconductor device |
| CN106057671A (en) * | 2015-04-16 | 2016-10-26 | 台湾积体电路制造股份有限公司 | Process of manufacturing Fin-FET device |
| CN109585289A (en) * | 2017-09-28 | 2019-04-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112271161A (en) * | 2020-10-26 | 2021-01-26 | 上海华力集成电路制造有限公司 | Method for improving Fin size of Fin type transistor |
| CN114038755A (en) * | 2021-10-25 | 2022-02-11 | 上海华力集成电路制造有限公司 | Etching method |
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