CN112271161A - Method for improving Fin size of Fin type transistor - Google Patents

Method for improving Fin size of Fin type transistor Download PDF

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Publication number
CN112271161A
CN112271161A CN202011154128.5A CN202011154128A CN112271161A CN 112271161 A CN112271161 A CN 112271161A CN 202011154128 A CN202011154128 A CN 202011154128A CN 112271161 A CN112271161 A CN 112271161A
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fin
semiconductor structure
hard mask
layer
mask layer
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CN202011154128.5A
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巴文民
胡展源
刘厥扬
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Priority to CN202011154128.5A priority Critical patent/CN112271161A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

The invention provides a method for improving Fin transistor Fin size, which comprises providing a first semiconductor structure comprising a plurality of fins, wherein a first hard mask layer and a second hard mask layer are formed on the tops of the fins; a first thin oxide layer is formed on the side wall of the Fin; cutting off part of Fin in the multiple Fins together with the first hard mask layer, the second hard mask layer and the thin oxide layer to form a second semiconductor structure; forming a silicon buffer layer on the second semiconductor structure; covering a silicon oxide layer on the second semiconductor structure with the silicon buffer layer by adopting a fluid chemical vapor deposition method; and annealing the second semiconductor structure. In the manufacturing process of the FinFET device, in order to avoid the consumption of Fin in the FCVD and the subsequent annealing process, a silicon buffer layer is formed on the Fin before the FCVD process after Fin forming so as to neutralize the consumption of Fin in the FCVD and the subsequent annealing process, thereby ensuring that the shape and the size of Fin are not influenced.

Description

Method for improving Fin size of Fin type transistor
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for improving Fin size of a Fin transistor.
Background
Fin transistors (finfets) have become a popular advanced CMOS technology in recent years, which has the advantage of increasing transistor density and electrical performance compared to conventional devices. The morphology and size of the Fin in a device are critical to the electrical parameters of the device. The high temperature process after Fin formation affects the Fin shape and size, and after Fin formation, FCVD is performed directly, thereby consuming Fin during FCVD and the subsequent Anneal annex process, thereby changing Fin shape and size.
Therefore, a new method is needed to solve the above problems.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention is directed to a method for improving Fin size of a Fin-type transistor, so as to solve the problem in the prior art that after Fin formation in FinFET device fabrication, Fin consumption due to high temperature annealing causes changes in the shape and size of Fin.
To achieve the above and other related objects, the present invention provides a method for improving Fin size of a Fin transistor, the method comprising:
providing a first semiconductor structure comprising a plurality of Fins, wherein a first hard mask layer and a second hard mask layer are formed on the tops of the Fins; a first thin oxide layer is formed on the side wall of the Fin and the bottom of the first semiconductor structure between the Fin and the Fin;
step two, cutting off part of Fin in the multiple Fin together with the first hard mask layer, the second hard mask layer and the thin oxide layer to form a second semiconductor structure;
step three, forming a silicon buffer layer on the second semiconductor structure;
fourthly, covering a silicon oxide layer on the second semiconductor structure with the silicon buffer layer by adopting a fluid chemical vapor deposition method;
and fifthly, annealing the second semiconductor structure.
Preferably, in the first step, the first hard mask layer is formed on the top of the Fin, and the second hard mask layer is formed on the first hard mask layer.
Preferably, in the first step, the first hard mask layer is silicon oxide, and the second hard mask layer is silicon nitride.
Preferably, the reaction temperature for forming the silicon buffer layer on the second semiconductor structure in the third step is 300-400 ℃.
Preferably, the source gas used in the third step of forming the silicon buffer layer on the second semiconductor structure is disilane.
Preferably, the thickness of the silicon buffer layer formed on the second semiconductor structure in the third step is 1 to 3 nm.
Preferably, a second thin oxide layer is formed on the silicon buffer layer of the second semiconductor structure before the fluid chemical vapor deposition process is performed in step four.
Preferably, the method further comprises a sixth step of removing the first and second hard mask layers on top of the Fin.
Preferably, the method further comprises a seventh step of back etching the silicon oxide layer.
As described above, the method for improving Fin size of a Fin transistor according to the present invention has the following advantages: in the manufacturing process of the FinFET device, in order to avoid the consumption of Fin in the FCVD and the subsequent annealing process, a silicon buffer layer is formed on the Fin before the FCVD process after Fin forming so as to neutralize the consumption of Fin in the FCVD and the subsequent annealing process, thereby ensuring that the shape and the size of Fin are not influenced.
Drawings
FIG. 1 is a schematic diagram illustrating a vertical cross-sectional structure of a second semiconductor structure according to the present invention;
FIG. 2 is a schematic diagram of a second semiconductor structure having a silicon buffer layer formed thereon according to the present invention;
FIG. 3 is a schematic diagram of a silicon oxide layer formed by FCVD on a second semiconductor according to the present invention;
FIG. 4 is a schematic structural diagram of a second semiconductor after etchback of silicon oxide in accordance with the present invention;
fig. 5 is a flowchart illustrating a method for improving Fin size of a Fin transistor according to the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 5. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Fig. 5 shows a flowchart of a method for improving Fin size of a Fin transistor according to the present invention, and fig. 5 shows a flowchart of the method for improving Fin size of a Fin transistor according to the present invention. The method at least comprises the following steps:
providing a first semiconductor structure comprising a plurality of Fins, wherein a first hard mask layer and a second hard mask layer are formed on the tops of the Fins; a first thin oxide layer is formed on the side wall of the Fin and the bottom of the first semiconductor structure between the Fin and the Fin; in the first step, the first hard mask layer is formed on the top of the Fin, and the second hard mask layer is formed on the first hard mask layer. In the first step, the first hard mask layer is silicon oxide, and the second hard mask layer is silicon nitride.
As shown in fig. 1, fig. 1 is a schematic longitudinal sectional structure of a second semiconductor structure according to the present invention. The second semiconductor structure is formed after the first semiconductor structure cuts off a part of Fin, in fig. 1, the first semiconductor structure includes a plurality of fins (i.e., Fin structure 01 in the Fin transistor in fig. 1), in the first semiconductor structure, a first hard mask layer 03 is formed on the top of the Fin (Fin structure 01), further, the first hard mask layer 03 in this embodiment is silicon oxide; forming a second hard mask layer 04 on the first hard mask layer on the Fin; in yet another embodiment of the present invention, the second hard mask layer 04 is silicon nitride.
In this embodiment, a first thin oxide layer (liner oxide)02 is formed on a sidewall of the Fin (Fin structure 01) in the first semiconductor structure; as shown in fig. 1, the first thin oxide layer (liner oxide)02 is also formed on the bottom of the first semiconductor structure between the Fin and the Fin.
Step two, cutting off part of Fin in the multiple Fin together with the first hard mask layer, the second hard mask layer and the thin oxide layer to form a second semiconductor structure; as shown in fig. 1, fig. 1 exemplarily discloses that a portion Fin in the first semiconductor structure is cut, for example, two fins located at the right side of the third Fin in fig. 1 are cut, and the positions and the number of the cut fins are not limited in other embodiments. Part of the Fin in the first semiconductor structure is cut off to form the second semiconductor structure in FIG. 2 because the part is not needed in the subsequent process.
Step three, forming a silicon buffer layer on the second semiconductor structure; further, in the third step of the present embodiment, the reaction temperature for forming the silicon buffer layer on the second semiconductor structure is 300-400 ℃. Still further, in the third step of the present invention, the source gas for forming the silicon buffer layer on the second semiconductor structure is disilane. Furthermore, in the third step of the present embodiment, the thickness of the silicon buffer layer formed on the second semiconductor structure is 1 to 3 nm.
As shown in fig. 2, fig. 2 is a schematic structural diagram illustrating a silicon buffer layer formed on a second semiconductor structure according to the present invention. That is, in the third step of this embodiment, at a reaction temperature of 300 to 400 ℃, disilane is used as a reaction source gas, the silicon buffer layer 05 is formed on the second semiconductor, the silicon buffer layer 05 covers the first thin oxide layer 02, the sidewall of the first hard mask layer 03, the sidewall of the second hard mask layer 04, the upper surface of the second hard mask layer 04, and the silicon buffer layer 05 covers the upper surface of the cut-off Fin.
Fourthly, covering a silicon oxide layer on the second semiconductor structure with the silicon buffer layer by adopting a fluid chemical vapor deposition method; as shown in fig. 3, fig. 3 is a schematic structural view illustrating a silicon oxide layer formed by FCVD on a second semiconductor according to the present invention. And fourthly, covering a silicon oxide layer 06 on the second semiconductor structure on which the silicon buffer layer 05 is formed by adopting a Fluid Chemical Vapor Deposition (FCVD), wherein the silicon oxide layer 06 fills the space between the Fin and covers the upper surfaces of the silicon buffer layer 05 on the tops of the first hard mask and the second hard mask.
In the present invention, before the fluid chemical vapor deposition is performed in the fourth step, a second thin oxide layer is formed on the silicon buffer layer of the second semiconductor structure. The second thin oxide layer is not shown in fig. 3. That is, after the third step of the present invention, i.e., after the silicon buffer layer 05 is formed, the second thin oxide layer is formed on the silicon buffer layer, and then the fourth step of covering the silicon oxide layer 06 on the second semiconductor layer by FCVD is performed.
And fifthly, annealing the second semiconductor structure. And fifthly, annealing (Anneal) the second semiconductor structure after the FCVD, wherein the silicon buffer layer is formed on the side wall of the Fin of the second semiconductor structure, and is oxidized into silicon oxide in the high-temperature annealing process, so that the direct oxidation of the Fin without the silicon buffer layer is avoided.
And sixthly, removing the first hard mask layer and the second hard mask layer on the top of the Fin.
And seventhly, etching back the silicon oxide layer. The structure is shown in fig. 4, and fig. 4 is a schematic structural diagram of the second semiconductor after etching back the silicon oxide in the present invention. Since step five is performed at a high temperature, the silicon buffer layer is oxidized into silicon oxide, and the first and second thin oxide layers are both silicon oxide in the present invention, and therefore the silicon oxide formed by oxidizing the first and second thin oxide layers and the silicon buffer layer and the silicon oxide layer 06 are both silicon dioxide, the first and second thin oxide layers, the oxidized product of the silicon buffer layer and the silicon oxide layer 06 are shown in fig. 4 as being combined, that is, combined in the silicon oxide layer 06. Step seven, after etching back the silicon oxide layer 06, a part of the top of the Fin is exposed, and the structure shown in fig. 4 is formed.
In summary, in the manufacturing process of the FinFET device, in order to avoid the consumption of Fin in the FCVD and the subsequent annealing processes, a silicon buffer layer is formed on the Fin before the FCVD process after the Fin formation to neutralize the consumption of Fin in the FCVD and the subsequent annealing processes, thereby ensuring that the shape and size of the Fin are not affected. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (9)

1. A method for improving Fin size of a Fin transistor, the method comprising:
providing a first semiconductor structure comprising a plurality of Fins, wherein a first hard mask layer and a second hard mask layer are formed on the tops of the Fins; a first thin oxide layer is formed on the side wall of the Fin and the bottom of the first semiconductor structure between the Fin and the Fin;
step two, cutting off part of Fin in the multiple Fin together with the first hard mask layer, the second hard mask layer and the thin oxide layer to form a second semiconductor structure;
step three, forming a silicon buffer layer on the second semiconductor structure;
fourthly, covering a silicon oxide layer on the second semiconductor structure with the silicon buffer layer by adopting a fluid chemical vapor deposition method;
and fifthly, annealing the second semiconductor structure.
2. The method of claim 1, wherein the Fin size of the Fin transistor is: in the first step, the first hard mask layer is formed on the top of the Fin, and the second hard mask layer is formed on the first hard mask layer.
3. The method of claim 2, wherein the Fin size of the Fin transistor is: in the first step, the first hard mask layer is silicon oxide, and the second hard mask layer is silicon nitride.
4. The method of claim 1, wherein the Fin size of the Fin transistor is: in the third step, the reaction temperature for forming the silicon buffer layer on the second semiconductor structure is 300-400 ℃.
5. The method of claim 1, wherein the Fin size of the Fin transistor is: in the third step, disilane is used as the source gas for forming the silicon buffer layer on the second semiconductor structure.
6. The method of claim 1, wherein the Fin size of the Fin transistor is: and step three, the thickness of the silicon buffer layer formed on the second semiconductor structure is 1-3 nm.
7. The method of claim 1, wherein the Fin size of the Fin transistor is: and forming a second thin oxide layer on the silicon buffer layer of the second semiconductor structure before performing the fluid chemical vapor deposition method in the fourth step.
8. The method of claim 1, wherein the Fin size of the Fin transistor is: and sixthly, removing the first hard mask layer and the second hard mask layer on the top of the Fin.
9. The method of claim 8, wherein the Fin size of the Fin transistor is: and seventhly, etching back the silicon oxide layer.
CN202011154128.5A 2020-10-26 2020-10-26 Method for improving Fin size of Fin type transistor Pending CN112271161A (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104979266A (en) * 2014-04-02 2015-10-14 中芯国际集成电路制造(上海)有限公司 Method for forming shallow trench isolation structure
CN107369643A (en) * 2016-05-11 2017-11-21 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
US9984933B1 (en) * 2017-10-03 2018-05-29 Globalfoundries Inc. Silicon liner for STI CMP stop in FinFET
US10276687B1 (en) * 2017-12-20 2019-04-30 International Business Machines Corporation Formation of self-aligned bottom spacer for vertical transistors
CN111564413A (en) * 2020-03-03 2020-08-21 上海华力集成电路制造有限公司 Fin structure manufacturing method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104979266A (en) * 2014-04-02 2015-10-14 中芯国际集成电路制造(上海)有限公司 Method for forming shallow trench isolation structure
CN107369643A (en) * 2016-05-11 2017-11-21 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
US9984933B1 (en) * 2017-10-03 2018-05-29 Globalfoundries Inc. Silicon liner for STI CMP stop in FinFET
US10276687B1 (en) * 2017-12-20 2019-04-30 International Business Machines Corporation Formation of self-aligned bottom spacer for vertical transistors
CN111564413A (en) * 2020-03-03 2020-08-21 上海华力集成电路制造有限公司 Fin structure manufacturing method

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