CN113506732A - Method for reducing cut-off effect of pseudo gate of FinFET (Fin field effect transistor) device - Google Patents
Method for reducing cut-off effect of pseudo gate of FinFET (Fin field effect transistor) device Download PDFInfo
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- CN113506732A CN113506732A CN202110685113.XA CN202110685113A CN113506732A CN 113506732 A CN113506732 A CN 113506732A CN 202110685113 A CN202110685113 A CN 202110685113A CN 113506732 A CN113506732 A CN 113506732A
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- dielectric layer
- interlayer dielectric
- hard mask
- effect
- polysilicon
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- 238000000034 method Methods 0.000 title claims abstract description 40
- 230000000694 effects Effects 0.000 title claims abstract description 24
- 230000005669 field effect Effects 0.000 title description 2
- 239000010410 layer Substances 0.000 claims abstract description 65
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 56
- 239000011229 interlayer Substances 0.000 claims abstract description 45
- 229920005591 polysilicon Polymers 0.000 claims abstract description 42
- 238000000137 annealing Methods 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 26
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 11
- 238000000151 deposition Methods 0.000 claims abstract description 9
- 239000002184 metal Substances 0.000 claims abstract description 8
- 239000007789 gas Substances 0.000 claims abstract description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims description 2
- 229910001873 dinitrogen Inorganic materials 0.000 abstract description 6
- 238000005498 polishing Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 6
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Abstract
The invention provides a method for reducing the pseudo gate cutting effect of a FinFET device, which comprises the steps of forming a plurality of polysilicon structures and hard mask structures which are arranged at intervals on a substrate; forming a side wall attached to the side walls of the polycrystalline silicon structure and the hard mask structure; forming an epitaxial structure on the substrate between the polysilicon structures; depositing an interlayer dielectric layer; carrying out first annealing treatment; grinding the interlayer dielectric layer until the top of the hard mask structure is exposed; carrying out secondary annealing treatment on the interlayer dielectric layer by adopting the annealing temperature of 500-700 ℃ and the annealing gas of nitrogen to release the tension of the interlayer dielectric layer; grinding the interlayer dielectric layer until the top of the polysilicon structure is exposed; and removing the polysilicon structure to form the HK metal gate. According to the invention, after the interlayer dielectric layer is ground, the dry nitrogen gas at 500-700 ℃ is adopted for annealing, and the dry nitrogen gas is used for releasing tensile stress generated in the annealing process in the FCVD process, so that the cutting-off effect can be reduced, and the change of the device at different positions is weakened.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for reducing the cutting-off effect of a pseudo gate of a FinFET device.
Background
The gate cutting effect can cause the same device to generate larger device change at different positions, and the main reason is that the tensile stress generated by the interlayer dielectric layer formed by the FCVD can be transferred to the metal gate in the channel, so if the gate cutting effect is to be reduced, the stress generated by the FCVD needs to be smaller.
Therefore, a new method is needed to solve the above problems.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention is directed to a method for reducing the dummy gate cut effect of a FinFET device, which is used to solve the problem of reducing the device performance due to the tensile stress transferred to the metal gate when forming the interlayer dielectric layer by FCVD in the prior art.
To achieve the above and other related objects, the present invention provides a method for reducing the effect of dummy gate cut off of a FinFET device, the method comprising at least:
providing a substrate, and forming a plurality of polysilicon structures arranged at intervals and hard mask structures positioned on the polysilicon structures on the substrate;
secondly, forming a side wall attached to the side walls of the polycrystalline silicon structure and the hard mask structure;
step three, forming an epitaxial structure on the substrate between the polysilicon structures which are mutually spaced;
depositing an interlayer dielectric layer; the interlayer dielectric layer covers the substrate, the polysilicon structure and the hard mask structure;
fifthly, carrying out primary annealing treatment on the interlayer dielectric layer;
step six, grinding the interlayer dielectric layer until the top of the hard mask structure is exposed;
seventhly, carrying out secondary annealing treatment on the interlayer dielectric layer by adopting the annealing temperature of 500-700 ℃ and the annealing gas of nitrogen to release the tension of the interlayer dielectric layer;
step eight, grinding the interlayer dielectric layer until the top of the polycrystalline silicon structure is exposed;
and ninthly, removing the polysilicon structure to form a groove, and forming the HK metal gate in the groove.
Preferably, in the first step, a polysilicon layer is formed on the substrate, a hard mask layer is formed on the polysilicon layer, and then the hard mask layer and the polysilicon layer are etched to form a plurality of polysilicon structures arranged at intervals and the hard mask structure located on the polysilicon structures.
Preferably, a dielectric layer is deposited on the substrate in the second step, and then the dielectric layer is etched to form a side wall attached to the side walls of the polysilicon structure and the hard mask structure.
Preferably, the epitaxial structure in step three comprises a SiP epitaxial structure and a SiGe epitaxial structure.
Preferably, the deposition of the interlayer dielectric layer in the fourth step adopts an FCVD method.
Preferably, the method for polishing the interlayer dielectric layer in the sixth step is a chemical mechanical polishing method.
Preferably, the first annealing treatment in the fifth step is a wet annealing treatment.
Preferably, the temperature of the second annealing in the seventh step is 650 ℃.
As described above, the method for reducing the dummy gate cut effect of the FinFET device of the present invention has the following beneficial effects: according to the invention, after the interlayer dielectric layer is ground, the dry nitrogen gas at 500-700 ℃ is adopted for annealing, and the dry nitrogen gas is used for releasing tensile stress generated in the annealing process in the FCVD process, so that the cutting-off effect can be reduced, and the change of the device at different positions is weakened.
Drawings
FIG. 1 illustrates a flow chart of a method of reducing the effect of dummy gate cut in a FinFET device in accordance with the present invention;
FIG. 2 is a schematic view of a plurality of polysilicon structures formed on a substrate in accordance with the present invention;
FIG. 3 is a schematic structural diagram of the polysilicon structure and the hard mask structure after forming sidewalls thereon;
FIG. 4 is a schematic diagram of the structure of the present invention after the epitaxial structure is formed;
FIG. 5 is a schematic diagram of a structure of the present invention in which an interlayer dielectric is formed and polished to expose a hard mask structure;
FIG. 6 is a schematic view of the present invention polishing the interlevel dielectric layer to expose the top of the polysilicon structure.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 6. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
The present invention provides a method for reducing the pseudo-gate-off effect of a FinFET device, as shown in fig. 1, where fig. 1 is a flowchart illustrating a method for reducing the pseudo-gate-off effect of a FinFET device in the present invention, the method at least includes:
providing a substrate, and forming a plurality of polysilicon structures arranged at intervals and hard mask structures positioned on the polysilicon structures on the substrate; referring to fig. 2, fig. 2 is a schematic diagram illustrating a plurality of polysilicon structures formed on a substrate according to the present invention. Providing a substrate 01 in the first step, and forming a plurality of polysilicon structures 02 arranged at intervals and hard mask structures 03 positioned on the polysilicon structures 02 on the substrate 01;
further, in the first step of this embodiment, a polysilicon layer is formed on the substrate 01, a hard mask layer is formed on the polysilicon layer, and then the hard mask layer and the polysilicon layer are etched to form a plurality of polysilicon structures 02 arranged at intervals and a plurality of hard mask structures 03 located on the polysilicon structures. In this embodiment, the hard mask structure is silicon nitride.
Secondly, forming a side wall attached to the side walls of the polycrystalline silicon structure and the hard mask structure; as shown in fig. 3, fig. 3 is a schematic structural diagram of the polysilicon structure and the hard mask structure after forming the sidewalls. In the second step, a sidewall 04 attached to the sidewalls of the polysilicon structure 02 and the hard mask structure 03 is formed.
Further, the method for forming the sidewall in the second step of this embodiment includes: depositing a dielectric layer on the substrate 01, and then etching the dielectric layer to form the side wall 04 attached to the side walls of the polysilicon structure 02 and the hard mask structure 03.
Step three, forming an epitaxial structure on the substrate between the polysilicon structures which are mutually spaced; as shown in fig. 4, fig. 4 is a schematic structural diagram of the epitaxial structure formed in the present invention. In the third step, the epitaxial structure 05 is formed on the substrate 01 between the polysilicon structures 02 spaced apart from each other.
Further, the epitaxial structure in step three of this embodiment includes a SiP epitaxial structure and a SiGe epitaxial structure. For example, the two epitaxial structures located on the left side in fig. 4 are SiP epitaxial structures, and the two epitaxial structures located on the right side in fig. 4 are SiGe epitaxial structures.
Depositing an interlayer dielectric layer; the interlayer dielectric layer covers the substrate, the polysilicon structure and the hard mask structure; and the interlayer dielectric layer deposited in the fourth step completely covers the substrate, the polycrystalline silicon structure and the hard mask structure.
Further, in the fourth step of this embodiment, an FCVD method is used for depositing the interlayer dielectric layer.
Fifthly, carrying out primary annealing treatment on the interlayer dielectric layer;
further, the first annealing treatment in step five of this embodiment is a wet annealing treatment.
Step six, grinding the interlayer dielectric layer until the top of the hard mask structure is exposed; as shown in fig. 5, fig. 5 is a schematic structural view illustrating the formation of an interlayer dielectric and polishing until the hard mask structure is exposed. In the sixth step, the interlayer dielectric layer 06 is ground until the top of the hard mask structure 03 is exposed.
Further, in the present invention, a method for polishing the interlayer dielectric layer 06 in the sixth step of this embodiment is a Chemical Mechanical Polishing (CMP) method.
Seventhly, carrying out secondary annealing treatment on the interlayer dielectric layer by adopting the annealing temperature of 500-700 ℃ and the annealing gas of nitrogen to release the tension of the interlayer dielectric layer; in the seventh step, annealing the FCVD interlayer dielectric layer 06 in a nitrogen atmosphere at a temperature of 500-700 ℃, and releasing the tensile stress in the FCVD interlayer dielectric layer by the second annealing. Further, the temperature of the second annealing in step seven of this embodiment is 650 ℃.
Step eight, grinding the interlayer dielectric layer until the top of the polycrystalline silicon structure is exposed; referring to fig. 6, fig. 6 is a schematic view illustrating a structure of polishing an interlayer dielectric layer until the top of a polysilicon structure is exposed according to the present invention. In this embodiment, the method for polishing the interlayer dielectric layer in the eighth step is a chemical mechanical polishing method.
And ninthly, removing the polysilicon structure to form a groove, and forming the HK metal gate in the groove. As shown in fig. 6, in the ninth step, the polysilicon structure 02 is removed, a groove with the sidewall 02 as a sidewall is left, and then HK metal is filled in the groove to form the HK metal gate.
In summary, after the interlayer dielectric layer is ground, the dry nitrogen gas with the temperature of 500-700 ℃ is adopted for annealing, and the dry nitrogen gas is used for releasing tensile stress generated in the annealing process in the FCVD process, so that the cutting effect can be reduced, and the change of the device at different positions is weakened. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (8)
1. A method of reducing a dummy gate turn-off effect in a FinFET device, the method comprising:
providing a substrate, and forming a plurality of polysilicon structures arranged at intervals and hard mask structures positioned on the polysilicon structures on the substrate;
secondly, forming a side wall attached to the side walls of the polycrystalline silicon structure and the hard mask structure;
step three, forming an epitaxial structure on the substrate between the polysilicon structures which are mutually spaced;
depositing an interlayer dielectric layer; the interlayer dielectric layer covers the substrate, the polysilicon structure and the hard mask structure;
fifthly, carrying out primary annealing treatment on the interlayer dielectric layer;
step six, grinding the interlayer dielectric layer until the top of the hard mask structure is exposed;
seventhly, carrying out secondary annealing treatment on the interlayer dielectric layer by adopting the annealing temperature of 500-700 ℃ and the annealing gas of nitrogen to release the tension of the interlayer dielectric layer;
step eight, grinding the interlayer dielectric layer until the top of the polycrystalline silicon structure is exposed;
and ninthly, removing the polysilicon structure to form a groove, and forming the HK metal gate in the groove.
2. The method of reducing the effect of dummy gate cut off of a FinFET device of claim 1, wherein: in the first step, a polycrystalline silicon layer is formed on the substrate, a hard mask layer is formed on the polycrystalline silicon layer, and then the hard mask layer and the polycrystalline silicon layer are etched to form a plurality of polycrystalline silicon structures arranged at intervals and hard mask structures positioned on the polycrystalline silicon structures.
3. The method of reducing the effect of dummy gate cut off of a FinFET device of claim 1, wherein: and depositing a dielectric layer on the substrate in the second step, and then etching the dielectric layer to form a side wall attached to the side walls of the polycrystalline silicon structure and the hard mask structure.
4. The method of reducing the effect of dummy gate cut off of a FinFET device of claim 1, wherein: the epitaxial structure in the third step comprises a SiP epitaxial structure and a SiGe epitaxial structure.
5. The method of reducing the effect of dummy gate cut off of a FinFET device of claim 1, wherein: and the deposition of the interlayer dielectric layer in the fourth step adopts an FCVD method.
6. The method of reducing the effect of dummy gate cut off of a FinFET device of claim 1, wherein: and sixthly, the method for grinding the interlayer dielectric layer is a chemical mechanical grinding method.
7. The method of reducing the effect of dummy gate cut off of a FinFET device of claim 5, wherein: and the first annealing treatment in the fifth step is wet annealing treatment.
8. The method of reducing the effect of dummy gate cut off of a FinFET device of claim 1, wherein: the temperature of the second annealing in the seventh step is 650 ℃.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110685113.XA CN113506732A (en) | 2021-06-21 | 2021-06-21 | Method for reducing cut-off effect of pseudo gate of FinFET (Fin field effect transistor) device |
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| CN202110685113.XA CN113506732A (en) | 2021-06-21 | 2021-06-21 | Method for reducing cut-off effect of pseudo gate of FinFET (Fin field effect transistor) device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113782436A (en) * | 2021-08-12 | 2021-12-10 | 上海华力集成电路制造有限公司 | Method for reducing pseudo gate cut-off effect of fin type transistor |
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- 2021-06-21 CN CN202110685113.XA patent/CN113506732A/en active Pending
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