CN109148373A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN109148373A CN109148373A CN201710461380.2A CN201710461380A CN109148373A CN 109148373 A CN109148373 A CN 109148373A CN 201710461380 A CN201710461380 A CN 201710461380A CN 109148373 A CN109148373 A CN 109148373A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
A kind of semiconductor structure and forming method thereof, the forming method includes: to form substrate；Forerunner's dielectric layer is formed on the substrate；Fine and close injection processing is carried out to forerunner's dielectric layer, to form interlayer dielectric layer.The densification injection processing can drive the H in forerunner's dielectric layer to release, to be conducive to the raising of the interlayer dielectric layer consistency, can effectively improve the performance of the interlayer dielectric layer；And the way for driving H to release is handled by fine and close injection, technological temperature can be effectively controlled, to be conducive to the control of heat budget, can be effectively reduced influence of the inter-level dielectric layer formation process to other semiconductor structures；So technical solution of the present invention can improve the consistency of the interlayer dielectric layer under the premise of controlling heat budget, it can be realized consistency raising and taken into account with what heat budget reduced, be conducive to the electric property for improving formed semiconductor structure.
Description
Technical field
The present invention relates to field of semiconductor manufacture, in particular to a kind of semiconductor structure and forming method thereof.
Background technique
With the rapid development of semiconductor processing technology, the continuous development of ic manufacturing technology, people are to integrated electricity
The requirement of the integrated level and performance on road becomes higher and higher.Semiconductor devices is towards higher component density and higher collection
The direction of Cheng Du is developed.In order to improve integrated level, cost is reduced, the critical size of component constantly becomes smaller, IC interior
Density of components and current densities it is increasing, this development is so that spacing between adjacent component, between adjacent circuit
It is smaller and smaller.
In semiconductor processing technology, electricity is usually realized by interlayer dielectric layer between adjacent component, between adjacent circuit
Sexual isolation.Between adjacent component, between adjacent circuit spacing reduction, improve the filling difficulty of interlayer dielectric layer, institute's shape
At being easy to appear cavity in interlayer dielectric layer.
In order to improve filling capacity, the prior art introduces fluid chemistry vapor deposition in the forming process of interlayer dielectric layer
Technique (Flowable Chemical Vapor Deposition, FCVD).But after introducing fluid chemistry gas-phase deposition,
It is formed by semiconductor structure often and will appear the bad problem of electric property.
Summary of the invention
Problems solved by the invention is to provide a kind of semiconductor structure and forming method thereof, to improve the electricity of semiconductor structure
Learn performance.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, comprising:
Form substrate；Forerunner's dielectric layer is formed on the substrate；Fine and close injection processing is carried out to forerunner's dielectric layer,
To form interlayer dielectric layer.
Optionally, the injection ion of the fine and close injection processing is He or Si.
Optionally, the fine and close injection processing is carried out by way of heat injection.
Optionally, the technological temperature of the fine and close injection processing is within the scope of 450 DEG C to 500 DEG C.
Optionally, the step of forming substrate includes: offer substrate；Gate structure is formed over the substrate；The forerunner
Dielectric layer covers the gate structure.
Optionally, the injection depth of the fine and close injection processing is less than or equal to forerunner's medium on the gate structure
The thickness of layer.
Optionally, the injection depth of the fine and close injection processing existsIt arrivesIn range.
Optionally, the technological parameter of the fine and close injection processing includes: technological temperature within the scope of 300 DEG C to 600 DEG C；Note
Enter energy in 10KeV to 200KeV range；Implantation dosage is in 2.0E14atom/cm2To 5.0E16atom/cm2In range.
Optionally, forerunner's dielectric layer is formed in such a way that fluid chemistry is vapor-deposited.
Optionally, the step of forming forerunner's dielectric layer includes: to form fluidized bed on the substrate；To the flowing
Layer carries out curing process.
Optionally, the curing process is carried out by way of the first annealing, first annealing is steam
Annealing.
Optionally, the annealing temperature of first annealing is within the scope of 450 DEG C to 600 DEG C, and annealing time is in 10min
Into 200min.
Optionally, the forming method further include: after carrying out fine and close injection processing, carry out the second annealing.
Optionally, the annealing temperature of second annealing is within the scope of 550 DEG C to 700 DEG C, and annealing time is in 10min
Into 150min.
Optionally, second annealing is carried out under N2 atmosphere.
Correspondingly, the present invention also provides a kind of semiconductor structures, comprising:
Substrate；Interlayer dielectric layer in the substrate, the densified injection processing of interlayer dielectric layer.
Optionally, the injection ion of the fine and close injection processing is He or Si.
Optionally, the injection depth of the fine and close injection processing existsIt arrivesIn range.
Optionally, the technological parameter of the fine and close injection processing includes: technological temperature within the scope of 300 DEG C to 600 DEG C；Note
Enter energy in 10KeV to 200KeV range；Implantation dosage is in 2.0E14atom/cm2To 5.0E16atom/cm2In range.
Optionally, the substrate includes substrate and the gate structure on the substrate；The interlayer dielectric layer covering
The gate structure；The injection depth of the fine and close injection processing is less than or equal to the thickness of forerunner's dielectric layer on the gate structure
Degree.
Compared with prior art, technical solution of the present invention has the advantage that
By carrying out fine and close injection processing to forerunner's dielectric layer, the densification injection processing can drive the forerunner
H in dielectric layer releases, to be conducive to the raising of the interlayer dielectric layer consistency, can effectively improve the inter-level dielectric
The performance of layer；And the way for driving H to release is handled by fine and close injection, technological temperature can be effectively controlled, to be conducive to
The control of heat budget can be effectively reduced influence of the inter-level dielectric layer formation process to other semiconductor structures；So this
Inventive technique scheme can improve the consistency of the interlayer dielectric layer, can be realized densification under the premise of controlling heat budget
Degree improves and what heat budget reduced takes into account, and is conducive to the electric property for improving formed semiconductor structure.
In optinal plan of the present invention, He or Si is injected into forerunner's dielectric layer by way of heat injection；Heat injection
He or Si the H in forerunner's dielectric layer can be driven to release, the consistency of the interlayer dielectric layer can be effectively improved；And
And the technological temperature of the fine and close injection processing controls within the scope of 450 DEG C to 500 DEG C, and the technological temperature is controlled reasonable
In range, the heat budget to be formed during the semiconductor structure can be effectively reduced；So technical solution of the present invention can be simultaneous
Low heat budget and high-compactness requirement are cared for, the electric property of formed semiconductor structure can be effectively improved.
In optinal plan of the present invention, the forming method further include: after carrying out fine and close injection processing, carry out second and move back
Fire processing；Second annealing is for releasing remaining H, to realize the further of the interlayer dielectric layer consistency
It improves, the quality of the interlayer dielectric layer can be effectively improved；And the annealing temperature of second annealing is controlled 550
DEG C within the scope of 700 DEG C, annealing time is controlled in 10min to 150min range, therefore described second make annealing treatment can be
Under the premise of controlling heat budget, the consistency of the interlayer dielectric layer is effectively improved, is advantageously implemented low heat budget and high-densit
Taking into account for degree, is conducive to the electric property for improving formed semiconductor structure.
In optinal plan of the present invention, the substrate includes substrate and the gate structure on the substrate, the forerunner
Dielectric layer covers the gate structure；So the injection depth of the fine and close injection processing is less than or equal on the gate structure
The thickness of forerunner's dielectric layer.The injection depth of fine and close injection processing shown in control, can effectively control the fine and close injection
The injection phase of processing injection ion has so as to reduce influence of the fine and close injection processing to structure in the substrate
Conducive to the influence for improving formed semiconductor structure performance.
Detailed description of the invention
Fig. 1 to Fig. 3 is the schematic diagram of the section structure corresponding to each step during a kind of semiconductor structure is formed；
Fig. 4 to Figure 11 is schematic diagram corresponding to each step of one embodiment of method for forming semiconductor structure of the present invention.
Specific embodiment
It can be seen from background technology that be formed by semiconductor structure and often go out after introducing fluid chemistry gas-phase deposition
The bad problem of existing electric property.The original of the bad problem of its electric property is analyzed now in conjunction with a kind of forming process of semiconductor structure
Cause:
Referring to figs. 1 to Fig. 3, cross-section structure corresponding to each step during a kind of semiconductor structure is formed is shown to show
It is intended to.
With reference to Fig. 1, substrate 10 is formed.
The step of forming substrate 10 includes: to provide substrate 11, has fin 12 on the substrate 11；On the fin 12
Form gate structure 14；Source and drain doping area 15 is formed in the fin 12 of 14 two sides of gate structure.
With reference to Fig. 2, fluidized bed is formed in the substrate 10, and curing process is carried out to the fluidized bed and forms forerunner Jie
Matter layer 21；With reference to Fig. 3, annealing 23 is carried out to forerunner's dielectric layer 21, to improve the densification of forerunner's dielectric layer 21
Degree forms interlayer dielectric layer 22.
In fluid chemistry gas-phase deposition, although forerunner's dielectric layer 21 be the fluidized bed it is cured processing and
It is formed, but the consistency of forerunner's dielectric layer 21 is poor, it is difficult to the requirement for meeting subsequent technique, especially subsequent
In flatening process, forerunner's dielectric layer 21 of low density is easy to appear defect, to influence the performance of the semiconductor structure
And yield.
Since the fluidized bed is formed by polymer, the polymer includes the elements such as Si, O, N and H.To described
It is exactly to release N in the polymer and H, and Si and O bonding is made to form silica that fluidized bed, which carries out curing process,.But it is solid
The effect that change processing releases N and H is limited, therefore after curing process, forerunner's dielectric layer 21 is needed to carry out at annealing
Reason 23, releases N and H further, especially releases H, to improve the consistency of dielectric layer 22 between the formed layer.
In order to improve the effect that H releases, the annealing temperature that forerunner's dielectric layer 22 carries out annealing 23 is higher, may
800 DEG C or more (specifically, generally can be within the scope of 800 DEG C to 900 DEG C) can be up to.Excessively high annealing temperature can make described partly to lead
Heat budget (thermal budget) during body is formed is excessively high, may cause shadow to the performance of formed semiconductor structure
It rings.
For example, being formed with lightly doped district (not shown) and source and drain doping area 15 in the substrate 11, excessively high heat is pre-
Calculation can be such that the Doped ions in the lightly doped district or the source and drain doping area 15 excessively spread, to cause formed semiconductor
The degeneration of structure electric property.
For another example having stressor layers (not indicating in figure) in the substrate 11, excessively high heat budget may make described answer
There is the problem of stress release in power layer, so that the effect that the stressor layers apply stress to channel is influenced, to cause to be formed
The degeneration of semiconductor structure electric property.
To solve the technical problem, the present invention provides a kind of forming method of semiconductor structure, at fine and close injection
Reason drives the H in forerunner's dielectric layer to release, and can be realized consistency raising and takes into account with what heat budget reduced, is conducive to improve
The electric property of formed semiconductor structure.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
With reference to Fig. 4 to Figure 11, show corresponding to each step of one embodiment of method for forming semiconductor structure of the present invention
Schematic diagram.
The method for forming semiconductor structure passes through to the forerunner's dielectric layer formed on the substrate 100 (as shown in Figure 4)
210 progress (as shown in Figure 6), 220 (as shown in Figure 7) of fine and close injection processing, to realize high-compactness interlayer dielectric layer 230 (such as
Shown in Fig. 9) formation.
The fine and close injection processing 220 can drive the H in 210 in forerunner's dielectric layer to release, to be conducive to institute
The raising of 230 consistency of interlayer dielectric layer is stated, and can effectively control technological temperature, is conducive to the control of heat budget, thus
Reduce influence of 230 forming process of interlayer dielectric layer to other semiconductor structures.
With reference to Fig. 4, substrate 100 is formed.
The substrate 100 is used to provide technological operation platform for subsequent step.
In the present embodiment, the semiconductor structure is used to form transistor, so the step of forming substrate 100 packet
It includes: substrate 110 is provided；Gate structure 140 is formed on the substrate 110.
Specifically, the semiconductor structure is used to form fin formula field effect transistor, so also having on the substrate 110
Fin 120 and the separation layer 130 being filled between adjacent fin 120；The gate structure 140 across the fin 120 and
Cover the surface of fin 120 atop part and partial sidewall.
In addition, in the present embodiment, the forming method further include: formed after the gate structure 140, in the grid
Source and drain doping area 150 is formed in the fin 120 of 140 two sides of structure.
The substrate 110 provides technological operation platform to be subsequently formed semiconductor structure；The ditch of formed semiconductor structure
Road is located in the fin 120.
In the present embodiment, 110 material of substrate is monocrystalline silicon.In other embodiments of the invention, the material of the substrate
It is also selected from the other materials such as polysilicon, amorphous silicon or germanium, germanium, SiGe, silicon carbide, GaAs or gallium indium.This hair
In other bright embodiments, the substrate can also be the silicon substrate on insulator, germanium substrate or glass substrate on insulator
Etc. other kinds of substrate.The material of the substrate can be the material for being suitable for process requirement or being easily integrated.
In the present embodiment, it is all monocrystalline silicon that the material of the fin 120 is identical as the material of the substrate 110.The present invention
In other embodiments, the material of the fin can also be different from the material of the substrate.The material of the fin may be
The other materials such as germanium, germanium, SiGe, silicon carbide, GaAs or gallium indium.
In the present embodiment, the substrate 110 and the fin 120 can be formed simultaneously, and form the substrate 110 and described
The step of fin 120 includes: offer initial substrate；Patterned fin mask layer is formed (in figure in the initial substrate surface
It is not shown)；Using the fin mask layer as exposure mask, the initial substrate is etched, remove the part initial substrate, described in formation
Substrate 110 and the fin 120 for being raised in 110 surface of substrate.
The separation layer 130 covers the partial sidewall of the fin 120, and is lower than the fin at the top of the separation layer 130
120 top of portion.Isolation structure of the separation layer 130 as semiconductor structure, can be in adjacent devices and adjacent fin 120
Between play the role of electric isolation.The separation layer 130 is located on the substrate 110 of the fin 120 exposing, and described
The height of separation layer 130 is lower than the height of the fin 120.
In the present embodiment, the material of the separation layer 130 is silica.In other embodiments of the invention, the isolation junction
The material of structure can also be other insulating materials such as silicon nitride or silicon oxynitride.
In the present embodiment, the step of forming separation layer 130 includes: the substrate to form the fin 120 and expose
Spacer material layer is formed on 110, the spacer material layer covers the top of the fin 120；Grinding removes the fin 120 and pushes up
Spacer material layer in portion；The segment thickness that remaining spacer material layer is removed by way of returning and carving, exposes the fin 120
Top and partial sidewall form the separation layer 130；Remove the fin mask layer.
In the present embodiment, formed semiconductor structure has high-K metal gate structure, so the gate structure 140 is
Pseudo- grid structure, for taking up space position for the formation of subsequent metal gate structure.It is described but in other embodiments of the invention
Gate structure is also possible to the gate structure of formed semiconductor structure, for controlling the conducting of formed semiconductor structure channel
And truncation.
In the present embodiment, the gate structure 140 is laminated construction, and the gate structure 140 includes pseudo- oxide layer (in figure
Do not indicate) and pseudo- grid layer (not indicated in figure) in the pseudo- oxide layer.
In the present embodiment, the material of the puppet oxide layer is silica.In other embodiments of the invention, the puppet oxide layer
Material can also be silicon oxynitride.
In the present embodiment, the material of the puppet grid layer is polysilicon.In other embodiments of the invention, the material of the puppet grid layer
Material can also be other materials such as silica, silicon nitride, silicon oxynitride, silicon carbide, carbonitride of silicium, carbon silicon oxynitride or amorphous carbon
Material.
In addition, dummy gate structure can also be single layer structure in other embodiments of the invention, correspondingly, the puppet grid
Structure includes pseudo- grid layer.
Specifically, the step of forming gate structure 140 includes: the fin 120 exposed in the separation layer 130
Surface forms layer of oxidized material；Pseudo- gate material layer is formed on the layer of oxidized material；It is formed on the pseudo- gate material layer surface
Gate mask layer (does not indicate) in figure；Using the gate mask layer as exposure mask, the pseudo- gate material layer is etched to exposing the oxygen
Change material layer, forms the pseudo- grid layer being located on the layer of oxidized material, the puppet grid layer is across the fin 120 and is located at described
On 120 atop part of fin and partial sidewall；The layer of oxidized material that the pseudo- grid layer is exposed is removed, the fin 120 is exposed
Surface, the remaining layer of oxidized material covered by the pseudo- gate material layer as pseudo- oxide layer, so the puppet oxide layer across
The surface of the fin 120 and covering fin 120 atop part and partial sidewall.
It should be noted that retaining the grid being located on 140 top of gate structure after forming the gate structure 140
Pole mask layer.The material of the gate mask layer is silicon nitride, and the gate mask layer is during subsequent technique for institute
It states and plays a protective role at the top of gate structure 140.In other embodiments, the material of the gate mask layer can also be nitrogen oxygen
SiClx, silicon carbide or boron nitride.
It should also be noted that, after forming the gate structure 140, the forming method further include: in gate structure 140
Side wall (not indicating in figure) is formed on side wall, to protect the gate structure 140 and define subsequent formed source and drain doping area
Position.The material of the side wall can be silica, silicon nitride, silicon carbide, carbonitride of silicium, carbon silicon oxynitride, silicon oxynitride, nitrogen
Change boron or boron carbonitrides, the side wall can be single layer structure or laminated construction.In the present embodiment, the side wall is single layer knot
Structure, the material of the side wall are silicon nitride.
The source and drain doping area 150 is used to form source region and the drain region of the semiconductor structure.
In the present embodiment, the step of forming source and drain doping area 150 includes: the fin in 140 two sides of gate structure
Stressor layers are formed in portion 120；The stressor layers are doped to form the source and drain doping area 150.
In the present embodiment, the semiconductor structure is used to form cmos device, therefore the substrate 100 includes being used to form
The PMOS area 100P of the P-type device and NMOS area 100N for being used to form N-type device.So the PMOS area 100P base
Formed source and drain doping area 150 is p-type source and drain doping area in bottom 100, i.e., the described stress layer material is germanium silicon or silicon, the stress
Doped ions are P-type ion, such as B, Ga or In in layer；Source and drain doping is formed by the NMOS area 100N substrate 100
Area 150 is N-type source and drain doping area, i.e., the material of the described stressor layers is carbon silicon or silicon, and the Doped ions in the stressor layers are N-type
Ion, such as: P, As or Sb.
But in other embodiments of the present invention, the substrate can also only include the area PMOS for being used to form P-type device
Domain, alternatively, only including the NMOS area for being used to form N-type device.
It should be noted that in the present embodiment, the forming method further include: formed after the gate structure 140, shape
Before the side wall, lightly doped drain injection (Lightly Doped is carried out to the fin of 140 two sides of gate structure
Drain, LDD), to improve the performance of formed semiconductor structure.
With reference to Fig. 5 to Fig. 6, forerunner's dielectric layer 210 is formed in the substrate 100.
Forerunner's dielectric layer 210 forms interlayer dielectric layer after processing.
Specifically, forerunner's dielectric layer 210 covers the gate structure 140 in the present embodiment, i.e., described forerunner's medium
The top of layer 210 is higher than the top of the gate structure 140.
In the present embodiment, forerunner's dielectric layer 210 is formed in such a way that fluid chemistry is vapor-deposited.Due to fluidisation
Learning vapor deposition is by the way that fluid or semifluid are solidified to form forerunner's dielectric layer 210, therefore the fluid chemistry gas
Mutually deposition has preferable gap filling ability, generation that can be empty effectively in formed forerunner's dielectric layer 210, to be conducive to mention
The quality of dielectric layer between high the formed layer.
Specifically, the step of forming forerunner's dielectric layer 210 includes: as shown in figure 5, being formed in the substrate 100
Fluidized bed 211；As shown in fig. 6, curing process is carried out to the fluidized bed 211, to form forerunner's dielectric layer 210.
Forerunner's dielectric layer 210 is used to form after the fluidized bed 211 is cured.The fluidized bed 211 has certain
Mobility, can flow to and be needed in the various structures filled under fluid or viscid state, and carry out from bottom to top
Filling, thus realize be sufficient filling with.
In the present embodiment, the material of the fluidized bed 211 is trimethyl silicane alkanamine (Trisilylamine, TSA).This hair
In bright other embodiments, the material of the fluidized bed can also be in fluid or viscid material for other, such as include poly- second silicon
The polysilanes materials such as penta silane of alkane and ring.Specifically, the step of forming fluidized bed 211 includes: the shape by way of spin coating
At the fluidized bed 211.
In the present embodiment, the fluidized bed 211 is used to form forerunner's dielectric layer 210, and forerunner's dielectric layer 210 covers
Cover the gate structure 140；So the fluidized bed 211 also covers the gate structure 140.
As shown in fig. 6, being formed after the fluidized bed 211, curing process is carried out.
In the present embodiment, the curing process, first annealing are carried out by way of the first annealing 212
212 make annealing treatment (Stream Anneal) for steam.During first annealing 212, the N in the fluidized bed 211
It can be released because of reacting with O；It will form chemical bond between Si and O, to make the fluidized bed 211 (as shown in Figure 5)
It loses flowability and realizes solidification, and then form forerunner's dielectric layer 210.
It should be noted that it is described first annealing 212 annealing temperature should not it is too high also should not be too low, annealing time
It is unsuitable it is too long also should not be too short.
If the annealing temperature of first annealing 212 is too high, if annealing time is too long, technique mistake will increase
Heat budget in journey, may cause institute at the problems such as may causing the excess diffusion or stressor layers stress release of Doped ions
Form the degeneration of semiconductor structure electric property；If the annealing temperature of first annealing 212 is too low, annealing time is such as
Fruit is too short, then is unfavorable for the generation reacted in the fluidized bed 211, is unfavorable for releasing for N and O, is unfavorable between Si and O chemical
The formation of key may will affect the solidification effect of the curing process.
Specifically, in the present embodiment, the annealing temperature of first annealing 212 within the scope of 450 DEG C to 600 DEG C,
Annealing time is in 10min to 200min range.
With reference to Fig. 7 to Fig. 9,220 (as shown in Figure 7) of fine and close injection processing are carried out to forerunner's medium 210, with forming layer
Between dielectric layer 230 (as shown in Figure 9).
The fine and close injection processing 220 can drive the H in forerunner's dielectric layer 210 to release, so as to improve
The consistency for stating forerunner's dielectric layer 210 advantageously forms the interlayer dielectric layer 230 of high-compactness；The interlayer dielectric layer 230 is used
Electric isolution between realization adjacent semiconductor constructs.
Specifically, the injection ion of the fine and close injection processing 220 is He or Si.The injection of He or Si ion can drive
Chemical bond rupture between Si and H and between O and H is conducive to forerunner's medium so as to effectively drive releasing for H
The raising of 210 consistency of layer；And the injection of He and Si, impurity will not be introduced in forerunner's dielectric layer 210 and influence institute
The electric isolution performance for stating interlayer dielectric layer 230 can reduce 220 pairs of formed semiconductor structure performances of the fine and close injection processing
Influence.
As shown in fig. 7, the substrate 100 includes substrate 110 and the institute on the substrate 120 in the present embodiment
State gate structure 140；The gate structure 140 is projected on the surface of the substrate 110；Therefore the fine and close injection processing 220
Injection depth d be less than or equal to the gate structure 140 on forerunner's dielectric layer 210 thickness h, to control the cause
The injection phase of close 220 injection ion of injection processing reduces the fine and close injection processing to the shadow of structure in the substrate 100
It rings, reduces the fine and close injection processing 220 as far as possible and inject ion into the gate structure 140, reduce the gate structure 140
The appearance of damage is conducive to the influence for improving formed semiconductor structure performance.
It should be noted that the injection depth of the fine and close injection processing 220 should not be too large also should not mistake in the present embodiment
It is small.
If the injection depth of the fine and close injection processing 220 is too big, it will increase the gate structure 140 and injected
Influence, injection ion may enter in the gate structure 140 to influence the performance of the gate structure 140, cause
Gate structure 140 is impaired, may cause the decline of formed semiconductor structure performance and the loss of yield；The fine and close injection
If the injection depth of processing 220 is too small, the injection ion of the fine and close injection processing 220 is too near to forerunner's dielectric layer
210 top is unfavorable for releasing for deep layer H, is unfavorable for reducing the concentration of remnants H in the interlayer dielectric layer 230, is unfavorable for institute
State the raising of 230 consistency of interlayer dielectric layer.
Specifically, the injection depth of the fine and close injection processing 220 existsIt arrivesIn range.
In the present embodiment, the fine and close injection processing 220 is carried out in such a way that heat injects (Hot Implant).Heat note
What the mode entered carried out that the fine and close injection processing 220 can effectively improve H releases effect, is conducive to the raising of consistency.
With reference to Fig. 8, the concentration and inter-level dielectric layer depth for remaining H between different process the formed layer in dielectric layer are shown
Relational graph.
Horizontal axis indicates the depth of the interlayer dielectric layer, i.e., the injection depth or annealing of the described fine and close injection processing in figure
In treatment process, the thickness of interlayer dielectric layer, unit nm；The longitudinal axis indicates the concentration that H is remained in the interlayer dielectric layer, unit
For at%.It should be noted that it is bottom, the logarithm of atomic percent shared by H that the residual H concentration that the longitudinal axis indicates, which is with 10,.
Figure line 810 remains the concentration of H between annealing way the formed layer in dielectric layer；Figure line 820 is carries out institute under room temperature
State the concentration for remaining H between 220 the formed layer of fine and close injection processing in dielectric layer；Figure line 830 is that hot injection mode carries out the cause
The concentration of H is remained between 220 the formed layer of close injection processing in dielectric layer.
As shown in figure 8, remaining H's in dielectric layer between annealing way the formed layer represented by figure line 810 in identical depth
Concentration is maximum, carries out remaining H's in dielectric layer between 220 the formed layer of the fine and close injection processing under room temperature represented by figure line 820
Concentration is taken second place, and the concentration of residual H differs smaller in dielectric layer between annealing way the formed layer；The note of heat represented by figure line 830
Enter mode remained in dielectric layer between 220 the formed layer of the fine and close injection processing H concentration it is minimum, and be less than by a relatively large margin
First two situation.
That is, forerunner's dielectric layer can be effectively improved by carrying out the fine and close injection processing by hot injection mode
H releases in 210, can be effectively reduced the concentration for remaining H between the formed layer in dielectric layer, is conducive to improve and is situated between the formed layer
The consistency of matter layer.
It should be noted that the technological temperature of the fine and close injection processing 220 should not it is too high also should not be too low.
If the technological temperature of the fine and close injection processing 220 is too high, the heat budget in technical process will increase, it may
The problems such as causing the excess diffusion or stressor layers stress release of Doped ions, it may cause formed semiconductor structure electricity
The degeneration of performance；If the technological temperature of the fine and close injection processing 220 is too low, it is unfavorable for driving releasing for H, is unfavorable for dropping
The concentration for remaining H between low the formed layer in dielectric layer is unfavorable for the consistency of dielectric layer between raising the formed layer.
In the present embodiment, the technological temperature of the fine and close injection processing 220 is within the scope of 450 DEG C to 500 DEG C.By by institute
The technological temperature control for stating fine and close injection processing 220 in the reasonable scope, can be effectively reduced to form the semiconductor structure mistake
Heat budget in journey；So technical solution of the present invention can take into account low heat budget and high-compactness requirement, institute can be effectively improved
Form the electric property of semiconductor structure.
In the present embodiment, the specific process parameter of the fine and close injection processing 220 includes: technological temperature at 300 DEG C to 600
Within the scope of DEG C；Implantation Energy is in 10KeV to 200KeV range；Implantation dosage is in 2.0E14atom/cm2To 5.0E16atom/
cm2In range.So Doped ions concentration exists in dielectric layer 230 between the formed layer after fine and close injection processing 200
1.0E19atom/cm3To 8.0E21atom/cm3In range.
With reference to Fig. 9, in the present embodiment, the forming method further include: carry out 220 (as shown in Figure 7) of fine and close injection processing
Later, the second annealing 231 is carried out.
Second annealing 231 can further drive H remaining in the interlayer dielectric layer 230 further to release
Out, so as to further increase the consistency of the interlayer dielectric layer 230, be conducive to 230 mass of interlayer dielectric layer
Further improve.
The annealing temperature of second annealing 231 should not it is too high also should not be too low, annealing time it is unsuitable it is too long not yet
It is preferably too short.
If the annealing temperature of second annealing 231 is too high, if annealing time is too long, technique mistake will increase
Heat budget in journey, may cause institute at the problems such as may causing the excess diffusion or stressor layers stress release of Doped ions
Form the degeneration of semiconductor structure electric property；If the annealing temperature of second annealing 231 is too low, annealing time is such as
Fruit is too short, then is unfavorable for driving further releasing for remnants H in the interlayer dielectric layer 230, is unfavorable for the interlayer dielectric layer
230 consistency further increase.
Specifically, in the present embodiment, the annealing temperature of second annealing 231 within the scope of 550 DEG C to 700 DEG C,
Annealing time is in 10min to 150min range, therefore second annealing 231 can be in the premise of control heat budget
Under, the consistency of the interlayer dielectric layer 230 is effectively further increased, the simultaneous of low heat budget and high-compactness is advantageously implemented
It cares for, is conducive to the electric property for improving formed semiconductor structure.
It should be noted that with reference to figures 10 to Figure 11, in the present embodiment, the forming method further include: return and carve the layer
Between dielectric layer 230, to expose the top of the gate structure 140；Support is formed on returning the interlayer dielectric layer 230 after carving
Dielectric layer 240, the supporting medium layer 240 cover the gate structure 140.
As shown in Figure 10, the step of carving interlayer dielectric layer 230 is returned for removing the inter-level dielectric of segment thickness
Layer 230, to expose the top of the gate structure 140.Specifically, being returned by way of dry etching in the present embodiment and carving institute
State interlayer dielectric layer 230.In other embodiments of the invention, wet etching or wet etching and dry etching phase can also be passed through
In conjunction with mode return and carve the interlayer dielectric layer 230.
The supporting medium layer 240 consistency with higher, therefore part thickness is substituted by the supporting medium layer 240
The interlayer dielectric layer 230 of degree, can effectively reduce subsequent technique dielectric layer and damage, and be conducive to raising and form half
The property of conductor structure.
Specifically, passing through plasma enhanced chemical vapor deposition (Plasma-enhanced in the present embodiment
Chemical vapor deposition, PECVD) mode form the supporting medium layer 240.Plasma enhanced chemical
The technological temperature of gas-phase deposition is lower, therefore the support that under the premise of controlling heat budget, can form high-compactness is situated between
Matter layer 240, to realize taking into account for high-compactness and low heat budget.
The subsequent planarization process that carries out is to expose the top of the gate structure 140, to be subsequent metal gate structure
Formation provide Process ba- sis.Since the consistency of the supporting medium layer 240 is higher, the support in the subsequent process
A possibility that dielectric layer 240 damages is lower, is conducive to the performance for improving formed semiconductor structure, improves the semiconductor
The manufacturing yield of structure.
Correspondingly, the present invention also provides a kind of semiconductor structures.
With reference to Fig. 9, the schematic diagram of the section structure of one embodiment of semiconductor structure of the present invention is shown.
As shown in figure 9, the semiconductor structure includes: substrate 100；Interlayer dielectric layer in the substrate 100
230, the densified injection of the interlayer dielectric layer 230 handles 220 (as shown in Figure 7).
The fine and close injection processing 220 can drive H to release, to be conducive to 230 consistency of interlayer dielectric layer
It improves, and can effectively control technological temperature, be conducive to the control of heat budget, to reduce by 230 shape of interlayer dielectric layer
Influence at process to other semiconductor structures.
The substrate 100 is used to provide technological operation platform for subsequent step.The substrate 100 includes substrate 110；It is located at
Gate structure 140 on the substrate 110.
In the present embodiment, the semiconductor structure is used to form fin formula field effect transistor, so on the substrate 110 also
With fin 120 and the separation layer 130 being filled between adjacent fin 120；The gate structure 140 is across the fin
120 and covering fin 120 atop part and partial sidewall surface.
In addition, in the present embodiment, the semiconductor structure further include: be located in the 140 two sides fin 120 of gate structure
Source and drain doping area 150.
The substrate 110 provides technological operation platform to form semiconductor structure；The channel of the semiconductor structure is located at
In the fin 120.
In the present embodiment, 110 material of substrate is monocrystalline silicon.In other embodiments of the invention, the material of the substrate
It is also selected from the other materials such as polysilicon, amorphous silicon or germanium, germanium, SiGe, silicon carbide, GaAs or gallium indium.This hair
In other bright embodiments, the substrate can also be the silicon substrate on insulator, germanium substrate or glass substrate on insulator
Etc. other kinds of substrate.The material of the substrate can be the material for being suitable for process requirement or being easily integrated.
In the present embodiment, it is all monocrystalline silicon that the material of the fin 120 is identical as the material of the substrate 110.The present invention
In other embodiments, the material of the fin can also be different from the material of the substrate.The material of the fin may be
The other materials such as germanium, germanium, SiGe, silicon carbide, GaAs or gallium indium.
The separation layer 130 covers the partial sidewall of the fin 120, and is lower than the fin at the top of the separation layer 130
120 top of portion.Isolation structure of the separation layer 130 as semiconductor structure, can adjacent devices and adjacent fin it
Between play the role of electric isolation.The separation layer 130 be located at the fin 120 exposing the substrate 110 on, and it is described every
The height of absciss layer 130 is lower than the height of the fin 120.
In the present embodiment, the material of the separation layer 130 is silica.In other embodiments of the invention, the isolation junction
The material of structure can also be other insulating materials such as silicon nitride or silicon oxynitride.
In the present embodiment, the semiconductor structure has high-K metal gate structure, so the gate structure 140 is puppet
Grid structure, for taking up space position for the formation of subsequent metal gate structure.But in other embodiments of the invention, the grid
Pole structure is also possible to the gate structure of the semiconductor structure, for controlling the conducting of the semiconductor structure channel and cutting
It is disconnected.
In the present embodiment, the gate structure 140 is laminated construction, and the gate structure 140 includes pseudo- oxide layer (in figure
Do not indicate) and pseudo- grid layer (not indicated in figure) in the pseudo- oxide layer.
In the present embodiment, the material of the puppet oxide layer is silica.In other embodiments of the invention, the puppet oxide layer
Material can also be silicon oxynitride.
In the present embodiment, the material of the puppet grid layer is polysilicon.In other embodiments of the invention, the material of the puppet grid layer
Material can also be other materials such as silica, silicon nitride, silicon oxynitride, silicon carbide, carbonitride of silicium, carbon silicon oxynitride or amorphous carbon
Material.In addition, dummy gate structure can also be single layer structure, correspondingly, dummy gate structure packet in other embodiments of the invention
Include pseudo- grid layer.
It should be noted that in the present embodiment, the semiconductor structure further include: be located at 140 side wall of gate structure
On side wall (not indicated in figure), to protect the gate structure 140 and define the position in the source and drain doping area 150.It is described
The material of side wall can be silica, silicon nitride, silicon carbide, carbonitride of silicium, carbon silicon oxynitride, silicon oxynitride, boron nitride or carbon
Boron nitride, the side wall can be single layer structure or laminated construction.In the present embodiment, the side wall is single layer structure, the side
The material of wall is silicon nitride.
The source and drain doping area 150 is used to form source region and the drain region of the semiconductor structure.
In the present embodiment, the source and drain doping area 150 includes: the stress positioned at the fin of 140 two sides of gate structure
Layer, the stressor layers are doped stressor layers.
In the present embodiment, the semiconductor structure is used to form cmos device, therefore the substrate 100 includes being used to form
The PMOS area 100P of the P-type device and NMOS area 100N for being used to form N-type device.So the PMOS area 100P base
Formed source and drain doping area 150 is p-type source and drain doping area in bottom 100, i.e., the described stress layer material is germanium silicon or silicon, the stress
Doped ions are P-type ion, such as B, Ga or In in layer；Source and drain doping is formed by the NMOS area 100N substrate 100
Area 150 is N-type source and drain doping area, i.e., the material of the described stressor layers is carbon silicon or silicon, and the Doped ions in the stressor layers are N-type
Ion, such as: P, As or Sb.
But in other embodiments of the present invention, the substrate can also only include the area PMOS for being used to form P-type device
Domain, alternatively, only including the NMOS area for being used to form N-type device.
It should be noted that in the present embodiment, the semiconductor structure further include: be located at 140 two sides of gate structure
Lightly doped district (Lightly Doped Drain, LDD) in fin 120, to improve the performance of the semiconductor structure.
The interlayer dielectric layer 230 is for realizing the electric isolution between adjacent semiconductor constructs.
The interlayer dielectric layer 230 is that forerunner's dielectric layer 210 is formed after processing.And forerunner's dielectric layer
210 be that fluidized bed 211 (as shown in Figure 5) is cured and formed.
The fluidized bed 211 has certain mobility, can flow to needs under fluid or viscid state and fill out
In the various structures filled, and filling from bottom to top is carried out, is sufficient filling with to realize.
In the present embodiment, the material of the fluidized bed 211 is trimethyl silicane alkanamine (Trisilylamine, TSA).This hair
In bright other embodiments, the material of the fluidized bed can also be in fluid or viscid material for other, such as include poly- second silicon
The polysilanes materials such as penta silane of alkane and ring.
Specifically, the injection ion of the fine and close injection processing 220 is He or Si.The injection of He or Si ion can drive
Chemical bond rupture between Si and H and between O and H is conducive to forerunner's medium so as to effectively drive releasing for H
The raising of 210 consistency of layer；And the injection of He and Si, impurity will not be introduced in forerunner's dielectric layer 210 and influence institute
The electric isolution performance for stating interlayer dielectric layer 230 can reduce the fine and close injection and handle 220 pairs of semiconductor structure performances
It influences.Specifically, Doped ions concentration is in 1.0E19atom/cm in the interlayer dielectric layer 230 of densified injection processing 2003It arrives
8.0E21atom/cm3In range.
As shown in fig. 7, the substrate 100 includes substrate 110 and the institute on the substrate 120 in the present embodiment
State gate structure 140；The gate structure 140 is projected on the surface of the substrate 110；Therefore the fine and close injection processing 220
Injection depth d be less than or equal to the gate structure 140 on forerunner's dielectric layer 210 thickness h, to control the cause
The injection phase of close 220 injection ion of injection processing reduces influence of the fine and close injection processing to structure in the substrate, to the greatest extent
Amount reduces the fine and close injection processing 220 and injects ion into the gate structure 140, reduces the gate structure 140 and damages
Appearance, be conducive to the influence for improving the semiconductor structure performance.
It should be noted that the injection depth of the fine and close injection processing 220 should not be too large also should not mistake in the present embodiment
It is small.If the injection depth of the fine and close injection processing 220 is too big, the gate structure 140 will increase by the shadow injected
It rings, injection ion may enter the performance that the gate structure 140 is influenced in the gate structure 140, cause grid
Structure 140 is impaired, may cause the decline of the semiconductor structure performance and the loss of yield；The densification injection processing
If 220 injection depth is too small, the injection ion of the fine and close injection processing 220 is too near to forerunner's dielectric layer 210
Top, be unfavorable for releasing for deep layer H, be unfavorable for reducing the concentration of remnants H in the interlayer dielectric layer 230, be unfavorable for described
The raising of 230 consistency of interlayer dielectric layer.Specifically, the injection depth of the fine and close injection processing 220 existsIt arrivesIn range.
It should be noted that the semiconductor structure is is provided semiconductor structure through the invention in the present embodiment
Semiconductor structure is formed by method.Specific technical solution refers to the record of aforesaid semiconductor Structure formation method embodiment,
Details are not described herein by the present invention.
To sum up, the fine and close injection processing can drive the H in forerunner's dielectric layer to release, to be conducive to the layer
Between dielectric layer consistency raising, the performance of the interlayer dielectric layer can be effectively improved；And technological temperature can be effectively controlled,
To be conducive to the control of heat budget, the inter-level dielectric layer formation process can be effectively reduced to the shadow of other semiconductor structures
It rings；So technical solution of the present invention can be realized, consistency is improved and what heat budget reduced takes into account, and is conducive to raising and is formed half
The electric property of conductor structure.And in optinal plan of the present invention, it is described densification injection processing be heat injection by way of into
Row, can effectively improve the consistency of the interlayer dielectric layer；And it in the reasonable scope by technological temperature control, can
The heat budget to be formed during the semiconductor structure is effectively reduced；So technical solution of the present invention can take into account low heat budget and
High-compactness requirement, can effectively improve the electric property of formed semiconductor structure.In addition, in optinal plan of the present invention,
After carrying out fine and close injection processing, the second annealing is carried out；Second annealing can be such that remaining H releases, thus
It realizes that further increasing for the interlayer dielectric layer consistency is advantageously implemented taking into account for low heat budget and high-compactness, is conducive to
Improve the electric property of formed semiconductor structure.In addition, the injection of the fine and close injection processing is deep in optinal plan of the present invention
Degree is less than or equal to the thickness of forerunner's dielectric layer on the gate structure.The injection for controlling the fine and close injection processing is deep
Degree can control the injection phase of the fine and close injection processing injection ion, effectively so as to reduce at the fine and close injection
The influence to structure in the substrate is managed, the influence for improving formed semiconductor structure performance is conducive to.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (20)
1. a kind of forming method of semiconductor structure characterized by comprising
Form substrate；
Forerunner's dielectric layer is formed on the substrate；
Fine and close injection processing is carried out to forerunner's dielectric layer, to form interlayer dielectric layer.
2. forming method as described in claim 1, which is characterized in that the injection ion of the fine and close injection processing be He or
Si。
3. forming method as claimed in claim 1 or 2, which is characterized in that carry out the fine and close note by way of heat injection
Enter processing.
4. forming method as claimed in claim 3, which is characterized in that the technological temperature of the fine and close injection processing is at 450 DEG C
To within the scope of 500 DEG C.
5. forming method as described in claim 1, which is characterized in that formed substrate the step of include:
Substrate is provided；
Gate structure is formed over the substrate；
Forerunner's dielectric layer covers the gate structure.
6. forming method as claimed in claim 5, which is characterized in that the injection depth of the fine and close injection processing is less than or waits
In the thickness of forerunner's dielectric layer described on the gate structure.
7. the forming method as described in claim 1,5 or 6, which is characterized in that the injection depth of the fine and close injection processing existsIt arrivesIn range.
8. forming method as described in claim 1, which is characterized in that the technological parameter of the fine and close injection processing includes: work
Skill temperature is within the scope of 300 DEG C to 600 DEG C；Implantation Energy is in 10KeV to 200KeV range；Implantation dosage exists
2.0E14atom/cm2To 5.0E16atom/cm2In range.
9. forming method as described in claim 1, which is characterized in that formed in such a way that fluid chemistry is vapor-deposited described
Forerunner's dielectric layer.
10. the forming method as described in claim 1 or 9, which is characterized in that the step of forming forerunner's dielectric layer include:
Fluidized bed is formed on the substrate；
Curing process is carried out to the fluidized bed.
11. forming method as claimed in claim 10, which is characterized in that carried out by way of the first annealing described solid
Change processing, first annealing are that steam makes annealing treatment.
12. forming method as claimed in claim 11, which is characterized in that the annealing temperature of first annealing is 450
DEG C within the scope of 600 DEG C, annealing time is in 10min to 200min range.
13. forming method as described in claim 1, which is characterized in that the forming method further include: carry out at fine and close injection
After reason, the second annealing is carried out.
14. forming method as claimed in claim 13, which is characterized in that the annealing temperature of second annealing is 550
DEG C within the scope of 700 DEG C, annealing time is in 10min to 150min range.
15. forming method as claimed in claim 13, which is characterized in that in N2Second annealing is carried out under atmosphere.
16. a kind of semiconductor structure characterized by comprising
Substrate；
Interlayer dielectric layer in the substrate, the densified injection processing of interlayer dielectric layer.
17. semiconductor structure as claimed in claim 16, which is characterized in that the injection ion of the fine and close injection processing is He
Or Si.
18. semiconductor structure as claimed in claim 16, which is characterized in that the injection depth of the fine and close injection processing existsIt arrivesIn range.
19. semiconductor structure as claimed in claim 16, which is characterized in that the technological parameter packet of the fine and close injection processing
Include: technological temperature is within the scope of 300 DEG C to 600 DEG C；Implantation Energy is in 10KeV to 200KeV range；Implantation dosage exists
2.0E14atom/cm2To 5.0E16atom/cm2In range.
20. semiconductor structure as claimed in claim 16, which is characterized in that the substrate include substrate and be located at the substrate
On gate structure；
The interlayer dielectric layer covers the gate structure；
The injection depth of the fine and close injection processing is less than or equal to the thickness of forerunner's dielectric layer on the gate structure.
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