CN105336773A - Fin type field effect transistor and formation method thereof - Google Patents
Fin type field effect transistor and formation method thereof Download PDFInfo
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- CN105336773A CN105336773A CN201410261126.4A CN201410261126A CN105336773A CN 105336773 A CN105336773 A CN 105336773A CN 201410261126 A CN201410261126 A CN 201410261126A CN 105336773 A CN105336773 A CN 105336773A
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Abstract
The invention provides a fin type field effect transistor and a formation method thereof. The formation method of a fin type field effect transistor comprises: ions are implanted into a semiconductor substrate, a first region doped with ions is formed in the semiconductor substrate, and the rest region of the semiconductor substrate serves as a second region; the first region and the second region are etched to form a fin, wherein the etching rate of the first region is lower than the etching rate of the second region, and thus the fin contains an ion implantation layer formed by etching the first region, wherein the width of the ion implantation layer is larger than that of the fin above the ion implantation layer; and a dielectric layer is formed on the semiconductor substrate and is exposed out of the ion implantation layer, a grid electrode crossing the fin is formed, and a source-drain region is formed in the fin. With the ion implantation layer, source-drain ion diffusion that is caused by source-drain ion implantation into the fin can be effectively inhibited, so that the depth of the ions in the source-drain region can be reduced, the accumulated fixed charge quantity at the juncture of the fin and the dielectric layer can be reduced during the application process, and thus the electrical performance of the fin type field effect transistor can be improved.
Description
Technical field
The present invention relates to semiconductor and form field, especially relate to a kind of fin formula field effect transistor and forming method thereof.
Background technology
Along with the develop rapidly of integrated circuit (being called for short IC) manufacturing technology, the process node of traditional integrated circuit reduces gradually, the size of integrated circuit (IC)-components constantly reduces, and integrated circuit (IC)-components preparation technology constantly reforms the performance improving integrated circuit (IC)-components.
As in MOS transistor, obtain desirable threshold voltage by forming the metal with different work functions between high-K dielectric layer and metal gates, thus improve device performance.But along with the reduction gradually of characteristic size, traditional plane formula MOS transistor cannot meet the demand to device performance, as the control ability of plane formula MOS transistor to channel current dies down, causes serious leakage current.For this reason, multi-gate device is paid close attention to widely as alternative the obtaining of conventional device.
The one that fin formula field effect transistor (FinFET) is described multi-gate device.Shown in figure 1, FinFET comprises: Semiconductor substrate 1; Be positioned at the fin 3 in Semiconductor substrate 1; Be positioned at the oxide layer 2 in Semiconductor substrate 1; Be positioned at oxide layer 2 surface successively and across the gate dielectric layer (not shown) of fin 3 and grid 4; Side wall 6 between the fin being positioned at fin 3 both sides; Be positioned at the grid curb wall 5 of grid 4 both sides; Be positioned at the source/drain 31 of grid 4 and grid curb wall 5 liang of lateral fins 3.
The part that the top of fin 3 of FinFET and the sidewall of both sides contact with grid all becomes channel region, and namely said structure makes a FinFET have effect of multiple grid simultaneously, thus is conducive to increasing drive current, improves device performance.
Incorporated by reference to reference to shown in figure 2, the preparation technology of FinFET comprises:
First be etched in Semiconductor substrate 1 and form multiple fin 3, form oxide skin(coating) 2 on semiconductor substrate 1 afterwards, remove the oxide skin(coating) 2 of segment thickness, after making fin 3 upper end expose described oxide skin(coating) 2, gate dielectric and semiconductor material layer (not shown) is formed according to this above described fin 3 with oxide skin(coating) 2, and form as shown in Figure 1 in described fin 3 and semiconductor material layer both sides side wall 6 between fin, side wall 6 is formed the grid 4 across side wall 6 between described fin 3 and fin between described fin 3 and fin, the sidewall of described grid 4 forms grid curb wall 5, source/drain 31 is formed in the fin 3 exposed at described grid 4 and grid curb wall 5 by modes such as ion implantations afterwards.
But along with FinFET development, find that the electric property of the FinFET formed by existing technique is unstable, thus have impact on the performance of FinFET, the performance how improving FinFET is the problem that those skilled in the art need solution badly for this reason.
Summary of the invention
The problem that the present invention solves is providing a kind of fin formula field effect transistor and forming method thereof, optimizes the performance of fin formula field effect transistor.
For solving the problem, the invention provides a kind of formation method of semiconductor device, comprising:
Semiconductor substrate is provided;
In described Semiconductor substrate, inject ion, form the first area doped with described ion in described Semiconductor substrate, other regions of Semiconductor substrate are second area;
Etch first area and the second area of described Semiconductor substrate, to form fin, the etch rate of described first area is less than the etch rate of described second area, make described fin comprise the ion implanted layer of etching described first area formation, and the width of described ion implanted layer is greater than the width of fin above described ion implanted layer;
The Semiconductor substrate that described fin exposes forms dielectric layer, and described dielectric layer exposes described ion implanted layer;
Described dielectric layer is formed the grid across described fin;
Source-drain area is formed in the fin that described grid exposes.
Alternatively, in described Semiconductor substrate, inject ion, in described Semiconductor substrate, the step formed doped with the first area of described ion comprises:
Carbon ion is injected in described Semiconductor substrate.
Alternatively, the step injecting ion in described Semiconductor substrate comprises: the dosage injecting carbon ion is 1.0 × 10
13~ 1.0 × 10
17/ cm
2, energy is 1 ~ 20eV.
Alternatively, etch first area and the second area of described Semiconductor substrate, comprise with the step forming fin:
Make the width of described ion implanted layer than the width large 5% ~ 20% of fin above described ion implanted layer.
Alternatively, the thickness of described ion implanted layer is more than or equal to
Alternatively, etch first area and the second area of described Semiconductor substrate, to be formed in the step of fin, described etching is dry etching.
Alternatively, described dry etching with the mist of carbon tetrafluoride, Nitrogen trifluoride and oxygen for etching gas.
Alternatively, the step of described dry etching comprises: air pressure is 10 ~ 200mtorr, and radio-frequency power is 100 ~ 1000W, and bias power is 0 ~ 300W, the flow of described carbon tetrafluoride is 10 ~ 200sccm, the flow of Nitrogen trifluoride is 0 ~ 200sccm, and the flow of described oxygen is 1 ~ 100sccm.
Alternatively, described etching gas also comprises one or more in hydrogen bromide, difluoromethane and chlorine.
Alternatively, described etching gas comprises: hydrogen bromide, difluoromethane and chlorine, and wherein the flow of hydrogen bromide is 10 ~ 200sccm, and the flow of difluoromethane is 10 ~ 200sccm, and the flow of chlorine is 10 ~ 200sccm.
Alternatively, etch first area and the second area of described Semiconductor substrate, comprise with the step forming fin:
Continue after etching described first area to etch the Semiconductor substrate be positioned at below described first area, in the Semiconductor substrate that described fin exposes, form groove, and the bottom of described groove is positioned at the below of described ion implanted layer.
Alternatively, described Semiconductor substrate comprises NMOS area and PMOS area;
In described Semiconductor substrate, inject ion, in described Semiconductor substrate, the step formed doped with the first area of described ion comprises:
In described NMOS area, inject described ion, in the NMOS area of described Semiconductor substrate, form described first area.
Alternatively, before inject ion in described Semiconductor substrate, the formation method of described fin formula field effect transistor also comprises:
To the NMOS area implanting p-type ion of described Semiconductor substrate, form P trap;
PMOS area to described Semiconductor substrate injects N-type ion, forms N trap;
Ion is injected in described Semiconductor substrate, the first area doped with described ion is formed in described Semiconductor substrate, other regions of Semiconductor substrate are that the step of second area comprises: inject ion in described NMOS area, in described NMOS area, form described first area;
Etch first area and the second area of described Semiconductor substrate, comprise with the step forming fin: etch described PMOS area and NMOS area, form PMOS fin in PMOS area, form NMOS fin in NMOS area, described NMOS fin comprises described ion implanted layer.
Alternatively, the step Semiconductor substrate exposed at described fin being formed dielectric layer comprises: adopt in the Semiconductor substrate of fluid chemistry vapour deposition process between described fin and form dielectric layer.
Present invention also offers a kind of fin formula field effect transistor, comprising:
Semiconductor substrate;
Be positioned at the fin in described Semiconductor substrate, comprise the ion implanted layer doped with ion at described fin, the width of described ion implanted layer is greater than the width of fin above described ion implanted layer;
Be positioned at the dielectric layer in Semiconductor substrate that described fin exposes, described dielectric layer exposes described ion implanted layer;
On described dielectric layer, and across the grid of described fin;
Be arranged in the source-drain area of the fin that described grid exposes.
Alternatively, the width of the ion implanted layer in described fin is than the width large 5% ~ 20% of fin above described ion implanted layer.
Alternatively, described ion implanted layer is between adjacent fins above Semiconductor substrate.
Alternatively, described fin formula field effect transistor is NMOS fin formula field effect transistor.
Alternatively, described ion is carbon ion.
Alternatively, the thickness of described ion implanted layer is more than or equal to
Compared with prior art, technical scheme of the present invention has the following advantages:
After providing Semiconductor substrate, in described Semiconductor substrate, inject ion, form the first area doped with described ion in described Semiconductor substrate, other regions of Semiconductor substrate are second area; Etch first area and the second area of described Semiconductor substrate, to form fin, the etch rate of described first area is less than the etch rate of described second area, make described fin comprise the ion implanted layer of etching described first area formation, and the width of described ion implanted layer is greater than the width of fin above described ion implanted layer; Afterwards, the Semiconductor substrate that described fin exposes forms dielectric layer, and described dielectric layer exposes described ion implanted layer, and forms the grid across described fin on described dielectric layer, source-drain area is formed, to form fin formula field effect transistor in the fin that described grid exposes.Described ion implanted layer effectively can suppress source and drain ion diffuse in fin, thus the degree of depth of ion in source-drain area can be reduced, and then be in use reduced in the amount of the fixed charge that fin and place, dielectric layer boundary are gathered, to improve the electric property of fin formula field effect transistor.
In possibility, form N trap and P trap in described Semiconductor substrate after, then etch described Semiconductor substrate formation PMOS fin and NMOS fin.Compared in the formation method of existing fin formula field effect transistor, first etch semiconductor substrates forms fin, PMOS area (or NMOS area) is covered afterwards with photoresist, implanting p-type ion (N-type ion) in the fin of NMOS area (or PMOS area), after forming P trap (or N trap) technique, when removing photoresist, PMOS (or NMOS fin) can be caused to damage.Technique scheme, first forms N trap and P trap, and the technical scheme of etch semiconductor substrates formation PMOS fin and NMOS fin effectively can reduce PMOS fin and the damage of NMOS fin more afterwards, thus improves performance of semiconductor device.
Accompanying drawing explanation
The structural representation of the existing fin formula field effect transistor of Fig. 1;
Preparation technology's structural representation of the existing fin formula field effect transistor of Fig. 2;
Fig. 3 is the electric property figure of existing NMOS fin formula field effect transistor;
Fig. 4 is the electric property figure of existing PMOS fin formula field effect transistor;
Fig. 5 to Figure 11 is the schematic diagram of the formation method of the fin formula field effect transistor that one embodiment of the invention provides;
Figure 12 is the electric property comparison diagram of the NMOS fin formula field effect transistor that existing NMOS fin formula field effect transistor and one embodiment of the invention provide;
Figure 13 and 14 is the schematic diagram of the formation method of the fin formula field effect transistor that another embodiment of the present invention provides;
Figure 15 ~ 16 are the structural representations of the fin formula field effect transistor that one embodiment of the invention provides;
Figure 17 ~ 18 are the structural representations of the fin formula field effect transistor that another embodiment of the present invention provides.
Embodiment
As described in the background art, the electrical performance stability of the fin formula field effect transistor formed by existing technique is poor, in order to obtain the poor reason of electrical performance stability, in running order fin formula field effect transistor is analyzed: fin formula field effect transistor grid can gather a large amount of fixed charges (fixedoxidecharge) at the intersection of fin and oxide layer after applying voltage.
With reference to figure 3 and Fig. 4, respectively illustrate fin and the electrical performance testing figure with oxide layer intersection in existing nmos pass transistor and PMOS transistor.Wherein, the longitudinal axis is threshold voltage, and transverse axis is fixed charge amount, the electric property curve of L1 and L3 to be width the be fin of about 6nm, the electric property curve of L2 and L4 to be width the be fin of about 9nm.Comparison diagram 4 and Fig. 3 known, in use, in N-type fin formula field effect transistor, fin and dielectric layer intersection can gather a large amount of fixed charges, and along with threshold voltage increase, the amount of charge gathered sharply increases.These fixed charges accumulating in fin and dielectric layer intersection can cause fin to be punctured by electric current, thus reduce the electrical performance stability of FinFET, and then reduce the performance of FinFET.
For this reason, the invention provides a kind of fin formula field effect transistor and forming method thereof, wherein, the formation method of fin formula field effect transistor comprises: in described Semiconductor substrate, inject ion, in described Semiconductor substrate, form the first area doped with described ion, other regions of Semiconductor substrate are second area; Etch first area and the second area of described Semiconductor substrate, to form fin, the etch rate of described first area is less than the etch rate of described second area, make described fin comprise the ion implanted layer of etching described first area formation, and the width of described ion implanted layer is greater than the width of fin above described ion implanted layer; Afterwards, the Semiconductor substrate that described fin exposes forms dielectric layer, and described dielectric layer exposes described ion implanted layer, and forms the grid across described fin on described dielectric layer, source-drain area is formed, to form fin formula field effect transistor in the fin that described grid exposes.Described ion implanted layer effectively can suppress source and drain ion diffuse when injecting source and drain ion in the fin of metal gates both sides, thus the degree of depth of ion in source-drain area can be reduced, and then in use compared to existing fin formula field effect transistor, the fin formula field effect transistor adopting the formation method of fin formula field effect transistor of the present invention to be formed can effectively reduce in FinFET, the fixed charge amount that fin and oxide layer intersection gather, thus improve the electric property of FinFET.
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Fig. 5 to Figure 11 is the schematic diagram of the formation method of the fin formula field effect transistor that one embodiment of the invention provides.
The formation method of the present embodiment fin formula field effect transistor comprises:
Shown in first reference diagram 5, provide Semiconductor substrate 100.
Semiconductor substrate 100 in the present embodiment is silicon substrate, and described Semiconductor substrate 100 can also be germanium, germanium silicon, gallium arsenide substrate or silicon-on-insulator substrate in other embodiments, and common Semiconductor substrate all can be used as the Semiconductor substrate in the present embodiment.
Described Semiconductor substrate 100 comprises NMOS area I and PMOS area II.Described NMOS area I is for the formation of NMOS fin formula field effect transistor, and described PMOS area II is for the formation of PMOS fin formula field effect transistor.
In described NMOS area I, implanting p-type ion is to form P trap 110, in described PMOS area II, inject N-type ion, forms N trap 120.
Described P type ion comprises B plasma, and described N-type ion comprises phosphorus (P), arsenic (As) plasma.In described Semiconductor substrate, implanting p-type ion and N-type ion processes are this area maturation process, do not repeat them here.
Shown in figure 6, in described Semiconductor substrate 100, inject ion, form the first area 130 doped with described ion in the NMOS area I of described Semiconductor substrate 100, other regions of described Semiconductor substrate 100 are second area.Wherein, in the NMOS area I of described Semiconductor substrate 100, above and below first area 130 described in through-thickness, be a part for second area.
In the present embodiment, described first area 130 is positioned at described P trap 110.
In the present embodiment, the concrete steps injecting ion in described Semiconductor substrate 100 comprise:
Described Semiconductor substrate 100 forms photoresist layer 210, described photoresist layer 210 covers described PMOS area II, exposed portion NMOS area I, injects ion with described photoresist layer 210 for mask afterwards in described NMOS area, to form described first area 130.In the present embodiment, described ion is carbon ion (C), and the parameter of the technique of ion implantation comprises: the carbon ion dosage of injection is 1.0 × 10
13~ 1.0 × 10
17/ cm
2, energy is 1 ~ 20
xv.
Shown in figure 7 and Fig. 8, etch described Semiconductor substrate 100, described Semiconductor substrate 100 is formed NMOS fin and PMOS fin.Detailed process comprises:
Described Semiconductor substrate 100 forms hard mask layer 221, amorphous carbon layer 222 and the anti-reflecting layer (Si-ARC layer) 223 based on Si from the bottom to top successively, photoetching agent pattern 224 is formed afterwards on described Si-ARC layer 223, and with described photoetching agent pattern 224 for Si-ARC layer 223, amorphous carbon layer 222 and hard mask layer 221 described in mask etching, form hard mask 220.
Then with reference to shown in figure 8, with described hard mask 220 for Semiconductor substrate described in mask etching 100, NMOS fin 310 is formed at described NMOS area I, PMOS fin 320 is formed in PMOS area II, and between adjacent fin (comprising PMOS fin and NMOS fin), in the Semiconductor substrate that fin exposes, form groove (not indicating in figure).
In the present embodiment, when etching described NMOS area I, etching after described first area 130 forms ion implanted layer 131, continue the described Semiconductor substrate 100 of etching, the ion implanted layer 131 formed is made to be positioned at the top of described channel bottom, have certain distance between described ion implanted layer 131 and channel bottom, namely described ion implanted layer 131 is positioned at the centre position of described NMOS fin 310.
In etching process, in described NMOS area I, etch rate doped with the described first area 130 of carbon ion is less than not doped with the etch rate of the second area of carbon ion in Semiconductor substrate 100, and namely the etch rate of described first area 130 is less than above described first area 130 and the etch rate of the Semiconductor substrate 100 of below.In the described NMOS fin 310 that the NMOS area I etching described Semiconductor substrate 100 is formed, the width etching the ion implanted layer 131 that described first area 130 is formed is greater than above described ion implanted layer 131 and the width of the fin of below, namely, in described NMOS fin 310, described ion implanted layer 131 protrudes from the sidewall of described NMOS fin 310.
In described NMOS fin 310, if the width of described ion implanted layer 131 is excessive, makes the oversize of described fin 310, affect the performance of other structures such as the grid in the nmos pass transistor of follow-up formation and described NMOS fin 310; If width is too small, follow-up when injecting source and drain ion to form source-drain area in fin, described ion implanted layer 131 cannot stop source and drain ion to spread in the fin below ion implanted layer 131 and Semiconductor substrate effectively, cause in the final follow-up use procedure of fin formula field effect transistor formed, a large amount of fixed charges can be gathered in the dielectric layer junction of NMOS fin 310 and follow-up formation, thus reduce performance of semiconductor device.
In the present embodiment, the width of NMOS fin 310 intermediate ion implanted layer 131 is than the width large 5% ~ 20% of fin above described ion implanted layer 131.
In the present embodiment, etching the step that described Semiconductor substrate 100 forms fin is dry etch process, and described dry etch process specifically comprises: with carbon tetrafluoride (CF
4), Nitrogen trifluoride (NF
3) and oxygen (O
2) mist be etching gas, controlling the air pressure of etching gas is 10 ~ 200mtorr, and radio-frequency power is 100 ~ 1000W, and bias power is 0 ~ 300W.Wherein, the flow of described carbon tetrafluoride is 10 ~ 200sccm, the flow of Nitrogen trifluoride is 0 ~ 200sccm, and the flow of described oxygen is 1 ~ 100sccm.
Alternatively, described etching gas also comprises hydrogen bromide (HBr), difluoromethane (CH
2f
2) and chlorine (Cl
2) in one or more, to improve the etch rate etching described Semiconductor substrate 100.In the present embodiment, described etching gas includes hydrogen bromide, difluoromethane and chlorine, and wherein, the flow of hydrogen bromide is 10 ~ 200sccm, and the flow of difluoromethane is 10 ~ 200sccm, and the flow of chlorine is 10 ~ 200sccm.
In the present embodiment, the material of described hard mask layer 221 is silicon nitride layer, and be the overall pattern precision that can effectively to improve as hard mask 220 in hard mask 220 using described Si-ARC layer 223, amorphous carbon layer 222 and hard mask layer 221, thus the structure precision of the fin formed after improving Semiconductor substrate 100 described in subsequent etching.But in other embodiments except the present embodiment; only can form photoetching agent pattern on described hard mask layer 221; be mask patterning described hard mask layer 221 with described photoetching agent pattern afterwards; and with the hard mask layer 221 after graphical for Semiconductor substrate described in mask etching 100; it can realize object of the present invention equally, and these simply change all in protection scope of the present invention.
Shown in figure 9, after removal described photoetching agent pattern 224, Si-ARC layer 223 and amorphous carbon layer 222, described Semiconductor substrate 100 forms dielectric layer 140, and described dielectric layer covers described PMOS fin 320 and NMOS fin 310; Afterwards, the planarization such as cmp (ChemicalMechanicalpolishing, CMP) are adopted to remove part dielectric layer, to exposing described hard mask layer 211.
In the present embodiment, described dielectric layer 140 is silicon oxide layer, and formation process is fluid chemistry vapour deposition process (F-CVD).Adopt fluid chemistry vapour deposition process effectively can improve the filling capacity of dielectric layer material between each fin, to improve the performance of the semiconductor device of follow-up formation.But material and the formation process thereof of described dielectric layer do not limit protection scope of the present invention, dielectric layer material of the prior art, and its formation process is all applicable to the present invention.
With reference to shown in Figure 10, continue with described hard mask layer 221 for mask, remove the described dielectric layer 140 of segment thickness, until expose described ion implanted layer 131 surface, or exposed portion thickness but not the described ion implanted layer 131 of full depth.Wherein, the described ion implanted layer 131 of remaining dielectric layer 141 cover part thickness, and NMOS fin 310 below ion implanted layer 131 and PMOS fin 320, the NMOS fin 310 above ion implanted layer 131 and PMOS fin 320 protrude from described dielectric layer 141 surface.
In the present embodiment, the technique removing the described dielectric layer 140 of segment thickness is dry etch process.Comprise particularly and adopting containing fluoroform (CHF
3), Nitrogen trifluoride (NF
3) or oxygen (O
2) etc. gas etchant described in dielectric layer 140.But the technique etching described dielectric layer does not limit protection scope of the present invention, in this area, the technique of etch media layer is all applicable to the present invention.
If the thickness of described ion implanted layer 131 is too small, follow-up when injecting source and drain ion to form source-drain area in fin, source and drain ion still can penetrate described ion implanted layer 131 and enter in the fin below ion implanted layer 131, and then in the fin formula field effect transistor use procedure of follow-up formation, still can gather relatively large fixed charge at the intersection of fin and dielectric layer.
In the present embodiment, the thickness of described ion implanted layer 131 (i.e. described first area 130) is more than or equal to
Then described in reference diagram 11, remove described hard mask layer 211, expose described NMOS fin 310 and PMOS fin 320 top.
In the present embodiment, the technique removing described hard mask layer 211 is wet-etching technology.Particularly, phosphoric acid solution can be adopted as wet etchant, reduce the damage of other structures of semiconductor device at the described hard mask layer 211 of removal simultaneously.
Afterwards, described Semiconductor substrate 100 forms gate dielectric, described dielectric layer 141 is formed the grid across described NMOS fin 310 (or PMOS fin 320), and to described grid both sides expose fin in inject source and drain ion, to form source-drain area, thus form fin formula field effect transistor, above-mentioned grid, with the maturation process that the formation process of source-drain area is this area, do not repeat them here.
In the present embodiment, the etch rate of the first area in described NMOS area I is less than the etch rate of described second area, in the NMOS fin of follow-up formation, the width etching the ion implanted layer that described first area is formed is greater than the width of the fin above and below described ion implanted layer; Thus the Semiconductor substrate exposed at described fin forms dielectric layer, and form grid on described dielectric layer after, source and drain ion is injected to form the process of source-drain area in the fin that grid both sides are exposed, described ion implanted layer can effectively suppress source and drain ion diffuse, thus the degree of depth of ion in source-drain area can be reduced, and then be in use reduced in the fixed charge amount gathered of fin and dielectric layer intersection, thus improve the electric property of fin formula field effect transistor.
Shown in reference Figure 12, the electrical performance testing figure comparison diagram of the fin formula field effect transistor that the existing fin formula field effect transistor that Figure 12 is same size obtains with the formation method of the fin formula field effect transistor adopting the present embodiment to provide, wherein, L5 is the electric property curve of existing NMOS fin formula field effect transistor, the electric property curve of the nmos pass transistor of the fin formula field effect transistor that the formation method of the fin formula field effect transistor that L6 provides for this enforcement obtains.
As shown in Figure 12, compared to existing fin formula field effect transistor, in use procedure, under identical threshold voltage condition, the nmos pass transistor that the formation method of the fin formula field effect transistor that the present embodiment provides obtains obviously reduces in the fixed charge amount of the intersection of fin and dielectric layer.Thus effectively can reduce the breakdown probability of fin, improve the performance of fin formula field effect transistor.
In addition, when etching described NMOS area I to form NMOS fin, after having etched described first area formation ion implanted layer, continue the described Semiconductor substrate of etching, make above the channel bottom of the ion implanted layer of formation in described Semiconductor substrate between adjacent fins, between described ion implanted layer and channel bottom, there is certain distance, adopt filled media layer material in the groove of fluid chemistry vapour deposition process between adjacent fins afterwards.Technique scheme effectively can improve the filling capacity of the dielectric layer material between each fin, improve packing and the uniformity of the dielectric layer of follow-up formation, as the uniformity of the dielectric layer at ion implanted layer lower corners place and the dielectric layer of other parts that improve fin, and then improve the performance of fin formula field effect transistor of follow-up formation.
And, in the formation method of the present embodiment fin formula field effect transistor, first described Semiconductor substrate 100 in after formation N trap and P trap, then etch described Semiconductor substrate 100 and form PMOS fin and NMOS fin.Compared in the formation method of existing fin formula field effect transistor, first etch semiconductor substrates forms fin, PMOS area (or NMOS area) is covered afterwards with photoresist, implanting p-type ion (N-type ion) in the fin of NMOS area (or PMOS area), after forming P trap (or N trap) technique, when removing photoresist, PMOS fin (or NMOS fin) can be caused to damage.The present embodiment effectively can reduce PMOS fin and the damage of NMOS fin, to improve performance of semiconductor device.
In above-described embodiment, in NMOS fin, the width of described ion implanted layer is greater than the width of the fin above and below described ion implanted layer, but in other embodiments in addition to the implementation, in described NMOS fin, the fin width below described ion implanted layer can be greater than or equal to the width of described ion implanted layer.That is, the NMOS area of etching semiconductor device is with in the NMOS fin formed, and the width that the width of ion implanted layer only need be greater than fin above described ion implanted layer just can realize object of the present invention.
It is the structural representation of another embodiment of formation method of fin formula field effect transistor of the present invention as Figure 13 and Figure 14, its technique is roughly similar to the formation method of the fin formula field effect transistor that a upper embodiment provides, its difference is, after injecting ion and form first area 150 in Semiconductor substrate 120, when etching described Semiconductor substrate 120 to form NMOS fin 340, half-and-half lead and the bottom surface of described fin 340 is flushed with the bottom surface of the ion implanted layer 151 formed in described first area 150, namely described ion implanted layer 151 occupies the Lower Half of described NMOS fin 340, also namely described ion implanted layer 151 extends to described fin 340 bottom surface.That is, the width of the lower semisection of described fin 340 is greater than the width of described fin 340 upper semisection;
Afterwards, after Semiconductor substrate 120 is formed dielectric layer 143, ion implanted layer 151 described in described dielectric layer 143 exposed portion; And gate dielectric is formed in described Semiconductor substrate 120, and across the structure such as grid of described fin, and inject source and drain ion in the fin exposed to described grid both sides, to form source-drain area, thus form fin formula field effect transistor.
Correspondingly, present invention also offers a kind of fin formula field effect transistor.
The structural representation of the fin formula field effect transistor that the embodiment that Figure 15 and Figure 16 is the formation method adopting the fin formula field effect transistor shown in above-mentioned Fig. 5 ~ Figure 11 obtains.But fin formula field effect transistor provided by the invention is not limited to and forms being formed of method by above-mentioned fin formula field effect transistor.Herein, Figure 16 be Figure 15 along A-A to generalized section.
Shown in reference Figure 15 and 16, the concrete structure of the fin formula field effect transistor that the present embodiment provides comprises:
Semiconductor substrate 400,
Be positioned at the fin 420 in described Semiconductor substrate 400.Wherein, comprise ion implanted layer 421 at described fin 420, described ion implanted layer 421 is doped with ion, and fin 420 part above and below described ion implanted layer 421 is not doped with ion.The width of described ion implanted layer 421 is greater than above described ion implanted layer 421, and the width of the fin 420 of below.
Be positioned at the dielectric layer 410 in described Semiconductor substrate 400 that described fin 420 exposes, described dielectric layer 410 exposes described ion implanted layer 421 surface, or exposed portion thickness but not the described ion implanted layer 421 of full depth.
Being positioned on described dielectric layer 410, across the grid 430 of described fin 420, doped with ion in the part fin 422 that described grid 430 both sides are exposed, is the source-drain electrode of fin formula field effect transistor.
In the present embodiment, described fin formula field effect transistor is NMOS fin formula field effect transistor.Doped with P type ion in described fin 420, to form P trap.Described P type ion comprises boron (B) ion etc.
In described ion implantation, the ion of doping is carbon (C) ion, and the width of described ion implanted layer 421 is than the width large 5% ~ 20% of fin above described ion implanted layer 421.
Described ion implanted layer 421 thickness is more than or equal to
Shown in reference Figure 12, compared to existing fin formula field effect transistor, the fin formula field effect transistor that the present embodiment provides is under identical threshold voltage condition, obviously less in the fixed charge amount of the intersection of fin and dielectric layer, thus effectively can reduce the breakdown probability of fin, improve the performance of fin formula field effect transistor.Its principle is described above, does not repeat them here.
Shown in reference Figure 17 and Figure 18, the structural representation of the fin formula field effect transistor that the embodiment for the formation method adopting the fin formula field effect transistor shown in above-mentioned Figure 13 ~ Figure 14 obtains.But the preparation method of the fin formula field effect transistor that the present embodiment provides is not limited to the embodiment of the formation method of above-mentioned fin formula field effect transistor.
Figure 18 be Figure 17 along B-B to generalized section.
The present embodiment and above-mentioned Figure 15 and Figure 16 provide the structural similarity of fin formula field effect transistor, its difference is, the bottom of the ion implanted layer 422 in the fin 440 of the fin formula field effect transistor that the present embodiment provides flushes with the root of fin 440, namely described ion implanted layer 422 occupies the lower semisection of described NMOS fin 440, also namely described ion implanted layer 442 extends to described fin 440 root, makes the width of the lower semisection of described fin 440 be greater than described fin 440 upper semisection width.Above-mentioned simple structural change is all in protection scope of the present invention.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (20)
1. a formation method for fin formula field effect transistor, is characterized in that, comprising:
Semiconductor substrate is provided;
In described Semiconductor substrate, inject ion, form the first area doped with described ion in described Semiconductor substrate, other regions of Semiconductor substrate are second area;
Etch first area and the second area of described Semiconductor substrate, to form fin, the etch rate of described first area is less than the etch rate of described second area, make described fin comprise the ion implanted layer of etching described first area formation, and the width of described ion implanted layer is greater than the width of fin above described ion implanted layer;
The Semiconductor substrate that described fin exposes forms dielectric layer, and described dielectric layer exposes described ion implanted layer;
Described dielectric layer is formed the grid across described fin;
Source-drain area is formed in the fin that described grid exposes.
2. the formation method of fin formula field effect transistor as claimed in claim 1, it is characterized in that, in described Semiconductor substrate, inject ion, in described Semiconductor substrate, the step formed doped with the first area of described ion comprises:
Carbon ion is injected in described Semiconductor substrate.
3. the formation method of fin formula field effect transistor as claimed in claim 2, it is characterized in that, the step injecting ion in described Semiconductor substrate comprises: the dosage injecting carbon ion is 1.0 × 10
13~ 1.0 × 10
17/ cm
2, energy is 1 ~ 20eV.
4. the formation method of fin formula field effect transistor as claimed in claim 1, is characterized in that, etch first area and the second area of described Semiconductor substrate, comprise with the step forming fin:
Make the width of described ion implanted layer than the width large 5% ~ 20% of fin above described ion implanted layer.
5. the formation method of fin formula field effect transistor as claimed in claim 1, it is characterized in that, the thickness of described ion implanted layer is more than or equal to
6. the formation method of fin formula field effect transistor as claimed in claim 1, it is characterized in that, etch first area and the second area of described Semiconductor substrate, to be formed in the step of fin, described etching is dry etching.
7. the formation method of fin formula field effect transistor as claimed in claim 6, is characterized in that, described dry etching with the mist of carbon tetrafluoride, Nitrogen trifluoride and oxygen for etching gas.
8. the formation method of fin formula field effect transistor as claimed in claim 7, it is characterized in that, the step of described dry etching comprises: air pressure is 10 ~ 200mtorr, radio-frequency power is 100 ~ 1000W, bias power is 0 ~ 300W, the flow of described carbon tetrafluoride is 10 ~ 200sccm, the flow of Nitrogen trifluoride is 0 ~ 200sccm, and the flow of described oxygen is 1 ~ 100sccm.
9. the formation method of fin formula field effect transistor as claimed in claim 7, is characterized in that, described etching gas also comprise in hydrogen bromide, difluoromethane and chlorine one or more.
10. the formation method of fin formula field effect transistor as claimed in claim 9, it is characterized in that, described etching gas comprises: hydrogen bromide, difluoromethane and chlorine, wherein the flow of hydrogen bromide is 10 ~ 200sccm, the flow of difluoromethane is 10 ~ 200sccm, and the flow of chlorine is 10 ~ 200sccm.
The formation method of 11. fin formula field effect transistors as claimed in claim 1, is characterized in that,
Etch first area and the second area of described Semiconductor substrate, comprise with the step forming fin:
Continue after etching described first area to etch the Semiconductor substrate be positioned at below described first area, in the Semiconductor substrate that described fin exposes, form groove, and the bottom of described groove is positioned at the below of described ion implanted layer.
The formation method of 12. fin formula field effect transistors as claimed in claim 1, is characterized in that,
Described Semiconductor substrate comprises NMOS area and PMOS area;
In described Semiconductor substrate, inject ion, in described Semiconductor substrate, the step formed doped with the first area of described ion comprises:
In described NMOS area, inject described ion, in the NMOS area of described Semiconductor substrate, form described first area.
The formation method of 13. fin formula field effect transistors as claimed in claim 12, is characterized in that, before inject ion in described Semiconductor substrate, the formation method of described fin formula field effect transistor also comprises:
To the NMOS area implanting p-type ion of described Semiconductor substrate, form P trap;
PMOS area to described Semiconductor substrate injects N-type ion, forms N trap;
Ion is injected in described Semiconductor substrate, the first area doped with described ion is formed in described Semiconductor substrate, other regions of Semiconductor substrate are that the step of second area comprises: inject ion in described NMOS area, in described NMOS area, form described first area;
Etch first area and the second area of described Semiconductor substrate, comprise with the step forming fin: etch described PMOS area and NMOS area, form PMOS fin in PMOS area, form NMOS fin in NMOS area, described NMOS fin comprises described ion implanted layer.
The formation method of 14. fin formula field effect transistors as claimed in claim 1, it is characterized in that, the step that the Semiconductor substrate that described fin exposes is formed dielectric layer comprises: adopt in the Semiconductor substrate of fluid chemistry vapour deposition process between described fin and form dielectric layer.
15. 1 kinds of fin formula field effect transistors, is characterized in that, comprising:
Semiconductor substrate;
Be positioned at the fin in described Semiconductor substrate, comprise the ion implanted layer doped with ion at described fin, the width of described ion implanted layer is greater than the width of fin above described ion implanted layer;
Be positioned at the dielectric layer in Semiconductor substrate that described fin exposes, described dielectric layer exposes described ion implanted layer;
On described dielectric layer, and across the grid of described fin;
Be arranged in the source-drain area of the fin that described grid exposes.
16. fin formula field effect transistors as claimed in claim 15, is characterized in that, the width of the ion implanted layer in described fin is than the width large 5% ~ 20% of fin above described ion implanted layer.
17. fin formula field effect transistors as claimed in claim 15, is characterized in that, described ion implanted layer is between adjacent fins above Semiconductor substrate.
18. fin formula field effect transistors as claimed in claim 15, it is characterized in that, described fin formula field effect transistor is NMOS fin formula field effect transistor.
19. fin formula field effect transistors as described in claim 15 or 18, it is characterized in that, described ion is carbon ion.
20. fin formula field effect transistors as claimed in claim 15, it is characterized in that, the thickness of described ion implanted layer is more than or equal to
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| US20080001171A1 (en) * | 2006-06-30 | 2008-01-03 | Tsutomu Tezuka | Field effect transistor, integrated circuit element, and method for manufacturing the same |
| US20100327363A1 (en) * | 2008-05-22 | 2010-12-30 | Panasonic Corporation | Semiconductor device and method for fabricating the same |
| US20140124794A1 (en) * | 2012-11-07 | 2014-05-08 | Globalfoundries Inc. | Fabrication of reverse shallow trench isolation structures with super-steep retrograde wells |
| CN103811320A (en) * | 2012-11-09 | 2014-05-21 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
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| US20080001171A1 (en) * | 2006-06-30 | 2008-01-03 | Tsutomu Tezuka | Field effect transistor, integrated circuit element, and method for manufacturing the same |
| US20100327363A1 (en) * | 2008-05-22 | 2010-12-30 | Panasonic Corporation | Semiconductor device and method for fabricating the same |
| US20140124794A1 (en) * | 2012-11-07 | 2014-05-08 | Globalfoundries Inc. | Fabrication of reverse shallow trench isolation structures with super-steep retrograde wells |
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