CN103811347B - The forming method of transistor - Google Patents

The forming method of transistor Download PDF

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Publication number
CN103811347B
CN103811347B CN201210454774.2A CN201210454774A CN103811347B CN 103811347 B CN103811347 B CN 103811347B CN 201210454774 A CN201210454774 A CN 201210454774A CN 103811347 B CN103811347 B CN 103811347B
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transistor
stressor layers
forming method
ion
thickness
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CN103811347A (en
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徐依协
金兰
涂火金
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions

Abstract

A kind of forming method of transistor, including：Semiconductor substrate with grid structure is provided；Opening is formed in the Semiconductor substrate of grid structure both sides；The first stressor layers are formed in the opening；Ion implanting is carried out to first stressor layers；Form the second stressor layers of the full opening of filling.The transistor performance that the Transistor forming method of the present invention is formed is good.

Description

The forming method of transistor
Technical field
The present invention relates to the forming method of field of semiconductor manufacture, more particularly to transistor.
Background technology
In super large-scale integration, generally use strained silicon technology（Strained Silicon）So that NMOS crystal Tensile stress is formed on pipe, forms compression on the pmos transistors, so as to increase the current-carrying of nmos pass transistor and PMOS transistor Transport factor, driving current is increased, improve the response speed of circuit.Embedded stress transistor is strained silicon technology application One of focus.
Fig. 1-3 is the process schematic that prior art forms embedded stress transistor.
It refer to Fig. 1, there is provided Semiconductor substrate 10, grid structure, the grid are formed on the surface of Semiconductor substrate 10 Pole structure includes gate dielectric layer 11, the gate electrode layer 12 positioned at the gate dielectric layer surface positioned at the Semiconductor substrate 10； Side wall 13 is formed in the both sides of semiconductor substrate surface, the gate dielectric layer 11 and gate electrode layer 12；
The grid structure can also include the hard mask layer positioned at the surface of gate electrode layer 12（It is not shown）；
Fig. 2 is refer to, using the side wall 13 and grid structure as mask, etch semiconductor substrates 10 form opening 14, institute It is d to state 14 depth of opening, and the opening 14 is usually " Σ " shape, it is described etch generally use wet etching, dry etching or The etching technics that Wet-dry method combines.The opening of " Σ " is used to subsequently fill stress material, and " Σ " shape opening can increase The stress effect of strong stress material.
Fig. 3 is refer to, in the opening 14（It refer to Fig. 2）Interior extension stress material until fill it is described opening 14, and Ion doping is carried out to the stress material of filling opening 14, forms source area and drain region；Wherein, when the transistor of formation is During NMOS, the stress material is SiC, and when the transistor of formation is PMOS, the stress material is SiGe.
Wherein more data about embedded stress transistor refer to Publication No. US2012/0228720A1 U.S. State's patent document.
But the continuous reduction of the characteristic size with semiconductor devices, the embedded stress crystal that prior art is formed Tube leakage current is high, and device performance is bad.
The content of the invention
The present invention solves the problems, such as to be to provide a kind of forming method of the embedded stress transistor of High-performance low leakage electricity.
To solve the above problems, the present invention provides a kind of forming method of transistor, including：There is provided with grid structure Semiconductor substrate；Opening is formed in the Semiconductor substrate of grid structure both sides；The first stressor layers are formed in the opening；It is right First stressor layers carry out ion implanting；Form the second stressor layers of the full opening of filling.
Optionally, when transistor to be formed is NMOS, the first stress layer material is SiC；When crystalline substance to be formed When body pipe is PMOS, the first stress layer material is SiGe.
Optionally, the first stressor layers include Seed Layer.
Optionally, when transistor to be formed is NMOS, seed layer materials are SiC in first stressor layers；When treating When the transistor of formation is PMOS, seed layer materials are SiGe in first stressor layers.
Optionally, the ion that the thickness of first stressor layers is suitable to avoid injecting during ion implantation technology punctures the grid The thickness of pole structure.
Optionally, the first stressor layers thickness is less than the thickness of the grid structure.
Optionally, the first stressor layers thickness is 15 nanometers -35 nanometers.
Optionally, the formation process of first stressor layers is extension, and epitaxy technique parameter is：Used reactant bag Include：SiH4、GeH4、HCl、CH4、CH3Cl、CH2Cl2、H2Or B2H6In one or more, or SiH2Cl2、GeH4、HCl、 CH4、CH3Cl、CH2Cl2、H2Or B2H6In one or more, epitaxial temperature be 450 degree Celsius to 700 degree Celsius, formation seed The Ge of layer mass percent is 15~30%.
Optionally, when transistor to be formed is PMOS, the process conditions of the ion implanting are the boron ion of injection Concentration is 1E18~1E19atom/cm3。
Optionally, the Doped ions concentration of second stressor layers is more than the Doped ions concentration of first stressor layers.
Optionally, when transistor to be formed is NMOS, the second stress layer material is SiC；When crystalline substance to be formed When body pipe is PMOS, the second stress layer material is SiGe.
Optionally, when transistor to be formed is PMOS, the mass percent for forming the second stress layer material Ge is 15 ~55%.
Optionally, when transistor to be formed is NMOS, the mass percent for forming the second stressor layers material C is 0.1 ~20%.
Optionally, the formation process of second stressor layers is to be with position doped epitaxial, technological parameter：Used reaction Thing includes：SiH4、GeH4、HCl、CH4、CH3Cl、CH2Cl2、H2Or B2H6In one or more, or SiH2Cl2、GeH4、 HCl、CH4、CH3Cl、CH2Cl2、H2Or B2H6In one or more, epitaxial temperature be 450 degree Celsius to 700 degree Celsius, same to position The boron ion concentration that doped epitaxial is formed is 5E19~1E21atom/cm3。
Optionally, second stressor layers include：Body layer and the coating positioned at body layer surface.
Compared with prior art, the present invention has advantages below：
Embodiments of the invention form the first stressor layers in the opening, then carry out first to first stressor layers Ion implanting, when overcoming prior art directly to source area and drain region progress source and drain injection, high energy ion enters to grid The defects of Semiconductor substrate under dielectric layer and gate dielectric layer.
In addition, first carrying out the first ion implanting to the first stressor layers, source and drain injection then is carried out to the second stressor layers, than existing There is technology directly to carry out source area and drain region source and drain injection to be easier to form ion doping concentration hangover pattern, reduce technique Difficulty, improve the process window that subsequently the second stressor layers are carried out with source and drain injection.
Further, first stressor layers can be Seed Layer, so as to while stating advantage in realization, increase Processing step.
Brief description of the drawings
Fig. 1-Fig. 3 is the process schematic that prior art forms embedded stress transistor；
Fig. 4 is the source area of embedded stress transistor and/or the perfect ion doping concentration distribution figure of drain region；
Fig. 5-Fig. 9 is the process schematic of the Transistor forming method of one embodiment of the invention.
Embodiment
With the further development of semiconductor technology, the continuous reduction of the characteristic size of semiconductor devices, in order to small The performance of transistor is improved under characteristic size, refer to Fig. 2, the opening of the stress material to be inserted of embedded stress transistor is deep It is more and more deeper to spend d, to play a part of further increasing transistor carrier mobility.
On the other hand, in order to reduce the leakage current of embedded stress transistor, the source area of embedded stress transistor and The ion doping concentration of drain region needs have hangover pattern（Doping Tail Profile）Distribution, refer to Fig. 4, Fig. 4 To be preferably embedded the ion doping concentration profile of the source area of formula stress transistor and/or drain region, abscissa is insertion The source area of formula stress transistor（Or drain region）Depth, ordinate be Doped ions concentration value, can understand from Fig. 4 See, in source area（Or drain region）Bottom position 20, hangover pattern is presented in the concentration values of Doped ions.
But realize that the ion doping of source area and drain region is dense in the embedded stress transistor of small characteristic size Degree distribution hangover pattern it is extremely difficult, with embedded stress transistor stress material to be inserted opening depth d increasingly It is deep, the source area of embedded stress transistor（Or drain region）Also increasingly deeper, the deeper source area of depth（Or drain region） Depth make it that forming ion doping concentration hangover pattern using ion implanting turns into extremely challenging, it is generally relatively difficult to achieve.
Further, due to embedded stress transistor performance requirement itself, source area and/or drain region ion doping are only The ion implanting of high-energy low dosage can be used（higher energy and low dose）, this be further exacerbated by being formed from The difficulty of sub- doping concentration hangover pattern.
It should also be noted that, because the gate electrode layer generally use material of transistor is polysilicon, prior art is usual The gate electrode layer of polysilicon can be doped to improve performance, specifically in the embedded stress transistor compared with large-feature-size In, the extra setting of grid structure will not also be stopped when realizing the ion implanting of source area and drain region, so as to source electrode Ion implanting also is carried out to gate electrode layer while the ion implanting of area and drain region.But with the progress of semiconductor technology, The continuous reduction of the characteristic size of semiconductor devices, cause opening depth d further intensification so that source area（Or drain region） Depth be more than embedded stress transistor grid structure thickness, the ion of source area and/or drain region ion doping note Enter in technique, the ion of high-energy is easier to puncture grid structure, the Semiconductor substrate entered under gate dielectric layer and gate dielectric layer It is interior, cause embedded stress transistor drain current to increase, embedded stress transistor nonfunctional is caused when serious.
Therefore, the application proposes a kind of forming method of the embedded stress transistor of High-performance low leakage electricity, pass through improvement Technique, on the basis of not additional process complexity, it can be easier to dense in source area and/or drain region formation ion doping Degree hangover pattern, and during being doped to source area and/or drain region, high energy ion will not puncture grid knot Structure, improve the reliability of the embedded stress transistor of formation so that the embedded stress transistor drain current of formation is low.
Specifically, it refer to Fig. 5, there is provided Semiconductor substrate 100, the Semiconductor substrate 100 are interior formed with isolation structure With the active area for being isolated structure isolation.
Specifically, the Semiconductor substrate 100 can be monocrystalline silicon, polysilicon or non-crystalline silicon；The substrate 100 can also It is silicon, germanium, GaAs or silicon Germanium compound；The Semiconductor substrate 100 can also have epitaxial layer or insulating barrier silicon-on；Institute The Semiconductor substrate 100 stated can also be other semi-conducting materials, will not enumerate here；The isolation structure can be with shallow ridges Road isolation structure（Shallow TrenchIsolation, STI）；The active area is used to be subsequently formed embedded stress crystal Pipe or other active devices.
Still with reference to figure 5 grid structure, the grid knot please be formed in the surfaces of active regions of the Semiconductor substrate 100 The thickness of structure be 50 nanometers to 60 nanometers, the grid structure include positioned at the Semiconductor substrate 100 gate dielectric layer 110, Gate electrode layer 120 positioned at the surface of gate dielectric layer 110；And positioned at the surface of Semiconductor substrate 100, the gate dielectric layer 110 and the side wall 130 of the both sides of gate electrode layer 120.
Specifically, the material of the gate dielectric layer 110 is the high k dielectric materials such as silicon oxynitride or hafnium oxide；The grid electricity The material of pole layer 120 is polysilicon, metal or other conductive materials.The side wall 130 can be the side wall knot of multiple-level stack Structure, the material of the side wall 130 can be silica, silicon nitride or silicon oxynitride, in one example, can be silica- The stacked structure of silicon nitride, or the stacked structure for oxide-nitride-oxide.The forming method of the grid structure Existing grid structure formation process is may be referred to, is formed using depositing operation and etching technics, repeated no more herein.
Fig. 6 is refer to, using etching technics, opening is formed in the Semiconductor substrate 100 of the grid structure both sides 140；
Stress material can be filled in 140 subsequent techniques of the opening, so as to improve the stress of the channel region of transistor.
The formation process of the opening 140 can be the etching work that dry etching, wet etching or dry method wet method combine Skill, the section shape of the opening 140 can be U-shaped, square shape, or Σ（sigma）Shape.
In the present embodiment, the formation process of opening 140 is done with Σ types exemplary illustrated：First with the grid structure For mask, the pre- opening that the Semiconductor substrate 100 forms inverted trapezoidal is etched using dry etch process（It is not shown）, then adopt Continued to etch the pre- opening with wet-etching technology, form the opening 140 of Σ shapes, Σ shapes opening can strengthen stress material Stress effect.
It should also be noted that, in order to meet the needs of technological development, the depth of the opening 140 can be than prior art Opening is further deepened, and specifically, 140 depth of the opening are 50 nanometers to 100 nanometers, for example, 55 nanometers, 65 nanometers, 75 receive Rice.
It should be noted that due to the depth of the intensification of the embodiment of the present invention opening 140, so that the opening 140 depth is more than the thickness of the grid structure.From analyzing before, if directly using the opening of prior art Filling fully stress material in 140, then carries out ion implanting to the stress material, and the ion of high-energy is easier to puncture grid knot Structure, enter in the Semiconductor substrate under gate dielectric layer and gate dielectric layer, cause embedded stress transistor drain current to increase, sternly Cause embedded stress transistor nonfunctional during weight.
Therefore, embodiments of the invention are not after the opening 140 for the thickness that depth is more than the grid structure is formed The filling fully stress material directly in the opening 140, refer to Fig. 7, and the first stressor layers are packed into the opening 140 150, the thickness of the first stressor layers 150 is less than the thickness of the grid structure.
Specifically, first, the opening is cleaned using pre-cleaning processes, removes the oxide layer and miscellaneous in opening Matter, the pre-cleaning processes are wet-cleaning.
Then, the first stressor layers 150 are formed in the opening 140 using epitaxy technique, first stressor layers 150 are thick Thickness of the degree less than the grid structure.
The effect of the first stressor layers 150 is formed in the opening is：Injected for subsequent ion to source area and/or drain electrode Area provides buffering, avoids the high energy ion of ion implanting from entering in the Semiconductor substrate under gate dielectric layer and gate dielectric layer； Carried in addition, hangover pattern can also be presented in first stressor layers 150 for the concentration value of source area and/or the Doped ions of drain region For larger regulation window.
The thickness of first stressor layers 150 is 15 nanometers -35 nanometers；When transistor to be formed is NMOS, described One stress layer material is SiC；When transistor to be formed is PMOS, the first stress layer material is SiGe.
In one embodiment, the first stressor layers 150 include Seed Layer.
In a preferred embodiment, first stressor layers 150 are Seed Layer（Seed layer）, Seed Layer is extension work The conventional cushion of skill, specifically act as：
First, subsequently in the source that formed, after drain region, high-temperature process can be carried out to activate Doped ions, in order to prevent due to Source, the Doped ions in drain region are diffused into Semiconductor substrate 100 and cause source, drain region resistivity to shift, first in the grid One layer of Seed Layer is formed on the bottom of the opening of pole structure both sides, and playing prevents the Doped ions in source, drain region to Semiconductor substrate 100 The effect of diffusion.
Second, can be because the lattice constant of extension body layer be much larger than half if directly forming extension body layer in open surfaces Conductor substrate 100（Silicon）Lattice constant, and cause lattice to mismatch, have influence between extension body layer and Semiconductor substrate 100 Lattice Matching, and may result in the stress release of extension body layer, and the Seed Layer for forming one layer of buffering reduces above-mentioned lack Sunken influence.
3rd, after opening is formed using etching technics, the surface of opening sustains damage, and Seed Layer can repair opening table The damage in face, and obtain smooth open surfaces.
And be in the present embodiment not need additional process as the effect of the first stressor layers from Seed Layer, can Reasonably above-mentioned purpose is realized using existing semiconductor process step.
Specifically, so that transistor to be formed is PMOS as an example, the seed layer materials are SiGe, the shape of the Seed Layer It is epitaxy technique into technique, specific process parameter is：Used reactant includes：SiH4、GeH4、HCl、CH4、CH3Cl、 CH2Cl2、H2Or B2H6In one or more, or SiH2Cl2、GeH4、HCl、CH4、CH3Cl、CH2Cl2、H2Or B2H6In one Kind is a variety of, and epitaxial temperature is 450 degree to 700 degree, and the mass percent for forming the Ge of Seed Layer is 15~30%.
In other embodiments, the first stressor layers 150 include Seed Layer and are additionally epitaxially formed on the seed layer outer Prolong layer, the ion that first stressor layers 150 only need thickness to be suitable to avoid injecting during ion implantation technology punctures the grid The thickness of structure, those skilled in the art can according to be actually needed the first stressor layers 150 of selection for single coating or Multilayer packed structures, specially illustrate herein, should not too limit the scope of protection of the invention.
Fig. 8 is refer to, to first stressor layers 150（It refer to Fig. 7）Carry out the first ion implanting.
So that transistor to be formed is PMOS as an example, the ion of the injection is boron ion, the process conditions of ion implanting It is 1E18~1E19atom/cm for the boron ion concentration of injection3。
It should be noted that forming the first stressor layers 150（It refer to Fig. 7）First stressor layers 150 are entered afterwards The ion implanting of row first, forms the first stressor layers 150 ' of injection ion, and the ion implanting can be simultaneously to grid structure Gate electrode layer is injected, and is had the following advantages：Because the thickness of the first stressor layers 150 is less than the thickness of the grid structure Degree, when carrying out ion implanting to first stressor layers 150, injection ion will not penetrate the gate electrode layer of grid structure, only It can rest in gate electrode layer, therefore, improve the reliability of transistor while reducing the resistance of gate electrode layer, improving The performance of transistor.
Further, avoid prior art thicker source area and/or drain region are carried out more difficult technology difficulty from Son injection, the present embodiment using first to the first stressor layers carry out ion implanting, subsequently source area and/or drain region are carried out from Son doping, so as to be easier to realize that the concentration value of source area and/or the Doped ions of drain region is presented using simple technique Trail pattern, adds the window of process adjustments.
Yet further, first stressor layers 150 of the present embodiment are Seed Layer, so as to state the same of advantage in realization When, processing step will not be increased.
Fig. 9 is refer to, after ion implantation technology, full second stressor layers 160 of filling in the opening 140.
Specifically, the formation process of second stressor layers 160 is extension, when transistor to be formed is NMOS, institute It is SiC to state the material of the second stressor layers 160；When transistor to be formed is PMOS, the material of the second stressor layers 160 is SiGe, the Doped ions concentration of second stressor layers 160 are more than the Doped ions concentration of first stressor layers 150.
Second stressor layers 160 are multilayer lamination structure, and in one embodiment, second stressor layers 160 include：Body Layer（Bulk Layer）With the coating positioned at body layer surface（Cap Layer）.
It is preferred that the formation process of second stressor layers 160 is to be with position doped epitaxial technique, specific process parameter： Used reactant includes：SiH4、GeH4、HCl、CH4、CH3Cl、CH2Cl2、H2Or B2H6In one or more, or SiH2Cl2、GeH4、HCl、CH4、CH3Cl、CH2Cl2、H2Or B2H6In one or more, epitaxial temperature be 450 degree to 700 degree, Formed Seed Layer Ge mass percent be 15~55%, with position doped epitaxial formed boron ion concentration for 5E19~ 1E21atom/cm3。
In another embodiment, when transistor to be formed is NMOS, the quality percentage of the second stressor layers material C is formed Than for 0.1~20%.
After the second stressor layers 160 are formed, source and drain ion implantation technology is carried out to the second stressor layers 160, afterwards, to first The stressor layers 160 of stressor layers 150 and second are annealed, and ion doping is formed in the first stressor layers 150 and the second stressor layers 160 Concentration hangover pattern.It should be noted that due to carrying out the first ion implanting work to first stressor layers 150 before Skill, therefore, in source and drain ion implantation technology, it is not necessary to which complicated and high difficulty ion implantation technology can is realized first Ion doping concentration hangover pattern is formed in the stressor layers 160 of stressor layers 150 and second.
Embodiments of the invention form the first stressor layers in the opening, and then first stressor layers 150 are carried out First ion implanting, when overcoming prior art directly to source area and drain region progress source and drain injection, high energy ion enters The defects of Semiconductor substrate under to gate dielectric layer and gate dielectric layer.
In addition, first carrying out the first ion implanting to the first stressor layers, source and drain injection then is carried out to the second stressor layers, than existing There is technology directly to carry out source area and drain region source and drain injection to be easier to form ion doping concentration hangover pattern, reduce technique Difficulty, improve the process window that subsequently the second stressor layers are carried out with source and drain injection.
Further, first stressor layers can be Seed Layer, so as to while stating advantage in realization, increase Processing step.
Although the present invention is disclosed as above with preferred embodiment, it is not for limiting the present invention, any this area Technical staff without departing from the spirit and scope of the present invention, may be by the methods and technical content of the disclosure above to this hair Bright technical scheme makes possible variation and modification, therefore, every content without departing from technical solution of the present invention, according to the present invention Any simple modifications, equivalents, and modifications made to above example of technical spirit, belong to technical solution of the present invention Protection domain.

Claims (15)

  1. A kind of 1. forming method of transistor, it is characterised in that including：
    Semiconductor substrate with grid structure is provided；
    Opening is formed in the Semiconductor substrate of grid structure both sides；
    The first stressor layers are formed in the opening, the thickness of first stressor layers is less than the thickness of the grid structure；
    Ion implanting is carried out simultaneously to first stressor layers and grid structure；
    Form the second stressor layers of the full opening of filling；
    The impurity ion in the second stressor layers, the Doped ions concentration of the second stressor layers are more than mixing for first stressor layers Heteroion concentration.
  2. 2. the forming method of transistor as claimed in claim 1, it is characterised in that when transistor to be formed is NMOS, institute It is SiC to state the first stress layer material；When transistor to be formed is PMOS, the first stress layer material is SiGe.
  3. 3. the forming method of transistor as claimed in claim 1, it is characterised in that the first stressor layers include Seed Layer.
  4. 4. the forming method of transistor as claimed in claim 2, it is characterised in that when transistor to be formed is NMOS, institute It is SiC to state seed layer materials in the first stressor layers；When transistor to be formed is PMOS, Seed Layer in first stressor layers Material is SiGe.
  5. 5. the forming method of transistor as claimed in claim 1, it is characterised in that the thickness of first stressor layers is suitable to avoid The ion injected during ion implantation technology punctures the thickness of the grid structure.
  6. 6. the forming method of transistor as claimed in claim 1, it is characterised in that the first stressor layers thickness is less than the grid The thickness of pole structure.
  7. 7. the forming method of transistor as claimed in claim 1, it is characterised in that the first stressor layers thickness be 15 nanometers- 35 nanometers.
  8. 8. the forming method of transistor as claimed in claim 1, it is characterised in that the formation process of first stressor layers is outer Prolong, epitaxy technique parameter is：Used reactant includes：SiH4、GeH4、HCl、CH4、CH3Cl、CH2Cl2、H2Or B2H6In One or more, or SiH2Cl2、GeH4、HCl、CH4、CH3Cl、CH2Cl2、H2Or B2H6In one or more, epitaxial temperature For 450 degree Celsius to 700 degree Celsius, the mass percent for forming the Ge of Seed Layer is 15~30%.
  9. 9. the forming method of transistor as claimed in claim 1, it is characterised in that when transistor to be formed is PMOS, institute The process conditions for stating ion implanting are that the boron ion concentration of injection is 1E18~1E19atom/cm3。
  10. 10. the forming method of transistor as claimed in claim 1, it is characterised in that the Doped ions of second stressor layers are dense Doped ions concentration of the degree more than first stressor layers.
  11. 11. the forming method of transistor as claimed in claim 1, it is characterised in that when transistor to be formed is NMOS, institute It is SiC to state the second stress layer material；When transistor to be formed is PMOS, the second stress layer material is SiGe.
  12. 12. the forming method of transistor as claimed in claim 11, it is characterised in that when transistor to be formed is PMOS, The mass percent for forming the second stress layer material Ge is 15~55%.
  13. 13. the forming method of transistor as claimed in claim 11, it is characterised in that when transistor to be formed is NMOS, The mass percent for forming the second stressor layers material C is 0.1~20%.
  14. 14. the forming method of transistor as claimed in claim 11, it is characterised in that the formation process of second stressor layers is With position doped epitaxial, technological parameter is：Used reactant includes：SiH4、GeH4、HCl、CH4、CH3Cl、CH2Cl2、H2Or B2H6In one or more, or SiH2Cl2、GeH4、HCl、CH4、CH3Cl、CH2Cl2、H2Or B2H6In one or more, Epitaxial temperature is 450 degree Celsius to 700 degree Celsius, and the boron ion concentration formed with position doped epitaxial is 5E19~1E21atom/ cm3。
  15. 15. the forming method of transistor as claimed in claim 1, it is characterised in that second stressor layers include：Body layer and position In the coating of body layer surface.
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