CN103811347A - Transistor forming method - Google Patents

Transistor forming method Download PDF

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CN103811347A
CN103811347A CN201210454774.2A CN201210454774A CN103811347A CN 103811347 A CN103811347 A CN 103811347A CN 201210454774 A CN201210454774 A CN 201210454774A CN 103811347 A CN103811347 A CN 103811347A
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stressor layers
transistor
transistorized formation
transistorized
formation method
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CN103811347B (en
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徐依协
金兰
涂火金
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Corp
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Semiconductor Manufacturing International Shanghai Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A transistor forming method comprises providing a semiconductor substrate with a gate structure; forming openings in the semiconductor substrate on the two sides of the gate structure; forming first stress layers in the openings; performing ion injection on the first stress layers; forming second stress layers filling the openings. Transistors formed through the method are good in performance.

Description

Transistorized formation method
Technical field
The present invention relates to field of semiconductor manufacture, particularly transistorized formation method.
Background technology
In very lagre scale integrated circuit (VLSIC), conventionally adopt strained silicon technology (Strained Silicon) to make to form on nmos pass transistor tensile stress, on PMOS transistor, form compression, thereby increase nmos pass transistor and the transistorized carrier mobility of PMOS, increase drive current, improved the response speed of circuit.Embedded stress transistor is one of focus of strained silicon technology application.
Fig. 1-3 are the transistorized process schematic diagram of embedded stress for prior art forms.
Please refer to Fig. 1, Semiconductor substrate 10 be provided, form grid structures on described Semiconductor substrate 10 surfaces, described grid structure comprise be positioned at described Semiconductor substrate 10 gate dielectric layer 11, be positioned at the gate electrode layer 12 on described gate dielectric layer surface; Both sides at semiconductor substrate surface, described gate dielectric layer 11 and gate electrode layer 12 form side wall 13;
Described grid structure can also comprise the hard mask layer (not shown) that is positioned at described gate electrode layer 12 surfaces;
Please refer to Fig. 2, take described side wall 13 and grid structure as mask, etching semiconductor substrate 10 forms opening 14, and described opening 14 degree of depth are d, described opening 14 is generally " Σ " shape, and described etching adopts the etching technics of wet etching, dry etching or Wet-dry method combination conventionally.The opening of described " Σ " is for follow-up filling stress material, and " Σ " shape opening can strengthen the stress effect of stress material.
Please refer to Fig. 3, please refer to Fig. 2 at described opening 14() in extension stress material until fill described opening 14, and the stress material of filling opening 14 is carried out to ion doping, form source area and drain region; Wherein, in the time that the transistor forming is NMOS, described stress material is SiC, and in the time that the transistor forming is PMOS, described stress material is SiGe.
Wherein manyly please refer to the U.S. patent documents that publication number is US2012/0228720A1 about the transistorized data of embedded stress.
But along with constantly reducing of the characteristic size of semiconductor device, the embedded stress transistor drain current that prior art forms is high, device performance is bad.
Summary of the invention
The problem that the present invention solves is to provide the transistorized formation method of embedded stress of the low electric leakage of a kind of high-performance.
For addressing the above problem, the invention provides a kind of transistorized formation method, comprising: the Semiconductor substrate with grid structure is provided; In the Semiconductor substrate of grid structure both sides, form opening; In described opening, form the first stressor layers; Described the first stressor layers is carried out to Implantation; Form second stressor layers of filling full described opening.
Optionally, in the time that transistor to be formed is NMOS, described the first stressor layers material is SiC; In the time that transistor to be formed is PMOS, described the first stressor layers material is SiGe.
Optionally, the first stressor layers comprises Seed Layer.
Optionally, in the time that transistor to be formed is NMOS, in described the first stressor layers, seed layer materials is SiC; In the time that transistor to be formed is PMOS, in described the first stressor layers, seed layer materials is SiGe.
Optionally, the ion injecting when the thickness of described the first stressor layers is suitable for avoiding ion implantation technology punctures the thickness of described grid structure.
Optionally, described the first stressor layers thickness is less than the thickness of described grid structure.
Optionally, described the first stressor layers thickness is 15 nanometer-35 nanometers.
Optionally, the formation technique of described the first stressor layers is extension, epitaxy technique parameter for: the reactant adopting comprises: SiH 4, GeH 4, HCl, CH 4, CH 3cl, CH 2cl 2, H 2or B 2h 6in one or more, or SiH 2cl 2, GeH 4, HCl, CH 4, CH 3cl, CH 2cl 2, H 2or B 2h 6in one or more, epitaxial temperature be 450 degree Celsius to 700 degree Celsius, the mass percent of Ge that forms Seed Layer is 15～30%.
Optionally, in the time that transistor to be formed is PMOS, the process conditions of described Implantation are that the boron ion concentration of injecting is 1E18～1E19atom/cm 3.
Optionally, the doping ion concentration of described the second stressor layers is greater than the doping ion concentration of described the first stressor layers.
Optionally, in the time that transistor to be formed is NMOS, described the second stressor layers material is SiC; In the time that transistor to be formed is PMOS, described the second stressor layers material is SiGe.
Optionally, in the time that transistor to be formed is PMOS, the mass percent that forms the second stressor layers material Ge is 15～55%.
Optionally, in the time that transistor to be formed is NMOS, the mass percent that forms the second stressor layers material C is 0.1～20%.
Optionally, the formation technique of described the second stressor layers is coordination doped epitaxial, technological parameter for: the reactant adopting comprises: SiH 4, GeH 4, HCl, CH 4, CH 3cl, CH 2cl 2, H 2or B 2h 6in one or more, or SiH 2cl 2, GeH 4, HCl, CH 4, CH 3cl, CH 2cl 2, H 2or B 2h 6in one or more, epitaxial temperature be Celsius 450 degree to Celsius 700 degree, coordination doped epitaxial form boron ion concentration be 5E19～1E21atom/cm 3.
Optionally, described the second stressor layers comprises: body layer and be positioned at the cover layer on body layer surface.
Compared with prior art, the present invention has the following advantages:
Embodiments of the invention form the first stressor layers in described opening, then described the first stressor layers is carried out to the first Implantation, overcome prior art and directly source has been carried out in source area and drain region and leak while injecting, high energy ion enters to the defect in the Semiconductor substrate under gate dielectric layer and gate dielectric layer.
In addition, first the first stressor layers is carried out to the first Implantation, then the second stressor layers is carried out to source and leak injection, source is carried out in source area and drain region leak to inject and more easily form ion doping concentration hangover pattern than prior art is direct, reduce technology difficulty, improved the follow-up process window that the second stressor layers is carried out to source leakage injection.
Further, described the first stressor layers can be Seed Layer, thereby when stating advantage in realization, can not increase processing step.
Accompanying drawing explanation
Fig. 1-Fig. 3 is that prior art forms the transistorized process schematic diagram of embedded stress;
Fig. 4 is the desirable ion doping concentration profile of the transistorized source area of embedded stress and/or drain region;
Fig. 5-Fig. 9 is the process schematic diagram of the Transistor forming method of one embodiment of the invention.
Embodiment
Along with further developing of semiconductor technology, constantly reducing of the characteristic size of semiconductor device, in order to improve transistorized performance under little characteristic size, please refer to Fig. 2, the opening depth d of embedded stress stress material transistorized to be inserted is more and more darker, to play the effect of further increase transistor carrier mobility.
On the other hand, in order to reduce the transistorized leakage current of embedded stress, the ion doping concentration of the transistorized source area of embedded stress and drain region need to have the distribution of hangover pattern (Doping Tail Profile), please refer to Fig. 4, Fig. 4 is the ion doping concentration profile of the transistorized source area of embedded stress and/or drain region preferably, abscissa is the degree of depth of the transistorized source area of embedded stress (or drain region), ordinate is the concentration value of doping ion, from Fig. 4, can know and see, the bottom position 20 of (or drain region) in source area, the concentration value of doping ion presents hangover pattern.
But, the ion doping CONCENTRATION DISTRIBUTION hangover pattern of realizing source area and drain region in the embedded stress transistor of little characteristic size is very difficult, along with the opening depth d of embedded stress stress material transistorized to be inserted is more and more darker, the degree of depth of the transistorized source area of embedded stress (or drain region) is also more and more darker, the degree of depth of darker source area (or drain region) makes to adopt Implantation to form ion doping concentration hangover pattern to be become and has challenge, more difficult realization conventionally.
Further, due to the performance requirement of embedded stress transistor own, source area and/or drain region ion doping can only adopt the Implantation (higher energy and low dose) of high-energy low dosage, and this has further aggravated to form the difficulty of ion doping concentration hangover pattern.
Also it should be noted that; be polysilicon because transistorized gate electrode layer adopts material conventionally; prior art can adulterate to improve performance to the gate electrode layer of polysilicon conventionally; specifically in compared with the embedded stress transistor of large-feature-size; in the time realizing the Implantation of source area and drain region, also can not stop extra setting of grid structure, thereby also gate electrode layer is carried out to Implantation in to the Implantation of source area and drain region.But, along with the progress of semiconductor technology, constantly reducing of the characteristic size of semiconductor device, cause the further intensification of opening depth d, make the degree of depth of source area (or drain region) be greater than the transistorized grid structure thickness of embedded stress, in the ion implantation technology of source area and/or drain region ion doping, high-octane ion more easily punctures grid structure, enter in the Semiconductor substrate under gate dielectric layer and gate dielectric layer, cause embedded stress transistor drain current to strengthen, when serious, cause embedded stress transistor nonfunctional.
For this reason, the application proposes the transistorized formation method of embedded stress of the low electric leakage of a kind of high-performance, by improving technique, additionally do not increasing on the basis of process complexity, can be more easily in source area and/or drain region form ion doping concentration hangover pattern, and in the process of being adulterated in source area and/or drain region, high energy ion can not puncture grid structure, improve the transistorized reliability of embedded stress forming, make the embedded stress transistor drain current of formation low.
Particularly, please refer to Fig. 5, Semiconductor substrate 100 is provided, in described Semiconductor substrate 100, be formed with isolation structure and be isolated the active area that structure is isolated.
Particularly, described Semiconductor substrate 100 can be monocrystalline silicon, polysilicon or amorphous silicon; Described substrate 100 can be also silicon, germanium, GaAs or silicon Germanium compound; This Semiconductor substrate 100 can also have epitaxial loayer or insulating barrier silicon-on; Described Semiconductor substrate 100 can also be other semi-conducting material, will not enumerate here; Described isolation structure can isolation structure of shallow trench (Shallow TrenchIsolation, STI); Described active area is for the embedded stress transistor of follow-up formation or other active devices.
Please still with reference to figure 5, surfaces of active regions in described Semiconductor substrate 100 forms grid structure, the thickness of described grid structure is 50 nanometer to 60 nanometers, described grid structure comprise be positioned at described Semiconductor substrate 100 gate dielectric layer 110, be positioned at the gate electrode layer 120 on described gate dielectric layer 110 surfaces; And be positioned at the side wall 130 of Semiconductor substrate 100 surfaces, described gate dielectric layer 110 and gate electrode layer 120 both sides.
Particularly, the material of described gate dielectric layer 110 is the contour k dielectric material of silicon oxynitride or hafnium oxide; The material of described gate electrode layer 120 is polysilicon, metal or other electric conducting materials.Described side wall 130 can be the sidewall structure of multiple-level stack, the material of described side wall 130 can be silica, silicon nitride or silicon oxynitride, in one example, can be the stacked structure of silica-silicon nitride, or be the stacked structure of silica-silicon-nitride and silicon oxide.The formation method of described grid structure can form technique with reference to existing grid structure, adopts depositing operation and etching technics to form, and here repeats no more.
Please refer to Fig. 6, adopt etching technics, the interior formation opening 140 of Semiconductor substrate 100 in described grid structure both sides;
In described opening 140 subsequent techniques, can fill stress material, thereby improve the stress of transistorized channel region.
The formation technique of described opening 140 can be the etching technics of dry etching, wet etching or the combination of dry method wet method, and the section shape of described opening 140 can be U shape, square shape, or Σ (sigma) shape.
In the present embodiment, with Σ type, the formation technique of opening 140 is done to exemplary illustrated: first take described grid structure as mask, described in employing dry etch process etching, Semiconductor substrate 100 forms the pre-opening (not shown) of inverted trapezoidal, then adopt wet-etching technology to continue pre-opening described in etching, the opening 140 that forms Σ shape, Σ shape opening can strengthen the stress effect of stress material.
Also it should be noted that, in order to meet the demand of technological development, the degree of depth of described opening 140 can further be deepened than the opening of prior art, and particularly, described opening 140 degree of depth are 50 nanometer to 100 nanometers, for example 55 nanometers, 65 nanometers, 75 nanometers.
Also it should be noted that, due to the degree of depth of the described opening 140 of intensification of the embodiment of the present invention, thereby make the degree of depth of described opening 140 be greater than the thickness of described grid structure.From analyzing before, if directly adopt the full stress material of the interior filling of described opening 140 of prior art, then described stress material is carried out to Implantation, high-octane ion more easily punctures grid structure, enter in the Semiconductor substrate under gate dielectric layer and gate dielectric layer, cause embedded stress transistor drain current to strengthen, when serious, cause embedded stress transistor nonfunctional.
For this reason, embodiments of the invention are greater than after the opening 140 of thickness of described grid structure in the formation degree of depth, be not directly at the full stress material of the interior filling of described opening 140, please refer to Fig. 7, in described opening 140, be packed into the first stressor layers 150, described the first stressor layers 150 thickness are less than the thickness of described grid structure.
Particularly, first, adopt prerinse technique to clean described opening, remove oxide layer and impurity in opening, described prerinse technique is wet-cleaned.
Then, adopt epitaxy technique in interior formation the first stressor layers 150 of described opening 140, described the first stressor layers 150 thickness are less than the thickness of described grid structure.
The effect that forms the first stressor layers 150 in described opening is: for follow-up Implantation provides buffering to source area and/or drain region, avoid the high energy ion of Implantation to enter in the Semiconductor substrate under gate dielectric layer and gate dielectric layer; In addition, described the first stressor layers 150 can also provide larger adjusting window for the concentration value of the doping ion of source area and/or drain region presents hangover pattern.
Described the first stressor layers 150 thickness are 15 nanometer-35 nanometers; In the time that transistor to be formed is NMOS, described the first stressor layers material is SiC; In the time that transistor to be formed is PMOS, described the first stressor layers material is SiGe.
In one embodiment, the first stressor layers 150 comprises Seed Layer.
In a preferred embodiment, described the first stressor layers 150 is Seed Layer (Seed layer), and Seed Layer is the resilient coating that epitaxy technique is conventional, specifically act as:
First, follow-up after formation source, drain region, can carry out high-temperature process to activate doping ion, in order to prevent causing that because the doping ion in source, drain region is diffused in Semiconductor substrate 100 source, drain region resistivity are offset, first form one deck Seed Layer in the bottom of the opening of described grid structure both sides, play the effect that the doping ion in the source of preventing, drain region spreads to Semiconductor substrate 100.
Second, if directly form extension body layer in open surfaces, can because the lattice constant of extension body layer much larger than Semiconductor substrate 100(silicon) lattice constant, and cause lattice not mate, have influence on the Lattice Matching between extension body layer and Semiconductor substrate 100, and may cause the Stress Release of extension body layer, and the Seed Layer of formation one deck buffering reduces the impact of above-mentioned defect.
The 3rd, adopting etching technics to form after opening, the surface of opening sustains damage, and Seed Layer can be repaired the damage of open surfaces, and obtains smooth open surfaces.
Be not need additionally to increase technique and select in the present embodiment Seed Layer as the effect of the first stressor layers, can reasonably utilize existing semiconductor technology step to realize above-mentioned purpose.
Particularly, be example take transistor to be formed as PMOS, described seed layer materials is SiGe, the formation technique of described Seed Layer is epitaxy technique, concrete technology parameter for: the reactant adopting comprises: SiH 4, GeH 4, HCl, CH 4, CH 3cl, CH 2cl 2, H 2or B 2h 6in one or more, or SiH 2cl 2, GeH 4, HCl, CH 4, CH 3cl, CH 2cl 2, H 2or B 2h 6in one or more, epitaxial temperature is 450 degree to 700 degree, the mass percent of Ge that forms Seed Layer is 15～30%.
In other embodiments; the epitaxial loayer that the first stressor layers 150 comprises Seed Layer and extra extension forms in Seed Layer; 150 ions that inject while needing thickness to be suitable for avoiding ion implantation technology of described the first stressor layers puncture the thickness of described grid structure; it is single coating or multilayer packed structures that those skilled in the art can select the first stressor layers 150 according to actual needs; specially illustrate at this, should too not limit the scope of protection of the invention.
Please refer to Fig. 8, described the first stressor layers 150(be please refer to Fig. 7) carry out the first Implantation.
Be example take transistor to be formed as PMOS, the ion of described injection is boron ion, and the process conditions of Implantation are that the boron ion concentration of injecting is 1E18～1E19atom/cm 3.
It should be noted that, in formation, the first stressor layers 150(please refer to Fig. 7) afterwards described the first stressor layers 150 is carried out to the first Implantation, form the first stressor layers 150 ' of injecting ion, described Implantation can inject the gate electrode layer of grid structure simultaneously, have advantages of as follows: because described the first stressor layers 150 thickness are less than the thickness of described grid structure, in the time that described the first stressor layers 150 is carried out to Implantation, inject the gate electrode layer that ion can not penetrate grid structure, only can rest in gate electrode layer, therefore, improving transistorized reliability and lowered simultaneously the resistance of gate electrode layer, improve transistorized performance.
Further, avoid prior art thicker source area and/or drain region to be carried out to the Implantation of more difficult technology difficulty, the present embodiment adopts and first the first stressor layers is carried out to Implantation, follow-up ion doping is being carried out in source area and/or drain region, thereby the concentration value that adopts simple technique can more easily realize the doping ion of source area and/or drain region presents hangover pattern, has increased the window of process adjustments.
Again further, described first stressor layers 150 of the present embodiment is Seed Layer, thereby when stating advantage in realization, can not increase processing step.
Please refer to Fig. 9, after ion implantation technology, in full the second stressor layers 160 of the interior filling of described opening 140.
Particularly, the formation technique of described the second stressor layers 160 is extension, and in the time that transistor to be formed is NMOS, described the second stressor layers 160 materials are SiC; In the time that transistor to be formed is PMOS, described the second stressor layers 160 materials are SiGe, and the doping ion concentration of described the second stressor layers 160 is greater than the doping ion concentration of described the first stressor layers 150.
Described the second stressor layers 160 is multiple-level stack structure, and in one embodiment, described the second stressor layers 160 comprises: body layer (Bulk Layer) and be positioned at the cover layer (Cap Layer) on body layer surface.
Preferably, the formation technique of described the second stressor layers 160 is coordination doped epitaxial technique, concrete technology parameter for: the reactant adopting comprises: SiH 4, GeH 4, HCl, CH 4, CH 3cl, CH 2cl 2, H 2or B 2h 6in one or more, or SiH 2cl 2, GeH 4, HCl, CH 4, CH 3cl, CH 2cl 2, H 2or B 2h 6in one or more, epitaxial temperature is 450 degree to 700 degree, the mass percent of Ge that forms Seed Layer is 15～55%, the boron ion concentration that coordination doped epitaxial forms is 5E19～1E21atom/cm 3.
In another embodiment, in the time that transistor to be formed is NMOS, the mass percent that forms the second stressor layers material C is 0.1～20%.
Forming after the second stressor layers 160, the second stressor layers 160 is carried out to source and leak ion implantation technology, afterwards, the first stressor layers 150 and the second stressor layers 160 are annealed, at the first stressor layers 150 and the interior formation ion doping of the second stressor layers 160 concentration hangover pattern.It should be noted that, owing to described the first stressor layers 150 being carried out to the first ion implantation technology before, therefore, leak in ion implantation technology in source, do not need complexity and the high ion implantation technology of difficulty just can realize at the first stressor layers 150 and the interior formation ion doping of the second stressor layers 160 concentration hangover pattern.
Embodiments of the invention form the first stressor layers in described opening, then described the first stressor layers 150 is carried out to the first Implantation, overcome prior art and directly source has been carried out in source area and drain region and leak while injecting, high energy ion enters to the defect in the Semiconductor substrate under gate dielectric layer and gate dielectric layer.
In addition, first the first stressor layers is carried out to the first Implantation, then the second stressor layers is carried out to source and leak injection, source is carried out in source area and drain region leak to inject and more easily form ion doping concentration hangover pattern than prior art is direct, reduce technology difficulty, improved the follow-up process window that the second stressor layers is carried out to source leakage injection.
Further, described the first stressor layers can be Seed Layer, thereby when stating advantage in realization, can not increase processing step.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible variation and modification to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.

Claims (15)

1. a transistorized formation method, is characterized in that, comprising:
The Semiconductor substrate with grid structure is provided;
In the Semiconductor substrate of grid structure both sides, form opening;
In described opening, form the first stressor layers;
Described the first stressor layers is carried out to Implantation;
Form second stressor layers of filling full described opening.
2. transistorized formation method as claimed in claim 1, is characterized in that, in the time that transistor to be formed is NMOS, described the first stressor layers material is SiC; In the time that transistor to be formed is PMOS, described the first stressor layers material is SiGe.
3. transistorized formation method as claimed in claim 1, is characterized in that, the first stressor layers comprises Seed Layer.
4. transistorized formation method as claimed in claim 2, is characterized in that, in the time that transistor to be formed is NMOS, in described the first stressor layers, seed layer materials is SiC; In the time that transistor to be formed is PMOS, in described the first stressor layers, seed layer materials is SiGe.
5. transistorized formation method as claimed in claim 1, is characterized in that, the ion that the thickness of described the first stressor layers injects while being suitable for avoiding ion implantation technology punctures the thickness of described grid structure.
6. transistorized formation method as claimed in claim 1, is characterized in that, described the first stressor layers thickness is less than the thickness of described grid structure.
7. transistorized formation method as claimed in claim 1, is characterized in that, described the first stressor layers thickness is 15 nanometer-35 nanometers.
8. transistorized formation method as claimed in claim 1, is characterized in that, the formation technique of described the first stressor layers is extension, epitaxy technique parameter for: the reactant adopting comprises: SiH 4, GeH 4, HCl, CH 4, CH 3cl, CH 2cl 2, H 2or B 2h 6in one or more, or SiH 2cl 2, GeH 4, HCl, CH 4, CH 3cl, CH 2cl 2, H 2or B 2h 6in one or more, epitaxial temperature be 450 degree Celsius to 700 degree Celsius, the mass percent of Ge that forms Seed Layer is 15～30%.
9. transistorized formation method as claimed in claim 1, is characterized in that, in the time that transistor to be formed is PMOS, the process conditions of described Implantation are that the boron ion concentration of injecting is 1E18～1E19atom/cm 3.
10. transistorized formation method as claimed in claim 1, is characterized in that, the doping ion concentration of described the second stressor layers is greater than the doping ion concentration of described the first stressor layers.
11. transistorized formation methods as claimed in claim 1, is characterized in that, in the time that transistor to be formed is NMOS, described the second stressor layers material is SiC; In the time that transistor to be formed is PMOS, described the second stressor layers material is SiGe.
12. transistorized formation methods as claimed in claim 11, is characterized in that, in the time that transistor to be formed is PMOS, the mass percent that forms the second stressor layers material Ge is 15～55%.
13. transistorized formation methods as claimed in claim 11, is characterized in that, in the time that transistor to be formed is NMOS, the mass percent that forms the second stressor layers material C is 0.1～20%.
14. transistorized formation methods as claimed in claim 11, is characterized in that, the formation technique of described the second stressor layers is coordination doped epitaxial, technological parameter for: the reactant adopting comprises: SiH 4, GeH 4, HCl, CH 4, CH 3cl, CH 2cl 2, H 2or B 2h 6in one or more, or SiH 2cl 2, GeH 4, HCl, CH 4, CH 3cl, CH 2cl 2, H 2or B 2h 6in one or more, epitaxial temperature be Celsius 450 degree to Celsius 700 degree, coordination doped epitaxial form boron ion concentration be 5E19～1E21atom/cm 3.
15. transistorized formation methods as claimed in claim 1, is characterized in that, described the second stressor layers comprises: body layer and be positioned at the cover layer on body layer surface.
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