CN105374750A - Transistor manufacturing method - Google Patents
Transistor manufacturing method Download PDFInfo
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- CN105374750A CN105374750A CN201410432202.3A CN201410432202A CN105374750A CN 105374750 A CN105374750 A CN 105374750A CN 201410432202 A CN201410432202 A CN 201410432202A CN 105374750 A CN105374750 A CN 105374750A
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Abstract
The invention provides a transistor manufacturing method, which comprises the steps of providing a semiconductor substrate, wherein the semiconductor substrate comprises a plurality of active regions and isolation structures formed between adjacent active regions; forming a gate structure on the semiconductor substrate, wherein the gate structure stretches across at least one active region; after forming the gate structure, implanting ions into the isolation structures by using ions that can deactivate the isolation structures; after the ion implantation step, forming grooves in the active regions on both sides of the gate structure; and forming stress gasket layers inside the grooves. By adopting the above method, the performances of formed transistors are improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of formation method of transistor.
Background technology
Prior art is along with the develop rapidly of semiconductor fabrication, and semiconductor device is in order to reach higher arithmetic speed, larger memory data output and more function, and semiconductor device is towards higher component density, higher integrated level future development.Therefore, the grid of complementary metal oxide semiconductors (CMOS) (ComplementaryMetalOxideSemiconductor, CMOS) transistor becomes more and more thinner and length becomes shorter than ever.But the change in size of grid can affect the electric property of semiconductor device, at present, performance of semiconductor device is improved mainly through controlling carrier mobility.A key element of this technology controls the stress in transistor channel.Such as suitable proof stress, improves charge carrier (electronics in n-channel transistor, the hole in p-channel transistor) mobility, just can improve drive current.Thus stress greatly can improve the performance of transistor.
Because silicon, germanium have identical lattice structure, i.e. " diamond " structure, at room temperature, the lattice constant of germanium is greater than the lattice constant of silicon, so in the source of PMOS transistor, drain region formed SiGe (SiGe), the compression that between silicon and germanium silicon, lattice mismatch is formed can be introduced, improve compression further, improve the performance of PMOS transistor.Correspondingly, in the source of nmos pass transistor, drain region forms carbon silicon (CSi) and can introduce the tension stress that lattice mismatch between silicon and carbon silicon formed, and improves tension stress further, improves the performance of nmos pass transistor.
But the transistor performance that existing formation method is formed is not good.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of transistor, to improve the performance of transistor.
For solving the problem, the invention provides a kind of formation method of transistor, comprising:
There is provided Semiconductor substrate, described Semiconductor substrate comprises multiple active area and the isolation structure between adjacent active regions;
Form grid structure on the semiconductor substrate, described grid structure is across active area described at least one;
After the described grid structure of formation, adopt and can carry out ion implantation by isolation structure described in the ion pair of isolation structure described in passivation;
After carrying out described ion implantation, in the active area of described grid structure both sides, form groove;
Process described groove, make described groove be Sigma's shape;
Stress liner layer is formed in the described groove in Sigma's shape.
Optionally, when carrying out ion implantation to described isolation structure, described ion implantation is carried out in the active area of described grid structure both sides simultaneously.
Optionally, the described ion that described ion implantation adopts be carbon ion and Nitrogen ion at least one of them.
Optionally, the described ion concentration range that described ion implantation adopts is 1E13/cm
2~ 1E15/cm
2.
Optionally, the described ion energy range that described ion implantation adopts is 1kV ~ 20kV.
Optionally, in described active area, the degree of depth of carrying out described ion implantation is less than the degree of depth of described groove.
Optionally, after the described groove of process, and before the described stress liner layer of formation, also comprise the step of carrying out clean.
Optionally, the cleaning solution that described clean adopts is diluted hydrofluoric acid.
Optionally, in described diluted hydrofluoric acid, the mass ratio of hydrogen fluoride and water is 1:50 ~ 1:500.
Optionally, described stress liner layer is germanium-silicon layer or silicon carbon layer.
Compared with prior art, technical scheme of the present invention has the following advantages:
In technical scheme of the present invention, the Semiconductor substrate comprising multiple active area and the isolation structure between adjacent active regions is provided, then grid structure is formed on the semiconductor substrate, after the described grid structure of formation, employing can carry out ion implantation by isolation structure described in the ion pair of isolation structure described in passivation, in the active area of described grid structure both sides, form groove again, finally in described groove, form stress liner layer.The ion injected in described ion implantation can with the atomic reaction of isolation structure, thus isolation structure described in passivation, reduce the loss effect of isolation structure in transistor formation process process, the side, channel region below grid structure (side, channel region refers to two end faces at channel region width two ends) is prevented to be exposed because isolation structure loss is too many, therefore, when follow-up formation stress epitaxial loayer, stress epitaxial loayer can not directly directly contact with side, channel region, prevent the Doped ions in stress epitaxial loayer from diffusing to channel region, ensure that the electric property of channel region is good, improve the performance of transistor.
Further, the described ion that described ion implantation adopts be carbon ion and Nitrogen ion at least one of them.Carbon ion and Nitrogen ion can form chemical bond with the atom in described isolation structure, thus the wear resistant ability of described isolation structure in the formation process process of transistor is significantly strengthened.
Accompanying drawing explanation
Fig. 1 to Fig. 4 is structural representation corresponding to each step of formation method of existing transistor;
Fig. 5 to Figure 11 is structural representation corresponding to each step of formation method of embodiment of the present invention transistor.
Embodiment
As described in background, the transistor performance of the formation method formation of existing transistor is not good.In the step process of the formation method of existing transistor, comprise formation structure as shown in Figures 1 to 4.
Please refer to Fig. 1, provide Semiconductor substrate 100, Semiconductor substrate 100 includes source region 101 and isolation structure 102.Form grid structure on a semiconductor substrate 100, described grid structure is positioned at below hard mask layer 130, and forms groove 103 in the active area 101 of described grid structure both sides.
Please refer to Fig. 2, the generalized section that Fig. 2 obtains along the cutting of A-A dotted line for structure shown in Fig. 1.Therefrom can see, the channel region in described grid structure protection active area 101, and define groove 103 in the active area 101 of described grid structure both sides.Described grid structure comprises gate dielectric layer 110 and grid 120, and the side of the side of described grid structure and hard mask layer 130 is covered by side wall 140.
But, in transistor formation process process, after formation groove 103, also to clean groove 103.In the process of cleaning groove 103, isolation structure 102 can be caused to be etched loss by cleaning solution.The most serious place of isolation structure 102 loss as dotted line circle 1011 in Fig. 1 shown in the part of surrounding.The active area 101 caused below side wall 140 is exposed by the loss of this part isolation structure 102, and causes groove 103 volume enlargement, and namely groove 103 extends to active area 101 and isolation structure 102 intersection.
Please refer to Fig. 3, after Fig. 3 shows and to clean groove 103 shown in Fig. 1, the cross-sectional view that structure shown in Fig. 1 obtains along the cutting of B-B dotted line, therefrom can see, be positioned at the groove 103a with volume enlargement of isolation structure 102 and active area 101 intersection, and come out by groove 103a in the active area 101 below side wall, namely at least part of side, channel region is exposed (two end faces that side, channel region refers to channel region width two ends).
Please refer to Fig. 4, after described cleaning, the groove 103a of the groove 103 shown in Fig. 2 and Fig. 3 is filled, form stress epitaxial loayer 150.Fig. 4 cuts the generalized section obtained after showing and filling stress epitaxial loayer 150 in the middle part of active area 101.Known, stress epitaxial loayer 150 directly can contact with side, channel region, and the ion of therefore follow-up doping in stress epitaxial loayer 150 can be diffused into channel region, causes and forms diffusion region 104.Due to the existence of diffusion region 104, cause the electric property of raceway groove to worsen (such as occurring short-channel effect), cause the hydraulic performance decline of transistor.
For this reason, the invention provides a kind of formation method of new transistor, described formation method after formation of the gate structure, and before groove is cleaned, employing can carry out ion implantation by isolation structure described in the ion pair of isolation structure described in passivation, thus the ion of isolation structure and injection is reacted, reduce cleaning solution to the loss effect of isolation structure, and then reduce cleaning solution to the etch rate of isolation structure, the channel region below grid structure is prevented to be exposed because isolation structure loss is too many, therefore, when follow-up formation stress epitaxial loayer, stress epitaxial loayer can not directly directly contact with side, channel region, prevent the Doped ions in stress epitaxial loayer from diffusing to channel region, ensure that the electric property of channel region is good, improve the performance of transistor.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
The embodiment of the present invention provides a kind of formation method of transistor, incorporated by reference to reference to figure 5 to Figure 10.
Please refer to Fig. 5, provide Semiconductor substrate 200, Semiconductor substrate 200 comprises multiple active area 201 and the isolation structure between adjacent active regions 201 202.
Semiconductor substrate 200 material can be silicon substrate, germanium silicon substrate, III-group Ⅴ element compound substrate, silicon carbide substrates or its laminated construction, or silicon on insulated substrate, or diamond substrate, or well known to a person skilled in the art that other semi-conducting materials are as substrate.
In the present embodiment, Semiconductor substrate 200 specifically adopts silicon substrate.
Isolation structure 202 can be fleet plough groove isolation structure (STI), or well known to a person skilled in the art other isolation structures for device isolation or active area isolation.
In the present embodiment, isolation structure 202 specifically adopts fleet plough groove isolation structure.
Please continue to refer to Fig. 5, form grid structure (incorporated by reference to reference to figure 6) on semiconductor substrate 200, grid structure is covered by hard mask layer 230, and grid structure both sides have side wall 240, and grid structure is across at least one active area 201.
In the present embodiment, incorporated by reference to reference to figure 6 (the tangent plane schematic diagram that Fig. 6 obtains along C-C Linear cut for structure shown in Fig. 5), the grid 220 that described grid structure comprises gate dielectric layer 210 and is positioned on gate dielectric layer 210.Above described grid structure, (that is above grid 210) also has hard mask layer 230.And side wall 240 is positioned at the side of described grid structure and hard mask layer 240.
In the present embodiment, the forming process of side wall 240 is specifically as follows: form spacer material layer and cover the side of described grid structure and the end face of hard mask layer 230 and side, and spacer material layer is covered to small part active area 201, return etching spacer material layer, be positioned at part on mask layer end face and active area 201 to remove spacer material layer, the spacer material layer that residue is positioned at the side of described grid structure and the side of mask layer retains becomes side wall 240.
Please refer to Fig. 7, adopt and ion 300 pairs of isolation structures 202 of passivation isolation structure 202 and active area 201 can carry out ion implantation.
Ion implantation first makes atom (or molecule) to be adulterated be ionized into ion, then accelerate to certain energy, makes it to be injected in the crystal of semi-conducting material, and then the annealed atom of doping that makes activates, and reaches the object of doping.Ion implantation device can be divided into three parts: 1 ion source; 2 bunch parts; 3 target chambers and terminal identity.Briefly ion source is exactly produce the place having the ion beam of energy.At ion source, filament powers up the hot electron of rear generation under the effect of electromagnetic field, clashes into dopant gas molecules or atom, make it to be ionized into ion after obtaining enough energy, then through extraction electrode sucking-off, becoming ion beam, then entering bunch part by focusing on.After ion enters bunch part, it will through multiple tracks process, to obtain required ion.Main process comprises 1. magnetic analyzers; 2. condenser lens; 3. faraday cup; 4. intensifier electrode; 5. electronics bath generator.Wherein, magnetic analyzer utilizes the difference of the ion of different charge-mass ratio movement locus under magnetic field by ion isolation, selects required foreign ion.Condenser lens is used for around line, producing electronics to keep not dispersing of line.
Usual injection ion will form hole or electronics at corresponding crystal structure, thus change the electrical property of corresponding semiconductor.But the object that the present embodiment enters ion implantation is not the electrical property in order to semiconductor, but the ion of injection and the silicon atom of isolation structure 202 are reacted form chemical bond, thus passivation isolation structure 202, make isolation structure 202 in the cleaning step process of transistor forming process, reduce cleaning solution to the etch rate of isolation structure 202, and then reduce the waste of isolation structure 202 in described cleaning process.
And the waste of isolation structure 202 in subsequent cleaning operation process is once reduce, follow-up filling epitaxial loayer in a groove would not extend to the place beyond groove, thus prevents the electric conductivity of channel region from changing.
In the present embodiment, the ion 300 that ion implantation adopts be carbon ion and Nitrogen ion at least one of them.Carbon ion and Nitrogen ion can form silicon-carbon bond or silicon-nitrogen key with the silicon atom in isolation structure 202, thus reduce the etch rate of follow-up cleaning solution to isolation structure 202, namely reduce the cleaning loss of described cleaning solution to isolation structure 202, and then side, channel region (table) face below grid structure that prevents is exposed.
In the present embodiment, the ion concentration range that ion implantation adopts can be 1E13/cm
2~ 1E15/cm
2if ion concentration is lower than 1E13/cm
2the silicon-carbon bond (silicon-nitrogen key) that atom then in isolation structure 202 and carbon ion (or Nitrogen ion) are formed very little; more weak to the passivation of isolation structure 202, be difficult to protective separation structure 202 in subsequent cleaning processes process and be not subject to too much loss.And if ion concentration is higher than 1E15/cm
2, easily cause corresponding ion to outdiffusion, affect the performance of transistor.
In the present embodiment, the ion energy range that ion implantation adopts is 1kV ~ 20kV.Ion energy needs to be greater than 1kV, to ensure that it enters corresponding active area 201 and isolation structure 202, but simultaneously, needs to control ion energy at below 20kV, to prevent the ion implantation degree of depth too large.
In the present embodiment, the degree of depth of described ion implantation is carried out (as the height of dotted line frame 203 enclosing region in Fig. 3 in active area 201, do not mark) be less than the degree of depth of the groove (please refer to Fig. 8) of follow-up formation, thus ensure the part of having carried out ion implantation in source region 201 can in successive recesses forming process, all etched removal, thus prevent injected ion from affecting the electrical property of follow-up source and drain areas.
It should be noted that, in the present embodiment, ion implantation is entered to active area 201 and isolation structure 202 simultaneously, can ensure that the part that isolation structure 202 and active area 201 have a common boundary obtains injecting sufficient ion, make the loss of follow-up isolation structure 202 less.But, in other embodiments of the invention, also can adopt and can carry out ion implantation separately by the ion pair isolation structure of isolation structure described in passivation, and described ion implantation not carried out to active area.Now, protective layer can be adopted to protect active area, then independent ion implantation is carried out to isolation structure.Further, in order to make isolation structure and active area intersection be injected preferably, protective layer can be made suitably to expose the active area part adjacent with isolation structure.
Please refer to Fig. 8, after carrying out ion implantation, in the active area 201 of grid structure both sides, form groove 204.
In the present embodiment, by forming groove 204 in active area 201, also the partial etching carrying out ion implantation in active area 201 being removed simultaneously, thus preventing above-mentioned ion implantation on the impact of active area 201 electric property.And mention above, consider the part removed in active area 201 carry out ion implantation completely just, in the process of therefore above-mentioned ion implantation, the degree of depth of ion implantation is less than the degree of depth of groove 204.
Please refer to Fig. 9, process groove 204, make groove 204 in Sigma's shape (Sigma shape), namely form the groove 205 in Sigma's shape.
In the present embodiment, the wet-etching technology process groove 204 of Tetramethylammonium hydroxide (TMAH) solution can be adopted.To silicon substrate, { 100} family of crystal planes is with { etch rate of 110} family of crystal planes is greater than the silicon substrate { etch rate of 111} family of crystal planes TMAH solution, therefore, groove 204 can be processed into the groove 205 in Sigma's shape, and the advantage such as TMAH solution has that crystal orientation selectivity is good, etch rate is high, nontoxic, pollution-free and convenient operation.Surfactant (surfactants) can also be added in TMAH solution.
Please continue to refer to Fig. 9, after process groove 204 forms the groove 205 in Sigma's shape, groove 205 is carried out to the step of clean.
In the present embodiment, described cleaning step can be removed in the groove 205 in Sigma's shape, the residue that etch step causes and impurity, thus the growth being beneficial to follow-up stress liner layer.The cleaning solution that described cleaning process adopts can be the hydrofluoric acid (DHF) of dilution, and in diluted hydrofluoric acid, the mass ratio of hydrogen fluoride and water is 1:50 ~ 1:500.The destruction of hydrofluoric acid to the silicon in isolation structure 202-oxygen key is larger, but it is less to the destruction of silicon-carbon bond and silicon-nitrogen key, therefore, after above-mentioned ion implantation is carried out to isolation structure 202, when adopting diluted hydrofluoric acid cleaning groove 205, the loss effect that isolation structure 202 is subject to reduces.
Owing to first having carried out above-mentioned ion implantation to isolation structure 202 in the present embodiment, therefore described cleaning step can be reduced to less than 30% to the etch rate of isolation structure 202, and therefore, the loss effect of described cleaning step to isolation structure 202 can be reduced to
below (and existing method causes the loss of isolation structure to exist usually
above), therefore, after described ion implantation, the side surface of active area 201 can not be exposed, and therefore the loss of isolation structure 202 does not affect the filling of follow-up stress liner layer substantially.
Please refer to Figure 10, in the groove 205 in fig .9 in Sigma's shape, form stress liner layer 250.
In the present embodiment, when forming PMOS transistor, stress liner layer 250 can be germanium-silicon layer, and when forming nmos pass transistor, stress liner layer 250 can be silicon carbon layer.The present embodiment is specifically described to form PMOS transistor.
In the present embodiment, the technique forming stress liner layer 250 can be selective epitaxial growth process, and described selective epitaxial growth process can adopt the one in low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum CVD (UHVCVD), rapid thermal CVD (RTCVD) and molecular beam epitaxy (MBE).
Concrete, the process forming stress liner layer 250 can be: in the groove in Sigma's shape, first form inculating crystal layer (seedlayer), described inculating crystal layer is thin layer monocrystalline silicon layer or the germanium silicon layer with low Ge content, then continue to form germanium-silicon layer (embedded germanium silicon layer) on described inculating crystal layer, namely form stress liner layer 250.
Please refer to Figure 11, Figure 11 is the vertical view of structure shown in Figure 10, in other words, and the generalized section that Figure 10 obtains along the cutting of D-D dotted line for structure shown in Figure 11.Therefrom can see, stress liner layer 250 is positioned at grid structure both sides, and isolation structure 202 is closely adjacent with stress liner layer 250.
Though do not show in figure, after formation stress liner layer, can also form cap layers (caplayer, not shown) on stress liner layer, described cap layers can be monocrystalline silicon layer or the germanium silicon layer with low Ge content.
The follow-up counter stress laying 250 that also comprises of the present embodiment carries out ion doping technique, thus obtain the stress liner layer of doping, and the source electrode finally obtained in described grid structure wherein side, in the drain electrode of grid structure opposite side, namely form complete PMOS transistor further.
In the formation method of the transistor that the present embodiment provides, the ion pair isolation structure 202 of passivation isolation structure 202 ion implantation can be carried out by adopting, thus loss in the cleaning step of isolation structure 202 in transistor formation process is reduced, therefore after described cleaning step, side, channel region can not be exposed, thus ensure that follow-up stress liner layer 250 does not directly contact side, channel region, prevent the conductive ion mixed by described ion doping in stress liner layer 250 from diffusing to channel region, thus improve the performance of transistor.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (10)
1. a formation method for transistor, is characterized in that, comprising:
There is provided Semiconductor substrate, described Semiconductor substrate comprises multiple active area and the isolation structure between adjacent active regions;
Form grid structure on the semiconductor substrate, described grid structure is across active area described at least one;
After the described grid structure of formation, adopt and can carry out ion implantation by isolation structure described in the ion pair of isolation structure described in passivation;
After carrying out described ion implantation, in the active area of described grid structure both sides, form groove;
Stress liner layer is formed in described groove.
2. the formation method of transistor as claimed in claim 1, is characterized in that, when carrying out ion implantation to described isolation structure, described ion implantation is carried out in the active area of described grid structure both sides simultaneously.
3. the formation method of transistor as claimed in claim 1 or 2, is characterized in that, the described ion that described ion implantation adopts be carbon ion and Nitrogen ion at least one of them.
4. the formation method of transistor as claimed in claim 1 or 2, is characterized in that, the described ion concentration range that described ion implantation adopts is 1E13/cm2 ~ 1E15/cm2.
5. the formation method of transistor as claimed in claim 1 or 2, is characterized in that, the described ion energy range that described ion implantation adopts is 1kV ~ 20kV.
6. the formation method of transistor as claimed in claim 2, it is characterized in that, in described active area, the degree of depth of carrying out described ion implantation is less than the degree of depth of described groove.
7. the formation method of the transistor as described in claim 1,2 or 6, is characterized in that, after the described groove of process, and before the described stress liner layer of formation, also comprises the step of carrying out clean.
8. the formation method of transistor as claimed in claim 7, is characterized in that, the cleaning solution that described clean adopts is diluted hydrofluoric acid.
9. the formation method of transistor as claimed in claim 8, it is characterized in that, in described diluted hydrofluoric acid, the mass ratio of hydrogen fluoride and water is 1:50 ~ 1:500.
10. the formation method of transistor as claimed in claim 1, it is characterized in that, described stress liner layer is germanium-silicon layer or silicon carbon layer.
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| US20030003644A1 (en) * | 2001-06-29 | 2003-01-02 | Toshiya Uenishi | Semiconductor integrated circuit device and method of fabricating the same |
| US6657223B1 (en) * | 2002-10-29 | 2003-12-02 | Advanced Micro Devices, Inc. | Strained silicon MOSFET having silicon source/drain regions and method for its fabrication |
| US20100181598A1 (en) * | 2009-01-21 | 2010-07-22 | Tsutomu Sato | Semiconductor device and method of manufacturing semiconducer device |
| CN103811347A (en) * | 2012-11-13 | 2014-05-21 | 中芯国际集成电路制造(上海)有限公司 | Transistor forming method |
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2014
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030003644A1 (en) * | 2001-06-29 | 2003-01-02 | Toshiya Uenishi | Semiconductor integrated circuit device and method of fabricating the same |
| US6657223B1 (en) * | 2002-10-29 | 2003-12-02 | Advanced Micro Devices, Inc. | Strained silicon MOSFET having silicon source/drain regions and method for its fabrication |
| US20100181598A1 (en) * | 2009-01-21 | 2010-07-22 | Tsutomu Sato | Semiconductor device and method of manufacturing semiconducer device |
| CN103811347A (en) * | 2012-11-13 | 2014-05-21 | 中芯国际集成电路制造(上海)有限公司 | Transistor forming method |
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