CN103715090B - Transistor and forming method thereof - Google Patents
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- CN103715090B CN103715090B CN201210378719.XA CN201210378719A CN103715090B CN 103715090 B CN103715090 B CN 103715090B CN 201210378719 A CN201210378719 A CN 201210378719A CN 103715090 B CN103715090 B CN 103715090B
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention provides a kind of transistor and forming method thereof.The forming method of the transistor includes：Gate structure is formed on a semiconductor substrate；It is exposing in gate structure, in the Semiconductor substrate of source/drain region position formed opening；Stress material is covered in the bottom of the opening and side wall, to form the first stressor layers doped with non-proliferation material；Continue to be filled the stress material to opening, to form the second stressor layers doped with source/drain region Doped ions.The transistor, including：Semiconductor substrate；Gate structure in the Semiconductor substrate；The opening being formed in the Semiconductor substrate that the gate structure exposes；The bottom of the opening and the first stressor layers of side wall are covered in, doped with non-proliferation material in first stressor layers；The second stressor layers being filled in the opening, second stressor layers are doped with source/drain region Doped ions.The present invention can reduce the leakage current of transistor.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of transistor and forming method thereof.
Background technology
Transistor is just being widely used at present as most basic semiconductor devices, with the component density of semiconductor devices
With the raising of integrated level, the grid size of transistor becomes shorter than ever；However, the grid size of transistor, which shortens, can make crystalline substance
Body pipe produces short-channel effect, and then produces leakage current, the final electric property for influencing semiconductor devices.At present, the prior art
Mainly by improving the stress of transistor channel region, to improve carrier mobility, and then the driving current of transistor is improved, reduced
Leakage current in transistor.
The method that the prior art improves the stress of transistor channel region is to form stressor layers in the source/drain region of transistor, its
In, the material of the stressor layers of PMOS transistor is SiGe（SiGe）, between silicon and SiGe because lattice mismatch formed compression, from
And improve the performance of PMOS transistor；The material of the stressor layers of nmos pass transistor is carborundum（SiC）, between silicon and carborundum because
The tension that lattice mismatch is formed, so as to improve the performance of nmos pass transistor.
The prior art has the cross-sectional view of the transistor forming process of stressor layers, as shown in Figure 1 to Figure 3, bag
Include：
Please refer to Fig.1, there is provided Semiconductor substrate 10, gate structure 11 is formed on 10 surface of Semiconductor substrate.It is described
Gate structure 11 includes：The gate dielectric layer 14 on 10 surface of Semiconductor substrate, the gate electrode layer on 14 surface of gate dielectric layer
15, and the side wall 16 on 10 surface of Semiconductor substrate of 15 both sides of the gate electrode layer.
Please refer to Fig.2, opening 12 is formed in the Semiconductor substrate 10 of 11 both sides of gate structure.The opening 12 is
Sigma（Σ, sigma）Shape, i.e., the side wall of described opening 12 and the surface of Semiconductor substrate 10 form Sigma's shape, described to open
Apex angle on 12 side walls of mouth extends into the Semiconductor substrate 10 of the lower section of gate structure 11.
Please refer to Fig.3, form stressor layers 13 in the opening 12, the material of the stressor layers 13 is SiGe or carbonization
Silicon, and ion doping is carried out to the stressor layers 13 to form source region and drain region.
However, the short-channel effect of the transistor formed with the prior art is obvious, there is larger leakage current.More tools
The transistor for having stressor layers refer to the U.S. patent documents of Publication No. US 2011256681A1.But the United States Patent (USP)
Also fail to solve above-mentioned technical problem.
The content of the invention
The present invention solves the problems, such as to be to provide a kind of transistor and forming method thereof, to reduce the leakage current of transistor.
To solve the above problems, the present invention provides a kind of forming method of transistor, including：Formed on a semiconductor substrate
Gate structure；It is exposing in gate structure, in the Semiconductor substrate of source/drain region position formed opening；In the opening
Stress material is covered in bottom and side wall, to form the first stressor layers doped with non-proliferation material；Continue to be filled out to opening
The stress material is filled, to form the second stressor layers doped with source/drain region Doped ions.
Correspondingly, the present invention also provides a kind of transistor, including：Semiconductor substrate；In the Semiconductor substrate
Gate structure；The opening being formed in the Semiconductor substrate that the gate structure exposes；It is covered in the bottom and side of the opening
First stressor layers of wall, doped with non-proliferation material in first stressor layers；The second stressor layers being filled in the opening,
Second stressor layers are doped with source/drain region Doped ions.
Compared with prior art, technical scheme has the following advantages：
In the forming method of transistor provided by the invention, the stressor layers are formed by technique twice, and are forming the
During one stressor layers, non-proliferation material is mixed in the first stressor layers, the non-proliferation material can prevent the diffusion of Doped ions,
The diffusion problem of Doped ions during so as to weaken transistor work in stressor layers, thereby reduces the leakage current of transistor；
In transistor provided by the invention, the non-proliferation material in the first stressor layers can effectively inhibit the second stressor layers
The diffusion of middle Doped ions, the Doped ions in the second stressor layers are difficult to diffuse to channel region, can prevent transistor drain current from increasing
The problem of big, reduce the short-channel effect of transistor.
Brief description of the drawings
Fig. 1 to Fig. 3 is the cross-sectional view of prior art Transistor forming method；
Fig. 4 to Fig. 8 is the cross-sectional view of one embodiment of Transistor forming method of the present invention.
Embodiment
Many details are elaborated in the following description in order to fully understand the present invention.But the present invention can be with
Much implement different from other manner described here, those skilled in the art can be in the situation without prejudice to intension of the present invention
Under do similar popularization, therefore the present invention is not limited to the specific embodiments disclosed below.
Secondly, the present invention is described in detail using schematic diagram, when the embodiment of the present invention is described in detail, for purposes of illustration only, institute
It is example to state schematic diagram, it should not limit the scope of protection of the invention herein.
In order to solve problem of the prior art, the present inventor is analyzed and has been ground to the transistor of the prior art
Study carefully, it is found that the Doped ions in source-drain area stressor layers are easily spread, so as to cause short-channel effect, improve transistor
Leakage current.
Correspondingly, the present invention provides a kind of forming method of transistor, the stressor layers are formed by technique twice, and
When forming the first stressor layers, in the first stressor layers mix non-proliferation material, the non-proliferation use can prevent doping from
The diffusion of son, so that the diffusion problem of Doped ions when weakening transistor work in stressor layers, thereby reduces transistor
Leakage current.
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, below in conjunction with the accompanying drawings to the present invention
Embodiment be described in detail.Fig. 4 to Fig. 8 shows the cross-section structure signal of one embodiment of Transistor forming method of the present invention
Figure.The present embodiment is illustrated by taking PMOS as an example, but the invention is not limited in this regard.
As shown in Figure 4, there is provided Semiconductor substrate 100, gate structure 101 is formed on 100 surface of Semiconductor substrate.
The Semiconductor substrate 100 is used for the technique platform of subsequent technique, and the stressor layers for being additionally operable to and being subsequently formed match
Close, tension or compression are formed based on lattice mismatch.In the present embodiment, the Semiconductor substrate 100 is silicon substrate, specifically
Ground, the Semiconductor substrate 100 is monocrystalline silicon or silicon-on-insulator, but the present invention does not do the material of Semiconductor substrate 100
Limitation.
In the present embodiment, the crystal face on 100 surface of Semiconductor substrate is（100）, make to be easy to subsequently through wet etching
The opening sidewalls of formation form Sigma's shape with 100 surface of Semiconductor substrate, but whether the present invention is Sigma's shape to opening
It is not limited, therefore correspondingly, the crystal face on 100 surface of Semiconductor substrate is not also limited.
Gate structure 101 is formed on 100 surface of Semiconductor substrate.Specifically, the gate structure 101 includes：Positioned at institute
The gate dielectric layer 103 on 100 surface of Semiconductor substrate is stated, the gate electrode layer 104, Yi Jiwei positioned at 103 surface of gate dielectric layer
Side wall 102 in 100 surface of Semiconductor substrate of 104 both sides of gate electrode layer.
The material of the gate electrode layer 104 is polysilicon or metal.
When the material of the gate electrode layer 104 is polysilicon, the material of the gate dielectric layer 103 can be silica,
Silicon nitride or silicon oxynitride；When the gate electrode layer 104 material for aluminium or copper when metal when, the gate dielectric layer 104 is
High K dielectric material, the high K dielectric material include：The dielectric material such as hafnium oxide or aluminium oxide.
The material of the side wall 102 is silica, the one or more in silicon nitride, silicon oxynitride.
Forming the method for gate structure 101, same as the prior art details are not described herein.
As shown in figure 5, gate structure 101 is exposing, is formed and opened in Semiconductor substrate 100 positioned at source/drain region position
Mouth 105.In the present embodiment, the side wall of the opening 105 forms Sigma with the surface of Semiconductor substrate 100（Σ, sigma）
Shape, the apex angle of the centre of Σ shapes opening 105 extend into the Semiconductor substrate 100 of the lower section of gate structure 101, make follow-up
Distance between the stressor layers formed in the opening 105 is smaller, then the stressor layers being subsequently formed put on gate structure 101
The stress of the channel region of lower section is larger, so that the performance for improving transistor improves.
It should be noted that before opening is formed, also mask layer is formed on 104 surface of gate electrode layer（Figure is not
Show）, the mask layer be used for formed during the dry etching and wet etching of opening, avoid etching process to the gate electrode
Layer 104 causes to damage；The mask layer is removed after subsequent technique forms stressor layers.Specifically, the material of the mask layer
Expect for one or more combinations in silicon nitride, titanium nitride, nitridation thallium, tungsten nitride, aluminium oxide.
In the present embodiment, the technique for forming opening 105 comprises the following steps：It is mask with the gate structure 101, adopts
Side wall first opening vertical with 100 surface of Semiconductor substrate is formed in the Semiconductor substrate 100 with being dry-etched in（Do not show
Go out）；After dry etching, using the first opening described in wet etching, make apex angle on first opening sidewalls to grid knot
Extension in the Semiconductor substrate 100 of the lower section of structure 101, forms the opening 105 of Sigma's shape.
The dry etching is anisotropic dry etching, etching gas can be for chlorine, hydrogen bromide or chlorine and
The mixed gas of hydrogen bromide.The wet etching is anisotropic wet etching, and the etching liquid is alkaline solution, such as：
Potassium hydroxide（KOH）, sodium hydroxide（NaOH）Deng.
Since the crystal face on 100 surface of Semiconductor substrate is（100）, and the anisotropic wet etching is vertical
It is very fast in the etch rate on 100 surface of Semiconductor substrate and direction parallel to 100 surface of Semiconductor substrate, and etching
Crystal face（111）When etch rate it is most slow so that it is described opening 105 shape become Sigma's shape.
It should be noted that the present invention is not limited the shape of opening 105, the formation process of opening 105 is not also done
Limitation, in other embodiments, the formation process of the opening 105 can be anisotropic dry etching, then the opening
105 side wall is vertical with semiconductor substrate surface, simplifies technique, cost-effective.
As shown in Figure 6 and Figure 7, stress material 106 is covered in the bottom of the opening 105 and side wall, to form doping
There are the first stressor layers 107 of non-proliferation material.
Specifically, in the present embodiment, the stress material 106 is SiGe, in the opening by way of epitaxial growth
The SiGe is covered in 105 bottom and side wall.
Doped ions are into Semiconductor substrate 100 in the second stressor layers that the non-proliferation material is used to prevent from being subsequently formed
Diffusion.In the present embodiment, Doped ions are boron in second stressor layers, and the non-proliferation material is carbon or nitrogen.At other
In embodiment, the Doped ions can also be phosphorus, and the non-proliferation material carbon or nitrogen are also possible to prevent the diffusion of phosphorus.
Non-proliferation material can be mixed during first stressor layers 107 are epitaxially-formed.Specifically, containing
The SiGe is epitaxially formed in the gaseous environment of carbon or nitrogen.If it should be noted that mixed into the first stressor layers 107 excessive
Non-proliferation material, then easily influence stressor layers and the size of stress be provided, and if mixed in the first stressor layers 107 nonproliferation
Dissipate the effect unobvious that material is too small, then prevents Doped ions from spreading.It is therefore preferred that mixed into first stressor layers 107
Miscellaneous carbon or the concentration of nitrogen are located in the range of 1E18 ~ 3E19 atoms/cubic centimetre.
Further, it is also possible to after by extensional mode deposition stress material, answered by way of ion implanting described
Incorporation non-proliferation material in dead-wood material, to form the first stressor layers 107.Specifically, the mode of epitaxial growth is first passed through described
Germanium-silicon layer is epitaxially formed in the bottom of opening 105 and side wall, the germanium-silicon layer is carried out by the ion implanting of carbon or nitrogen afterwards
Doping, to form the first stressor layers 107.Such as：Ion implanting carries out the germanium-silicon layer by carbon ion, wherein carbon ion is noted
The energy entered is located at 0.5K in the range of 2K electron volts, and dopant dose is located at the scope of 1E13 ~ 1E14 atoms/square centimeter
Interior, doping angle is located in the range of 0 ~ 40 °.Alternatively, by Nitrogen ion to the germanium-silicon layer carry out ion implanting, wherein nitrogen from
The energy of son injection is located at 0.5K in the range of 3K electron volts, and dopant dose is located at the model of 1E13 ~ 1E14 atoms/square centimeter
In enclosing, doping angle is located in the range of 0 ~ 40 °.
If the thickness of the first stressor layers 107 is excessive, the second stress layer thickness being subsequently formed is too small, one side second
The available stress of stressor layers is smaller, and the stress that on the other hand the second stressor layers provide is also more difficult to pass through the first blocked up stressor layers
107 and play a role to channel region.But if the thickness of the first stressor layers 107 is too small, it is nonproliferation in the first stressor layers 107
Scattered material can not effectively stop the Doped ions in the second stressor layers being subsequently formed, so that leakage current can not be reduced effectively.Cause
This preferably, the thickness of first stressor layers 107 is located in the range of 1 ~ 200 nanometer.
As shown in figure 8, continue to be filled the stress material to opening 105, with formed doped with source/drain region adulterate from
Second stressor layers 108 of son.
Form the material of second stressor layers 108 and the material identical of first stressor layers 107.The present embodiment treats shape
Into transistor be PMOS, the materials of second stressor layers 108 is still SiGe, and the Doped ions in the second stressor layers 108 are
Boron.
Material positioned at the second stressor layers 108 of source/drain region is SiGe, and the lattice constant of SiGe is more than partly leading for silicon materials
The lattice constant of body substrate 100.Second stressor layers 108 provide compression to Semiconductor substrate 100, specifically, positioned at grid knot
The Semiconductor substrate 100 of the lower section of structure 101 bears the compression of the second stressor layers 108 positioned at the source/drain region of its both sides.Namely
Say, the channel region of transistor affords compression, so as to improve the electron mobility of PMOS tube channel region, and then improves
The performance of PMOS.Simultaneously as the carbon or nitrogen in the first stressor layers 107 can be effectively inhibited and adulterated in the second stressor layers 108
The diffusion of ion boron, therefore the boron ion in the second stressor layers 108 is difficult to diffuse to channel region, prevents PMOS tube leakage current from increasing
The problem of, reduce the short-channel effect of PMOS tube.
It should be noted that if the doping concentration of boron is excessive in the second stressor layers 108, diffusion material can not be effectively
The diffusion of boron, so that leakage current is added, and if the doping concentration of boron is too small in the second stressor layers 108, influence PMOS works
Electric transmission when making in channel region.It is preferred that the doping concentration of boron can be located in second stressor layers 108
In the range of 1E19-1E21 atoms/cubic centimetre.
Specifically, SiGe can be filled into the opening by extensional mode, until SiGe is filled up after the opening
Boron ion injection is carried out to the SiGe, to form the second stressor layers 108.Formed doped with the second stressor layers 108 of boron ion
Source/drain region.It should be noted that the present invention is not restricted the formation process of the second stressor layers 108, in other embodiments,
The formation process of second stressor layers 108 can also be selective epitaxial depositing operation, and the technique of Doped ions is mixed for original position
General labourer's skill.
The forming method of transistor of the present invention, the surface deposition for being additionally included in the second stressor layers 108 are used to reduce contact electricity
The metal silicide of resistance（salicide）, on metal silicide surface form the processing step of interlayer dielectric layer etc..With existing skill
Art is identical, and details are not described herein.
Correspondingly, present invention also offers a kind of transistor, please continue to refer to Fig. 8, show that transistor one of the present invention is real
Apply the schematic diagram of example.It should be noted that transistor is still illustrated by taking PMOS tube as an example herein.
The transistor includes：Semiconductor substrate 100；Gate structure 101 in the Semiconductor substrate 100；Shape
Gate structure 101 described in Cheng Yu exposes, the opening in the Semiconductor substrate 100 of source/drain region position；It is covered in the opening
105 bottom and the first stressor layers 107 of side wall, doped with non-proliferation material in first stressor layers 107；It is filled in described
The second stressor layers 108 in opening 105, second stressor layers 108 are doped with source/drain region Doped ions.
The Semiconductor substrate 100 is used for the technique platform of subsequent technique, and the stressor layers for being additionally operable to and being subsequently formed match
Close, tension or compression are formed based on lattice mismatch.In the present embodiment, the Semiconductor substrate is silicon substrate.
The gate structure 101 includes：Gate dielectric layer 103 positioned at 100 surface of Semiconductor substrate, positioned at the grid
The gate electrode layer 104 on 103 surface of dielectric layer, and positioned at the side on 100 surface of Semiconductor substrate of 104 both sides of gate electrode layer
Wall 102.The gate structure 101 is same as the prior art, and details are not described herein.
In the present embodiment, the opening is Sigma's shape（Σ shapes）.Apex angle among the Σ shapes opening is to the grid
Extension in the Semiconductor substrate 100 of the lower section of structure 101, can be filled in the distance between stressor layers formed in the opening 105
It is smaller, make the stress that follow-up stressor layers put on the channel region of the lower section of gate structure 101 larger, so as to improve the performance of transistor
Improve.But the present invention is not limited the shape of opening.
In the present embodiment, the material of first stressor layers 107 is SiGe, is doped in first stressor layers 107
Non-proliferation material is carbon or nitrogen, and the carbon or nitrogen can play the role of suppressing boron or phosphorus diffusion of plasma.Preferably, first answer
In power layer 107, the concentration of carbon or nitrogen is located in the range of 1E18 ~ 3E19 atoms/cubic centimetre.First stressor layers 107
Thickness is located in the range of 1 ~ 200 nanometer.
The material identical of the material of second stressor layers 108 and the first stressor layers 107, is also SiGe.The present embodiment is brilliant
Body pipe is PMOS, and Doped ions are boron in second stressor layers 108, and in other embodiments, the Doped ions can be with
It is other kinds of p-type Doped ions.
In transistor provided by the invention, carbon or nitrogen in the first stressor layers 107 can effectively inhibit the second stressor layers
The diffusion of Doped ions boron in 108, therefore the boron ion in the second stressor layers 108 is difficult to diffuse to channel region, prevents PMOS tube
The problem of leakage current increases, reduces the short-channel effect of PMOS tube.
It should be noted that in the above-described embodiments, illustrated by taking PMOS tube as an example, but the present invention does not make this
Limitation, in other embodiments, the transistor can be with NMOS tube, and for NMOS tube, stressor layers can be carborundum
Etc. the less stress material of lattice constant, the silicon base of channel region（It is bigger than the lattice constant of carborundum）During with silicon carbide contact,
It can be stretched to stressor layers direction, so that the electron mobility of channel region is improved, in addition, for NMOS tube, Doped ions are
The diffusion material of phosphorus, carbon or nitrogen etc. can also play the role of suppressing phosphorus diffusion, so as to prevent the increase of transistor drain current.
Although the present invention is disclosed as above with preferred embodiment, it is not for limiting the present invention, any this area
Technical staff without departing from the spirit and scope of the present invention, may be by the methods and technical content of the disclosure above to this hair
Bright technical solution makes possible variation and modification, therefore, every content without departing from technical solution of the present invention, according to the present invention
Any simple modifications, equivalents, and modifications made to above example of technical spirit, belong to technical solution of the present invention
Protection domain.
Claims (17)
- A kind of 1. forming method of transistor, it is characterised in that including：Gate structure is formed on a semiconductor substrate；It is exposing in gate structure, in the Semiconductor substrate of source/drain region position formed opening；Stress material is covered in the bottom of the opening and side wall, to form the first stressor layers doped with non-proliferation material, The non-proliferation material is nitrogen, and first stressor layers are the SiGe doped with nitrogen；Continue to be filled the stress material to opening, to form the second stressor layers doped with source/drain region Doped ions.
- 2. the forming method of transistor as claimed in claim 1, it is characterised in that the source/drain region Doped ions for boron or Phosphorus.
- 3. the forming method of transistor as claimed in claim 1, it is characterised in that the step of forming the first stressor layers includes： First stressor layers are formed by extensional mode.
- 4. the forming method of transistor as claimed in claim 3, it is characterised in that forming the method for the first stressor layers includes： The SiGe is epitaxially formed in nitrogenous gaseous environment.
- 5. the forming method of transistor as claimed in claim 4, it is characterised in that the nitrogen adulterated into first stressor layers Concentration be located in the range of 1E18~3E19 atoms/cubic centimetre.
- 6. the forming method of transistor as claimed in claim 3, it is characterised in that forming the method for the first stressor layers includes： Germanium-silicon layer is epitaxially formed in the bottom of the opening and side wall, the ion implanting of nitrogen is carried out to the germanium-silicon layer afterwards, with shape Into the first stressor layers.
- 7. the forming method of transistor as claimed in claim 6, it is characterised in that carried out by Nitrogen ion to the germanium-silicon layer The energy of ion implanting, wherein N~+ implantation is located at 0.5K in the range of 3K electron volts, dopant dose be located at 1E13~ In the range of 1E14 atoms/square centimeter, doping angle is located in the range of 0~40 °.
- 8. the forming method of transistor as claimed in claim 1, it is characterised in that the step of forming the second stressor layers includes： Second stressor layers are formed by extensional mode.
- 9. the forming method of transistor as claimed in claim 8, it is characterised in that second stressor layers are doped with boron SiGe, forming the method for the second stressor layers includes：SiGe is filled into the opening by extensional mode, until SiGe fills up institute State and boron ion injection is carried out to the SiGe after being open, to form the second stressor layers.
- 10. the forming method of transistor as claimed in claim 1, it is characterised in that the opening is Sigma's shape.
- 11. the forming method of transistor as claimed in claim 10, it is characterised in that the semiconductor substrate materials are silicon, By the graphical Semiconductor substrate of the method for dry and wet etching, to form the opening of Sigma's shape.
- A kind of 12. transistor, it is characterised in that including：Semiconductor substrate；Gate structure in the Semiconductor substrate；It is formed at opening that the gate structure exposes, in the Semiconductor substrate of source/drain region position；It is covered in the bottom of the opening and the first stressor layers of side wall, doped with non-proliferation material in first stressor layers, The non-proliferation material is nitrogen, and first stressor layers are the SiGe of nitrating；The second stressor layers being filled in the opening, second stressor layers are doped with source/drain region Doped ions.
- 13. transistor as claimed in claim 12, it is characterised in that the source/drain region Doped ions are boron or phosphorus.
- 14. transistor as claimed in claim 12, it is characterised in that the concentration of nitrogen be located at 1E18~3E19 atoms/cube li In the range of rice.
- 15. transistor as claimed in claim 12, it is characterised in that second stressor layers are the SiGe of boron-doping.
- 16. transistor as claimed in claim 12, it is characterised in that the opening is the opening of Sigma's shape.
- 17. transistor as claimed in claim 12, it is characterised in that the Semiconductor substrate is silicon substrate.
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| CN104979291A (en) * | 2014-04-10 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device |
| CN105097437A (en) * | 2014-05-22 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Method for forming strain silicon layer, manufacturing method for PMOS device and semiconductor device |
| CN105575808B (en) * | 2014-10-09 | 2018-11-16 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor structure |
| CN105529268B (en) * | 2014-10-27 | 2019-01-22 | 中芯国际集成电路制造(上海)有限公司 | Transistor and forming method thereof |
| CN105633154B (en) * | 2014-11-26 | 2020-04-21 | 中芯国际集成电路制造(上海)有限公司 | Transistor and forming method thereof |
| CN107785422B (en) * | 2016-08-29 | 2021-07-13 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and manufacturing method thereof |
| CN109285769B (en) * | 2017-07-20 | 2021-07-09 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| CN108573874B (en) * | 2018-04-13 | 2020-10-02 | 上海华力集成电路制造有限公司 | Manufacturing method of NMOS with HKMG |
| CN111725067A (en) * | 2019-03-21 | 2020-09-29 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN112992680A (en) * | 2019-12-12 | 2021-06-18 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101925986A (en) * | 2008-01-25 | 2010-12-22 | 富士通半导体股份有限公司 | Semiconductor device and method for production thereof |
| CN102569082A (en) * | 2010-12-24 | 2012-07-11 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing embedded germanium-silicon strain PMOS (P-channel Metal Oxide Semiconductor) structure |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US7759199B2 (en) * | 2007-09-19 | 2010-07-20 | Asm America, Inc. | Stressor for engineered strain on channel |
| CN102709183B (en) * | 2011-03-28 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | The method being used for producing the semiconductor devices |
-
2012
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101925986A (en) * | 2008-01-25 | 2010-12-22 | 富士通半导体股份有限公司 | Semiconductor device and method for production thereof |
| CN102569082A (en) * | 2010-12-24 | 2012-07-11 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing embedded germanium-silicon strain PMOS (P-channel Metal Oxide Semiconductor) structure |
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