CN105448723B - Semiconductor devices and forming method thereof - Google Patents
Semiconductor devices and forming method thereof Download PDFInfo
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- CN105448723B CN105448723B CN201410418112.9A CN201410418112A CN105448723B CN 105448723 B CN105448723 B CN 105448723B CN 201410418112 A CN201410418112 A CN 201410418112A CN 105448723 B CN105448723 B CN 105448723B
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Abstract
A kind of semiconductor devices and forming method thereof, wherein the forming method of semiconductor devices includes: offer substrate, and substrate surface is formed with dummy gate structure；Doped region is formed in the substrate of dummy gate structure two sides；The interlayer dielectric layer for being covered in doped region surface and dummy gate structure surface is formed, and interlayer dielectric layer top surface is flushed with dummy gate structure top surface；The substrate of etching removal dummy gate structure and the segment thickness below dummy gate structure, forms groove in substrate；Channel stress layer is filled in the trench, and the material of the channel stress layer is insulating materials, and the channel stress layer top surface is lower than substrate surface；Intrinsic layer is formed in the channel stress layer surface, and the intrinsic layer fills the full groove；Gate structure is formed in the intrinsic layer surface.The present invention inhibits short-channel effect and Punchthrough problem, optimizes the electric property and reliability of semiconductor devices while improving semiconductor devices carrier mobility.
Description
Technical field
The present invention relates to field of semiconductor manufacture technology, in particular to a kind of semiconductor devices and forming method thereof.
Background technique
With the continuous development of semiconductor technology, carrier mobility enhancing technology obtains extensive research and application,
The carrier mobility for improving channel region is capable of increasing the driving current of semiconductor devices, improves the performance of device.
In existing semiconductor device fabrication process, since stress can change the energy gap and carrier mobility of silicon materials,
Therefore the performance that semiconductor devices is improved by stress becomes more and more common means.Specifically, it is answered by suitable control
Power can be improved carrier (electronics in NMOS device, the hole in PMOS device) mobility, and then improve driving current,
The performance of semiconductor devices is greatlyd improve with this.
Currently, using embedded germanium silicon (Embedded SiGe) technology, i.e., it is first in the region for needing to form source region and drain region
Germanium silicon material is formed, is then doped source region and the drain region to form PMOS device again；Forming the germanium silicon material is to draw
Enter the compression (Compressive Stress) that lattice mismatch is formed between silicon and germanium silicon (SiGe), to improve PMOS device
Performance.Using embedded carbon silicon (Embedded SiC) technology, i.e., carbon silicon is initially formed in the region for needing to form source region and drain region
Then material is doped source region and the drain region to form NMOS device again；Forming the carbon silicon materials is to introduce
The tensile stress (Tensile Stress) that lattice mismatch is formed between silicon and carbon silicon (SiC), to improve the performance of NMOS device.
But it finds in practical applications, the degree that the carrier mobility for the semiconductor devices that the prior art is formed improves
It is limited, it is insufficient for improving the demand of the speed of service of semiconductor devices, and there are drain-induced barrier reduction and leakage currents
The problems such as.
Summary of the invention
Problems solved by the invention is how to improve semiconductor devices carrier mobility, and reduce short-channel effect,
Optimize the electric property of semiconductor devices.
To solve the above problems, the present invention provides a kind of forming method of semiconductor devices, comprising: substrate is provided, it is described
Substrate surface is formed with dummy gate structure；Doped region is formed in the substrate of the dummy gate structure two sides；Formation is covered in institute
State the interlayer dielectric layer on doped region surface and dummy gate structure sidewall surfaces, and the interlayer dielectric layer top surface and pseudo- grid
Pole structural top surface flushes；Etching removes the lining of the dummy gate structure and the segment thickness below dummy gate structure
Bottom forms groove in the substrate；Channel stress layer is filled in the groove, and the material of the channel stress layer is insulation
Material, and the channel stress layer top surface is lower than substrate surface；Intrinsic layer, and institute are formed in the channel stress layer surface
It states intrinsic layer and fills the full groove；Gate structure is formed in the intrinsic layer surface.
Optionally, the shape of the groove is sigma shape.
Optionally, the processing step for forming the groove includes: to be carved after removing the dummy gate structure using dry method
The substrate of etching technique etching removal segment thickness forms pre- groove；Continue to etch institute along the pre- groove using wet-etching technology
Substrate is stated, forms groove in substrate.
Optionally, the side wall of the groove has to doped region the first apex angle outstanding, and the bottom of the groove has
To substrate bottom the second apex angle outstanding.
Optionally, the channel stress layer top surface is higher than first apex angle.
Optionally, the processing step for forming the channel stress layer includes: to form the channel stress for filling the full groove
Layer, and the channel stress layer top surface is higher than interlayer dielectric layer top surface；Removal is higher than interlayer dielectric layer top surface
Channel stress layer, until channel stress layer top surface flush with interlayer dielectric layer top surface；It is thick to be etched back to removal part
The channel stress layer of degree makes channel stress layer top surface lower than substrate surface.
Optionally, the material of the channel stress layer is silicon nitride.
Optionally, when the semiconductor devices of formation is NMOS device, the stress types of the channel stress layer are tensile stress；
When the semiconductor devices of formation is PMOS device, the stress types of the channel stress layer are compression.
Optionally, when the stress types of the channel stress layer are tensile stress, using plasma enhances chemical vapor deposition
Product technique forms the technological parameter of the channel stress layer are as follows: reaction gas includes silicon source and nitrogen source, wherein silicon source SiH4,
Nitrogen source is NH3, silicon source and nitrogen source gas flow ratio are 2 to 10, and reaction chamber temperature is 200 degree to 400 degree, reaction chamber chamber pressure
It is by force 300 millitorrs to 500 millitorrs, reaction chamber low frequency power is 150 watts to 500 watts.
Optionally, when the stress types of the channel stress layer are compression, using plasma enhances chemical vapor deposition
Product technique forms the technological parameter of the channel stress layer are as follows: reaction gas includes silicon source and nitrogen source, wherein silicon source SiH4,
Nitrogen source is NH3, silicon source and nitrogen source gas flow ratio are 0.2 to 2, and reaction chamber temperature is 250 degree to 400 degree, reaction chamber
Pressure is 400 millitorrs to 2000 millitorrs, and reaction chamber radio-frequency power is 20 watts to 500 watts.
Optionally, the material of the intrinsic layer is silicon or germanium.
Optionally, when the material of the intrinsic layer is silicon, technique that the intrinsic layer is formed using selective epitaxial process
Parameter are as follows: the technological parameter of the selective epitaxial process are as follows: reaction gas includes silicon source gas, H2And HCl, silicon source gas are
SiH4Or SiH2Cl2, wherein silicon source gas flow is 1sccm to 1000sccm, and HCl flow is 1sccm to 1000sccm, H2Stream
Amount is 100sccm to 50000sccm, and reaction chamber temperature is 400 degree to 800 degree, and chamber pressure is 1 support to 500 supports.
Optionally, the intrinsic layer with a thickness of the 1/6 to 1/2 of trench depth.
Optionally, it further comprises the steps of: and forms doping stressor layers in the doped region, and adulterate the stress types of stressor layers
Identical as the stress types of channel stress layer, the material for adulterating stressor layers is SiC, SiCP, SiGe or SiGeB.
The present invention also provides a kind of semiconductor devices, comprising: substrate；Groove in the substrate；Fill the ditch
The channel stress layer of slot, the material of the channel stress layer is insulating materials, and the channel stress layer top surface is lower than lining
Bottom surface；Positioned at the intrinsic layer of the channel stress layer surface, the intrinsic layer fills the full groove；Positioned at the intrinsic layer
The gate structure on surface；Doped region in the substrate of the gate structure two sides.
Optionally, the side wall of the groove has to doped region the first apex angle outstanding, and the bottom of the groove has
To substrate bottom the second apex angle outstanding, the channel stress layer top surface is higher than the first apex angle.
Optionally, the material of the channel stress layer is silicon nitride；When the semiconductor devices is NMOS device, the ditch
The stress types of road stressor layers are tensile stress；When the semiconductor devices is PMOS device, the stress class of the channel stress layer
Type is compression.
Optionally, the material of the intrinsic layer is silicon or germanium.
Optionally, the intrinsic layer with a thickness of the 1/6 to 1/2 of trench depth.
Optionally, it is formed with doping stressor layers in the doped region, and adulterates the stress types and channel stress of stressor layers
The stress types of layer are identical, and the material for adulterating stressor layers is SiC, SiCP, SiGe or SiGeB.
Compared with prior art, technical solution of the present invention has the advantage that
In the embodiment of the present invention, etching removes the lining of pseudo- grid structure and the segment thickness below dummy gate structure
Bottom forms groove in substrate；Channel stress layer is filled in the groove, and the channel stress layer applies stress to channel region
Effect, improves the carrier mobility of semiconductor devices, improves the speed of service of semiconductor devices.Also, due to channel stress
The material of layer is insulating materials, and the channel stress layer also acts as the effect for stopping adjacent doped region to diffuse into one another, and prevents source
The depletion region in drain region leans on excessively close, inhibits short-channel effect, prevents Punchthrough problem, improve the electric property of semiconductor devices
And reliability.
Further, the side wall of groove has to doped region the first apex angle outstanding, the bottom of groove in the embodiment of the present invention
With to substrate bottom the second apex angle outstanding, so that the volume of groove is larger；When filling channel stress layer in the trench, by
It is more in the larger channel stress layer for making filling of the volume of groove, to improve the stress that channel stress layer is applied to channel region
Effect improves semiconductor devices carrier mobility, improves the speed of service of semiconductor devices.
Further, the material of the intrinsic layer is silicon or germanium, so that carrier is in intrinsic layer and gate structure interface
Scattering is weaker, further increases the carrier mobility of semiconductor devices.
Further, the embodiment of the present invention forms doping stressor layers in doped region, and adulterates the stressor layers class of stressor layers
Type is identical as the stress types of channel stress layer.Specifically, formed semiconductor devices be PMOS device when, doping stressor layers to
Channel region applies compression；The stress types of channel stress layer are that (stress types of channel stress layer are compression for compression
Refer to: the stress types measured on length direction in the channel region being located above the channel stress layer are compression), then ditch
The internal stress types of road stressor layers itself are tensile stress, so that channel stress layer applies tensile stress to doping stressor layers, thus
Make to adulterate the compression increase that stressor layers apply to channel region；Meanwhile channel stress layer is answered to the application of channel region vertical direction
Power, and then make channel region length direction (i.e. carrier mobility direction) that there is compression；Therefore it is answered in channel stress layer and doping
Under the collective effect of power layer, the carrier mobility of semiconductor devices can be more effectively improved, the operation of semiconductor devices is improved
Speed.Likewise, the carrier mobility of semiconductor devices can also obtain effectively when the semiconductor devices formed is NMOS device
Raising.
The embodiment of the present invention also provides a kind of superior semiconductor devices of structural behaviour, comprising: substrate；Positioned at the substrate
Interior groove；The channel stress layer of the groove is filled, the material of the channel stress layer is insulating materials, and the channel is answered
Power layer top surface is lower than substrate surface；Positioned at the intrinsic layer of the channel stress layer surface, the intrinsic layer filling is full described
Groove；Positioned at the gate structure of the intrinsic layer surface；Doped region in the substrate of the gate structure two sides.Ditch of the present invention
Road stressor layers apply stress to channel region, improve the carrier mobility of semiconductor devices；Also, due to channel stress layer
Material be insulating materials, adjacent doped region phase counterdiffusion can be prevented, avoid the depletion layer of adjacent doped region from leaning on excessively close, suppression
Punchthrough problem processed and short-channel effect.
Further, if the thickness of intrinsic layer is excessively thin, the thickness of channel region is also very thin, be easy to cause the carrier number flowed through
Amount is few；If the thickness of intrinsic layer is blocked up, the thickness of channel stress layer is excessively thin, so that channel stress layer is answered to what channel region applied
Power effect is small.Therefore intrinsic layer described in the embodiment of the present invention with a thickness of the 1/6 to 1/2 of trench depth.
Detailed description of the invention
Fig. 1 is the flow diagram that an embodiment forms semiconductor devices；
Fig. 2 to Figure 12 be another embodiment of the present invention provides semiconductor devices forming process the schematic diagram of the section structure.
Specific embodiment
It can be seen from background technology that, the carrier mobility for the semiconductor devices that the prior art is formed improves limitation, and
The problems such as there are short-channel effects, Punchthrough.
To solve the above problems, the formation process for semiconductor devices is studied.The formation process of semiconductor devices
Include the following steps, please refer to Fig. 1: step S1, semiconductor substrate is provided, the semiconductor substrate surface is formed with grid knot
Structure；Step S2, the first ion implanting is carried out to the semiconductor substrate of the gate structure two sides, is formed lightly doped district (LDD)；Step
Rapid S3, the semiconductor substrate to the lightly doped district two sides close to channel region carry out the second ion implanting, form pocket region
(Pocket)；Step S4, side wall is formed in the gate structure two sides；Using the side wall as exposure mask, etching removal gate structure
The semiconductor substrate of two side portions thickness forms groove；Step S5, the stressor layers for filling the full groove are formed；To the grid
The stressor layers of pole structure two sides carry out third ion implanting, form heavily doped region.
However, the semiconductor devices operating rate that the above method is formed still is insufficient for being actually needed, channel region is carried
Flow the increased limitation of transport factor.
With the continuous reduction of dimensions of semiconductor devices, the gate dielectric layer thickness of gate structure constantly reduces, gate structure
The channel region length of lower section also reduces therewith, when channel region length is reduced to certain size, the semiconductor of above method formation
The short channel effect problem of device is more and more obvious, including induced barrier reduces, Punchthrough (Source to Drain
Punch Through), saturation current (Idsat) reduce the problems such as occur therewith.In order to improve, induced barrier is reduced and source and drain is worn
Logical problem, the method generallyd use are as follows: adjustment forms Implantation Energy, the injectant of the ion implanting of lightly doped district and pocket region
Amount and implant angle, so that the width of depletion region in semiconductor substrate close to channel region narrows, to improve semiconductor devices
Short-channel effect, reduce leakage current, increase the saturation current value of semiconductor devices.
For semiconductor devices forming method carry out further study show that, although having adjusted to form lightly doped district and mouth
Implantation Energy, implantation dosage and the implant angle of the ion implanting in bag area, the short-channel effect of the semiconductor devices of formation are asked
Topic still has.This is mainly as caused by following reason:
In order to improve the operating rate of semiconductor devices, increase the carrier mobility of channel region, the shape of semiconductor devices
Include step S4 and step S5 at method, form stressor layers in semiconductor substrate, the stressor layers apply pressure to channel region and answer
Power or tensile stress, to improve the carrier mobility of channel region.In step S4, the shape in the semiconductor substrate of gate structure two sides
It, also can be part or all of positioned at the lightly doped district of semiconductor substrate and pocket region during the formation groove at groove
Removal, so that the depletion region close to channel region broadens, thus the problem of exacerbating the short-channel effect of semiconductor devices, so that half
The induced barrier of conductor device reduces, leakage current increases, saturation current reduces.
Also, in the semiconductor devices that the above method is formed, the material of stressor layers is silicon carbide or SiGe, as carbon contains
The increase of amount or Ge content, stressor layers are continuously increased to the stress that channel region provides, and the carrier mobility of channel region is mentioned
It is high；However, after carbon content or Ge content increase to certain value, with the increase of carbon content or Ge content, stressor layers are to channel
The stress that area provides is not further added by, and the carrier mobility of channel region can not continue growing.What therefore the above method was formed partly leads
The ability that body device improves carrier mobility is limited, and the operating rate of semiconductor devices is insufficient for demand.
For this purpose, the present invention provides a kind of forming method of semiconductor devices, substrate is provided, the substrate surface is formed with puppet
Gate structure；Doped region is formed in the substrate of the dummy gate structure two sides；Formation be covered in the doped region surface and
The interlayer dielectric layer of dummy gate structure sidewall surfaces, and the interlayer dielectric layer top surface and dummy gate structure top surface are neat
It is flat；Etching removes the substrate of the dummy gate structure and the segment thickness below dummy gate structure, in the substrate
Form groove；Fill channel stress layer in the groove, the material of the channel stress layer is insulating materials, and the channel
Stressor layers top surface is lower than substrate surface；Intrinsic layer is formed in the channel stress layer surface, and intrinsic layer filling is full
The groove；Gate structure is formed in the intrinsic layer surface.The present invention is led to by forming channel stress layer below channel region
It crosses the channel stress layer and applies stress to channel region, and since the material of the channel stress layer is insulating materials,
Effectively inhibit short-channel effect and Punchthrough problem.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 2 to Figure 12 is the schematic diagram of the section structure for the semiconductor devices forming process that one embodiment of the invention provides.
Referring to FIG. 2, providing substrate 100,100 surface of substrate is formed with dummy gate structure.
The material of the substrate 100 is Si, Ge, SiGe or GaAs；The material of the substrate 100 may be monocrystalline silicon,
Silicon on polysilicon, amorphous silicon or insulator；100 surface of substrate can also be formed several epitaxial interface layers or stressor layers with
Improve the electric property of semiconductor devices.
In the present embodiment, the substrate 100 is silicon substrate, is formed with isolation structure 101 in the substrate 100, it is described every
It is fleet plough groove isolation structure from structure 101.
The dummy gate structure defines the position of the groove and gate structure that are subsequently formed.The dummy gate structure is
Single layer structure or multilayered structure.When the dummy gate structure is single layer structure, the material of the dummy gate structure is polysilicon.
In the present embodiment, the dummy gate structure is multilayered structure, comprising: the pseudo- gate dielectric layer positioned at 100 surface of substrate
102 and the pseudo- grid conductive layer 103 positioned at pseudo- 102 surface of gate dielectric layer, wherein the material of the puppet gate dielectric layer 102 is oxygen
The material of SiClx, the puppet grid conductive layer 103 is polysilicon；The dummy gate structure with a thickness of 500 angstroms to 5000 angstroms.
With continued reference to FIG. 2, forming side wall 104, and the side wall on 100 surface of substrate of the dummy gate structure two sides
The side wall of 104 closely dummy gate structures.
The effect of the side wall 104 are as follows: on the one hand, limit position and the width of the gate structure being subsequently formed；Another party
The side wall for the gate structure being subsequently formed is protected in face, and the side wall of gate structure is prevented to be damaged, and the side wall 104 can be with
As the subsequent exposure mask in substrate 100 when formation doped region.
The side wall 104 is single layer structure or multilayered structure, and the material of the side wall 104 is silica, silicon nitride or nitrogen
Silica.In the present embodiment, the side wall 104 is single layer structure, and the material of the side wall 104 is silicon nitride.
Referring to FIG. 3, the substrate 100 to the dummy gate structure two sides carries out ion implanting, the shape in the substrate 100
At lightly doped district 105.
The lightly doped district 105 can inhibit hot carrier's effect (HCE:Hot Carrier Effect).The present embodiment
Done so that the semiconductor devices of formation is NMOS device as an example it is exemplary illustrated, when the semiconductor devices of formation is NMOS device, institute
The injection ion for stating ion implanting is N-type ion, such as phosphorus, arsenic or antimony；As another embodiment, the semiconductor devices of formation is
When PMOS device, the injection ion of the ion implanting is P-type ion, such as boron, gallium or indium.
It can be comprising steps of being infused close to the lateral area of dummy gate structure by inclined ion in lightly doped district 105
Enter to be formed the area pocket (Pocket) (not shown), the injection ionic type is opposite with the Doped ions type of lightly doped district.It is logical
Cross lightly doped district 105 close to dummy gate structure lateral area formed pocket region, due to the pocket region Doped ions with
The Doped ions of lightly doped district 105 and the heavily doped region being subsequently formed are electrically on the contrary, make lightly doped district 105 close to channel region
Doped ions electrically on the contrary, the lightly doped district 105 is made to narrow close to the depletion region of channel region, delay to a certain extent
Short-channel effect is solved.
It further comprises the steps of: and the substrate 100 is made annealing treatment, activation injection ion, and repair ion implanting work
Skill is to lattice damage caused by substrate 100.
The present embodiment forms lightly doped district 105 after forming side wall 104 and can also formed in other embodiments
Before side wall, lightly doped district is formed in substrate.
Referring to FIG. 4, etching removal is located at the substrate 100 of dummy gate structure two side portions thickness, in the substrate 100
Form groove 106.
The present embodiment done so that the semiconductor devices that is formed is NMOS device as an example it is exemplary illustrated, due in U-shaped or rectangular
When groove 106 forms doping stressor layers, the tensile stress effect that the doping stressor layers apply to semiconductor device channel area is strong, because
The shape of groove 106 described in this present embodiment is U-shaped or rectangular.
The forming step of the groove 106 includes: with side wall 104 for exposure mask, using dry etch process, etching removal position
In the substrate 100 of the segment thickness of dummy gate structure two sides, groove 106 is formed in the substrate 100.
As one embodiment, the dry etch process is reactive ion etching, the reactive ion etching process
Technological parameter are as follows: etching gas includes HBr, He and O2, wherein HBr flow is 200sccm to 600sccm, and He flow is
200sccm to 600sccm, O2Flow be 2sccm to 200sccm, etching cavity pressure be 5 supports to 50 supports, bias be 50V extremely
300V。
As another embodiment, when the semiconductor devices of formation is PMOS transistor, the shape of groove is sigma (Σ)
Shape；When forming doping stressor layers in the groove of sigma shape, the pressure adulterating stressor layers and applying to semiconductor device channel area
Stress is strong.The forming step of the groove of sigma shape includes: using side wall as exposure mask, using dry etch process, etching removal
Positioned at the substrate of the segment thickness of dummy gate structure two sides, pre-groove is formed in the substrate；It is carved using wet-etching technology
The pre-groove is lost, forms the groove of sigma shape in substrate.
Referring to FIG. 5, forming the doping stressor layers 107 for filling the full groove 106.
In the present embodiment, done so that the semiconductor devices of formation is NMOS device as an example exemplary illustrated.Adulterate stressor layers 107
Material lattice constant be less than 100 interior raceway groove area material of substrate lattice constant, doping stressor layers 107 to channel region generate drawing
Stress (i.e. tensile stress) is stretched, so that the spacing of lattice of channel region becomes larger, mobility of the electronics in channel region becomes larger, to improve
Semiconductor devices carrier mobility improves the operating rate of semiconductor devices, optimizes the electric property of semiconductor devices.
The material of the doping stressor layers 107 is SiC or SiCP, forms the doping stress using selective epitaxial process
Layer 107.
In the present embodiment, the material of the doping stressor layers 107 is SiC, adulterates C atomic percent in 107 material of stressor layers
Than being 0.1% to 10%.
The technological parameter of the doping stressor layers 107 is formed using selective epitaxial process are as follows: reaction gas includes silicon source
Gas, carbon-source gas, HCl and H2, silicon source gas SiH4、SiH2Cl2Or Si2H6, carbon-source gas CH4Or C2H6, wherein silicon
Source gas flow be 5sccm to 500sccm, carbon-source gas flow be 5sccm to 500sccm, HCl flow be 1sccm extremely
300sccm, H2Flow is 1000sccm to 50000sccm, and reaction chamber pressure is 0.05 support to 50 supports, chamber temp 600
Degree is to 850 degree.
As another embodiment, when the semiconductor devices of formation is PMOS device, stressor layers 107 are adulterated to semiconductor device
Part channel region provides compression, and the lattice constant of doping 107 material of stressor layers is greater than the crystalline substance of 100 interior raceway groove area material of substrate
Lattice constant, so that the spacing of lattice of channel region reduces, hole becomes larger in the mobility of channel region, to improve semiconductor devices
Carrier mobility optimizes the electric property of semiconductor devices.When the semiconductor devices of formation is PMOS device, stress is adulterated
The material of layer 107 is SiGe or SiGeB, and adulterating Ge atomic percent in the material of stressor layers 107 is 10% to 55%.
As one embodiment, when the material for adulterating stressor layers 107 is SiGe, the technological parameter of selective epitaxial process
Are as follows: reaction gas includes silicon source gas, ge source gas, HCl and H2, silicon source gas SiH4、SiH2Cl2Or Si2H6, ge source gas
For GeH4, wherein silicon source gas flow is 5sccm to 500sccm, and ge source gas flow is 5sccm to 500sccm, HCl gas
Flow is 1sccm to 300sccm, H2Flow is 1000sccm to 50000sccm, and reaction chamber pressure is 0.05 support to 50 supports,
Chamber temp is 400 degree to 900 degree.
In the present embodiment, the material of the doping stressor layers 107 is SiC, after forming doping stressor layers 107, is also wrapped
It includes step: ion implanting being carried out to the substrate 100 of the dummy gate structure two sides, in the substrate 100 of dummy gate structure two sides
It is formed doped region (not shown).That is, being formed with doping stressor layers 107 in doped region in the present embodiment.
Referring to FIG. 6, forming the interlayer dielectric layer for being covered in the doped region surface and dummy gate structure sidewall surfaces
109, and 109 top surface of the interlayer dielectric layer is flushed with dummy gate structure top surface.
In the present embodiment, before forming the interlayer dielectric layer 109, further comprise the steps of: in doped region surface and puppet
Gate structure sidewall surface forms etching stop layer 108.
Etching technics is different to the etch rate of interlayer dielectric layer 109 with etching stop layer 108, therefore the etching stopping
Layer 108 plays the role of protecting doped region, avoids causing to etch to doped region.
The material of the interlayer dielectric layer 109 is silica, and the material of the etching stop layer 108 is silicon nitride or nitrogen oxygen
SiClx.
As a specific embodiment, the processing step packet of the etching stop layer 108 and interlayer dielectric layer 109 is formed
It includes: the etching stopping film for being covered in the doped region surface, dummy gate structure top surface and sidewall surfaces is formed, at the quarter
Erosion stops deielectric-coating between membrane surface forming layer, and the inter-level dielectric film top surface is higher than dummy gate structure top surface；
Using CMP process, removal is higher than the inter-level dielectric film and etching stopping film of dummy gate structure top surface,
Doped region surface and dummy gate structure sidewall surfaces form etching stop layer 108 and positioned at 108 surfaces of etching stop layer
Interlayer dielectric layer 109, and 109 top surface of the interlayer dielectric layer, 108 top surface of etching stop layer and dummy gate structure top
Portion surface flushes.
Referring to FIG. 7, etching removes the dummy gate structure, until exposing 100 surface of substrate.
Specifically, the removal pseudo- grid conductive layer 103 (please referring to Fig. 6) and pseudo- gate dielectric layer 102 (please referring to Fig. 6),
Until exposing 100 surface of substrate.
The dummy gate structure is removed using dry etch process etching.As a specific embodiment, the dry method is carved
The technological parameter of etching technique are as follows: reaction gas includes CF4、CHF3And Ar, CF4Flow is 50sccm to 100sccm, CHF3Flow
For 10sccm to 100sccm, Ar flow is 100sccm to 300sccm, and source power is 50 watts to 1000 watts, bias power 50
Watt to 250 watts, pressure is 50 millitorrs to 200 millitorrs, and chamber temp is 20 degree to 90 degree.
Referring to FIG. 8, etching removal is located at the substrate 100 of the segment thickness below the dummy gate structure, in the lining
Groove 110 is formed in bottom 100.
Extended meeting forms channel stress layer, the stress types and doping stressor layers of the channel stress layer in groove 110 afterwards
107 stress types are identical.
As a specific embodiment, when the semiconductor devices of formation is NMOS device, the stress types of channel stress layer
For tensile stress, (stress types of channel stress layer refer to for tensile stress: in the channel region being located above the channel stress layer
The stress types measured on length direction are tensile stress), the stress types of channel stress layer inside itself are compression, channel
Stressor layers generate compression to the doping stressor layers 107 of two sides, so that doping stressor layers 107 are further to the tensile stress of channel region
Enhancing；Also, in order to make channel stress layer provide enough compression to doping stressor layers 107, it should make to adulterate stressor layers 107
It is larger with the contact area of channel stress layer；Simultaneously as the stress types of itself are compression inside channel stress layer, it is described
Channel stress layer can generate compression to the vertical direction of channel region, so that channel region is stretched in the longitudinal direction, because
This described channel stress layer can provide tensile stress to channel region length direction, so that the tensile stress on channel region length direction obtains
It further increases.
The above analysis is it is found that if the compression of channel stress layer to the doping application of stressor layers 107 is bigger, to channel region
The compression that vertical direction generates is bigger, then the tensile stress obtained on channel region length direction is bigger, and then improves channel region and carry
Transport factor is flowed, the operating rate of semiconductor devices is improved.
Since the groove 110 of sigma (Σ) shape has the characteristics that make to doping first apex angle 200 outstanding of stressor layers 107
Stressor layers 107 must be adulterated and the contact surface of channel stress layer is larger；Also, for the dummy gate structure of same size,
The volume of the volume ratio square trench of the sigma shape groove 110 formed in substrate 100 below dummy gate structure is big, therefore
The content of the subsequent channel stress layer formed in groove 110 is more, so that channel stress layer is the tensile stress for promoting channel region
The beneficial effect played is stronger, and the compression that channel stress layer applies doping stressor layers 107 is bigger.Therefore the present embodiment
The shape of middle groove 110 is sigma shape, and 110 side wall of groove has to doped region the first apex angle 200 outstanding.
Meanwhile the bottom of groove 110 described in the present embodiment has to 100 bottom of substrate the second apex angle 300 outstanding, leads to
The etching stopping position for crossing control wet-etching technology, can be obtained bottom has to 100 bottom of substrate the second apex angle outstanding
300 groove 110.It is advantageous in that:
For the groove parallel with 200 surface of substrate compared to bottom surface, the volume for the groove 110 that the present embodiment is formed
Bigger, the amount of the subsequent channel stress layer filled in groove 110 is bigger, so that channel stress layer rises to channel region stress is improved
The effect arrived is more excellent, and keeps the thickness meet demand for the intrinsic layer being subsequently formed.
As another embodiment, when the semiconductor devices of formation is PMOS device, the stress types of channel stress layer are pressure
(stress types of channel stress layer refer to stress for compression: in the channel region length being located above the channel stress layer
The stress types measured on direction are compression), the stress types of channel stress layer inside itself are tensile stress, channel stress
Layer provides tensile stress to the doping stressor layers 107 of two sides, so that doping stressor layers 107 further increase the compression of channel region
By force；Simultaneously as the stress types of itself are tensile stress inside channel stress layer, the channel stress layer can hang down to channel region
Histogram is to tensile stress is generated, so that channel region is compressed in the longitudinal direction, therefore the channel stress layer can be to channel
Section length direction provides compression, so that the compression on channel region length direction is further increased, improves in channel region
Carrier mobility rate.
Likewise, being produced if the tensile stress of channel stress layer to the doping application of stressor layers 107 is bigger to channel region vertical direction
Raw tensile stress is bigger, then the compression obtained on channel region length direction is bigger, and then improves channel region carrier mobility,
Improve the operating rate of semiconductor devices.
Since the side wall of the groove 110 of sigma shape has the characteristics that doping first apex angle 200 outstanding of stressor layers 107,
So that doping stressor layers 107 and the contact surface of channel stress layer are larger；Also, relative to the dummy gate structure of same size
It says, the volume of the sigma shape groove 110 formed in the substrate 100 below dummy gate structure is bigger therefore subsequent in groove
The content of the channel stress layer formed in 110 is more, so that channel stress layer has for what the tensile stress of promotion channel region was played
Beneficial effect is stronger.Therefore when the semiconductor devices of formation is PMOS device, the shape of the groove 110 is sigma shape, described
The side wall of groove 110 has to doped region the first apex angle 200 outstanding, and the bottom of the groove 110 has to 100 bottom of substrate
Portion's the second apex angle 300 outstanding.
As a specific embodiment, the processing step for forming the groove 110 includes: to be etched using dry etch process
The substrate 100 of removal segment thickness forms pre- groove；Continue to etch the substrate along the pre- groove using wet-etching technology
100, groove 110 is formed in substrate 100.
As one embodiment, the dry etch process is plasma etch process, the plasma etching work
Skill is identical as the etching removal etching technics of dummy gate structure.
As one embodiment, the etch liquids of the wet etching are ammonium hydroxide (NH4OH) or tetramethylammonium hydroxide is molten
Liquid (TMAH).When due to using etch liquids as wet etching of ammonium hydroxide or tetramethyl ammonium hydroxide solution, wet etching pair
The etch rate that the etch rate of crystal face (100) compares crystal face (111) is big, therefore after the completion of wet-etching technology, forms Σ
The groove 110 of shape.
Referring to FIG. 9, forming the channel stress layer 111 for filling the full groove 110, and the channel stress layer 111 pushes up
Portion surface is higher than 109 top surface of interlayer dielectric layer；Removal is higher than the channel stress layer 111 of 109 top surface of interlayer dielectric layer,
Until 111 top surface of channel stress layer is flushed with 109 top surface of interlayer dielectric layer.
The channel stress layer 111 is used to play the stress for improving and being applied to channel region, to improve current-carrying in channel region
Transport factor improves the driveability of semiconductor devices.Also, in the present embodiment, the material of the channel stress layer 111 is exhausted
Edge material, therefore the channel stress layer 111 also acts as and prevents the ion between adjacent doped region from spreading, and effectively avoids short ditch
Channel effect and Punchthrough problem.
The material of the channel stress layer 111 is silicon nitride.When the semiconductor devices of formation is NMOS device, the channel
The stress types of stressor layers 111 are tensile stress, wherein the stress types of the channel stress layer 111 refer to for tensile stress: after
Continue has channel region above channel stress layer 111, and what is measured on 111 upper channels section length direction of channel stress layer answers
Power type is tensile stress, i.e., the stress types applied on 111 pairs of channel region length direction of channel stress layer are tensile stress；So ditch
The stress types of the internal measurement of road stressor layers 111 itself are compression.When the semiconductor devices of formation is PMOS device, the ditch
The stress types of road stressor layers 111 are compression, wherein the stress types of the channel stress layer 111 refer to for compression:
It is subsequent that there are channel region, the stress types measured in 111 upper channels area of channel stress floor above channel stress layer 111
For compression, i.e., the stress types that 111 pairs of channel region length direction of channel stress layer applies are compression；So channel stress layer
The stress types of 111 internal measurement itself are tensile stress.
Using plasma enhancing chemical vapor deposition process forms the channel stress layer 111.
When the stress types of the channel stress layer 111 are tensile stress, in the plasma enhanced chemical vapor deposition
Technique is formed in the technical process of channel stress layer 111, other than applying high frequency power source into reaction chamber, also to reaction chamber
Indoor application low frequency power source.High energy particle, the high energy grain are generated in reaction chamber in the environment of the low frequency power source
The channel stress layer 111 that son bombardment is formed, becomes channel stress layer 111 with compressibility.Also, the high energy particle may be used also
So that the atom or ions binding or rearrangement of channel stress layer 111, keep channel stress layer 111 finer and close, to make ditch
The stress types of 111 inside of road stressor layers itself are compression.Therefore the consistency of channel stress layer 111 is improved as far as possible, favorably
In the compression for improving 111 inside of channel stress layer itself, to improve on enough 111 pairs of channel region length directions of channel stress layer
The tensile stress size of application.
As one embodiment, when the stress types of the channel stress layer 111 are tensile stress, the plasma enhancing
The technological parameter of chemical vapor deposition process are as follows: reaction gas includes silicon source and nitrogen source, wherein silicon source SiH4, nitrogen source NH3,
Silicon source and nitrogen source gas flow ratio are 2 to 10, and reaction chamber temperature is 200 degree to 400 degree, and reaction chamber pressure is 300 millis
For support to 500 millitorrs, reaction chamber low frequency power is 150 watts to 500 watts.
When the stress types of the channel stress layer 111 are compression, in the plasma enhanced chemical vapor deposition
Technique is formed in the technical process of channel stress layer 111, and there are the processes that H atom is rejected, and is formed in channel stress layer 111 outstanding
It hangs key and cavity, the dangling bonds is cross-linked with each other, cavity is shunk and obtains the smallest surface.A series of this micro-variations is led
Causing the compactness of the channel stress layer 111 formed reduces, and becomes loose, and the Si- key hung and the N- of suspension bond are closed and formed
The Si-N key being stretched, interaction between atoms show as gravitation and are limited by reticular structure around, therefore channel stress
It is formed and is shunk in layer 111, so that the stress types of 111 inside of channel stress layer itself are tensile stress.The channel stress layer of formation
111 rejecting H atom abilities are stronger, and the Si-N linkage content that the Si- key hung and the N- of suspension bond conjunction are formed is more, to make
The tensile stress for obtaining 111 inside of channel stress layer itself is bigger, applies on 111 pairs of channel region length direction of channel stress layer to improve
The size of the compression added.
As a specific embodiment, embodiment is described when the stress types of the channel stress layer 111 are compression
The technological parameter of plasma enhanced chemical vapor deposition technique are as follows: reaction gas includes silicon source and nitrogen source, wherein silicon source is
SiH4, nitrogen source NH3, silicon source and nitrogen source gas flow ratio are 0.2 to 2, and reaction chamber temperature is 250 degree to 400 degree, reaction
Chamber pressure is 400 millitorrs to 2000 millitorrs, and reaction chamber radio-frequency power is 20 watts to 500 watts.
Referring to FIG. 10, being etched back to the channel stress layer 111 of removal segment thickness, and remaining channel stress layer 111 pushes up
Portion surface is lower than 100 surface of substrate.
As a specific embodiment, the technique that is etched back to is wet etching, and the etch liquids of the wet etching are
Phosphoric acid solution, wherein the mass percent of phosphoric acid is 65% to 85%, and solution temperature is 80 degree to 200 degree.
It is subsequent to form intrinsic layer on 111 surface of channel stress layer, and intrinsic layer top surface is flushed with 100 surface of substrate,
The intrinsic layer is the channel region of semiconductor devices.If the thickness of intrinsic layer is too small, the thickness of the channel region of semiconductor devices
It is too small, it will lead to the carrier quantity reduction for flowing through channel region, the operating current of semiconductor devices reduces, and influences semiconductor devices
Electric property；If the thickness of intrinsic layer is excessive, the amount for being etched back to the channel stress layer 111 of removal is excessive, causes remaining
The beneficial effect that channel stress layer 111 promotes channel region stress is affected.
For this purpose, in the present embodiment, after the completion of being etched back to technique, 111 top surface of channel stress layer to 100 surface of substrate
Distance be 110 depth of groove 1/6 to 1/2.
In order to improve the stress of channel stress layer 111 as far as possible, 111 top table of channel stress layer described in the present embodiment
Face is higher than the first apex angle 200 of groove 110.
The stress types for adulterating stressor layers 107 are identical as the stress types of channel stress layer 111；Related channel stress layer
111 can refer to foregoing description with 107 pairs of stressor layers mechanism for improving channel region stress of doping, and details are not described herein.
Figure 11 is please referred to, forms intrinsic layer 112 on 111 surface of channel stress layer, the intrinsic layer 112 fills full institute
It states groove 110 (please referring to Figure 10), and 112 top surface of the intrinsic layer is flushed with 100 surface of substrate.
The material of the intrinsic layer 112 is germanium, silicon or SiGe.The material of intrinsic layer 112 described in the present embodiment is silicon,
The intrinsic layer 112 with a thickness of the 1/6 to 1/2 of trench depth, the intrinsic layer 112 is formed using selective epitaxial process.
As a specific embodiment, the technological parameter of the selective epitaxial process are as follows: reaction gas includes silicon source gas
Body, H2And HCl, silicon source gas SiH4Or SiH2Cl2, wherein silicon source gas flow is 1sccm to 1000sccm, HCl flow
For 1sccm to 1000sccm, H2Flow is 100sccm to 50000sccm, and reaction chamber temperature is 400 degree to 800 degree, chamber
Pressure is 1 support to 500 supports.
It is the advantages of 111 surface of channel stress layer forms intrinsic layer 112: firstly, 112 conduct of the intrinsic layer
The mobility of the channel region of semiconductor devices, electronics or hole in the intrinsic layer 112 is higher；Secondly, rear extended meeting is intrinsic
112 surface of layer form gate dielectric layer, and the material of intrinsic layer 112 is silicon, and carrier (electronics or hole) is situated between in intrinsic layer 112 and grid
The carrier scattering that the interface of matter layer occurs is weak, and scattering and the channel region carrier mobility of carrier are inversely proportional, therefore, this
In embodiment, mobility of the carrier in channel region is high, so that the carrier for further increasing semiconductor device channel area moves
Shifting rate improves the speed of service of semiconductor devices.
As a specific embodiment, the intrinsic layer 112 with a thickness of 50 angstroms to 200 angstroms.
Figure 12 is please referred to, forms gate structure on 112 surface of intrinsic layer, the gate structure includes being located at intrinsic layer
The gate dielectric layer 113 on 112 surfaces and grid conductive layer 114 positioned at 113 surface of gate dielectric layer.
The material of the gate dielectric layer 113 is that (high K medium material refers to relative dielectric constant for silica or high K medium material
Greater than the dielectric material of 3.9 (relative dielectric constants of silica)).The high K medium material is HfO2、HfSiO、HfSiON、
HfTaO、HfTiO、HfZrO、ZrO2Or Al2O3。
The material of the grid conductive layer 114 is polysilicon or conductive metal.The conductive metal be Al, Cu, Ag, Au, Pt,
One of Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN or WSi or a variety of.
In the present embodiment, the material of the gate dielectric layer 113 is silica, and the material of the grid conductive layer 114 is polycrystalline
Silicon.
Correspondingly, the present embodiment also provides a kind of semiconductor devices, Figure 12 is please referred to, the semiconductor devices includes:
Substrate 100；
Groove in the substrate 100；
The channel stress layer 111 of the groove is filled, the material of the channel stress layer 111 is insulating materials, and described
111 top surface of channel stress layer is lower than 100 surface of substrate；
Intrinsic layer 112 positioned at 111 surface of channel stress layer, the intrinsic layer 112 fill the full groove；
Gate structure (not indicating) positioned at 112 surface of intrinsic layer；
Doped region (not shown) in gate structure two sides substrate 100.
The material of the substrate 100 is silicon, germanium, SiGe or GaAs, can also be formed with isolation in the substrate 100
Structure 101.
The gate structure includes: positioned at the gate dielectric layer 113 on 112 surface of intrinsic layer and positioned at 113 table of gate dielectric layer
The grid conductive layer 114 in face.The material of the gate dielectric layer 1113 be silica or high K medium material, the grid conductive layer 114
Material is polysilicon or metal material.
Further include: the side wall 104 positioned at 100 surface of substrate, and the closely gate structure sidewall table of the side wall 104
Face；Lightly doped district 105 in gate structure two sides substrate 100.
The doping type of the doped region is that n-type doping or p-type are adulterated.Specifically, the semiconductor devices is NMOS device
When part, the doping type of the doped region is n-type doping；When the semiconductor devices is PMOS device, the doped region is mixed
Miscellany type is p-type doping.
The shape of the groove is sigma shape, and the side wall of the groove has to doped region the first apex angle 200 outstanding,
And the bottom of the groove has to 100 bottom of substrate the second apex angle 300 outstanding, so that the capacity of groove is larger, so that
The amount for the channel stress layer 111 filled in groove is more, to increase the beneficial of 111 pairs of channel stress layer increase channel region stress
It influences.
The material of the channel stress layer 111 is silicon nitride；When the semiconductor devices is NMOS device, the channel is answered
The stress types of power layer 111 are tensile stress, and the stress types of the channel stress layer 111 refer to for tensile stress: by described
The influence of channel stress layer 111, the stress types on the channel region length direction above channel stress layer 111 are to open to answer
Power；And the stress types of channel stress layer 111 inside itself are compression.It is described when the semiconductor devices is PMOS device
The stress types of channel stress layer 111 are compression, and the stress types of the channel stress layer 111 refer to for compression: by
To the influence of the channel stress layer 111, the stress types on the channel region length direction above channel stress layer 111 are
Compression；And the stress types of channel stress layer 111 inside itself are tensile stress.
Since the material of channel stress layer 111 is insulating materials, the Doped ions of adjacent doped region can be prevented mutual
Infiltration inhibits short-channel effect, prevents semiconductor devices from source and drain punchthrough issues occur.
In the present embodiment, the semiconductor devices further include: be formed with doping stressor layers 107 in the doped region, and mix
The stress types of miscellaneous stressor layers 107 are identical as the stress types of channel stress layer 111, doping stressor layers 107 material be SiC,
SiCP, SiGe or SiGeB.
As one embodiment, the semiconductor devices is NMOS device, and the stress types of doping stressor layers 107 are to open to answer
Power, the material of doping stressor layers 107 are SiC or SiCP, and the stress types of channel stress layer 111 are tensile stress.Adulterate stressor layers
107 apply tensile stress to channel region, and channel area lattice spacing is made to become larger.The stress types of channel stress layer 111 are tensile stress, that
The internal stress types compression of channel stress layer 111 itself, channel stress layer 111 apply pressure to doping stressor layers 107 and answer
Power, so that doping stressor layers 107 are further enhanced to the tensile stress that channel region applies.Also, channel stress layer 111 is to ditch
Road area vertical direction applies compression, so that channel region obtains tensile stress in length direction (carrier mobility direction), thus into
One step improves the tensile stress on channel region length direction, further increases semiconductor devices carrier mobility, optimizes semiconductor
The electric property of device, and effectively prevent short channel effect problem and Punchthrough problem.
As another embodiment, the semiconductor devices is PMOS device, and the stress types of doping stressor layers 107 are that pressure is answered
Power, the material of doping stressor layers 107 are SiGe or SiGeB, and the stress types of channel stress layer 111 are compression.Adulterate stress
Layer 107 applies compression to channel region, so that channel area lattice spacing is shunk.The stress class of 111 inside of channel stress layer itself
Type is tensile stress, and channel stress layer 111 applies tensile stress to doping stressor layers 107, so that doping stressor layers 107 are applied to channel region
The compression added is further increased.Also, channel stress layer 111 applies tensile stress to channel region vertical direction, so that ditch
Road area obtains compression in the longitudinal direction, to further increase the compression on channel region length direction, further increases
Semiconductor devices carrier mobility optimizes the electric property of semiconductor devices, and effectively prevent short-channel effect and
Punchthrough problem.
The material of the intrinsic layer 112 is silicon or germanium.Carrier is in the interface of intrinsic layer 112 and gate dielectric layer 113
It scatters weak, to further increase the carrier mobility of channel region, improves the speed of service of semiconductor devices.
If the thickness of intrinsic layer 112 is too small, the thickness of the channel region of semiconductor devices is too small, will lead to and flows through channel region
Carrier quantity reduce, the operating current of semiconductor devices reduces, and influences the electric property of semiconductor devices；If intrinsic layer
112 thickness is excessive, then the amount for being located at the channel stress layer 111 of 112 lower section of intrinsic layer is very few, and channel stress layer 111 is caused to mention
The beneficial effect for rising channel region stress is affected.
For this purpose, in the present embodiment, the intrinsic layer 112 with a thickness of the 1/6 to 1/2 of trench depth, the intrinsic layer 112
Top surface is flushed with 100 surface of substrate.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (20)
1. a kind of forming method of semiconductor devices characterized by comprising
Substrate is provided, the substrate surface is formed with dummy gate structure；
Doped region is formed in the substrate of the dummy gate structure two sides；
Form the interlayer dielectric layer for being covered in the doped region surface and dummy gate structure sidewall surfaces, and the inter-level dielectric
Layer top surface is flushed with dummy gate structure top surface；
Etching removes the substrate of the dummy gate structure and the segment thickness below dummy gate structure, in the substrate
Form groove；
In the groove fill channel stress layer, in the doped region formed doping stressor layers, the channel stress layer with
The stress types for adulterating stressor layers are identical, and the channel stress layer top surface is lower than substrate surface, the channel stress layer
Material be insulating materials；Using plasma enhancing chemical vapor deposition process forms the channel stress layer, the channel
When the stress types of stressor layers are tensile stress, channel stress layer is formed in the plasma enhanced chemical vapor deposition technique
In technical process, other than applying high frequency power source into reaction chamber, apply low frequency power source also into reaction chamber, it is described
When the stress types of channel stress layer are compression, channel stress is formed in the plasma enhanced chemical vapor deposition technique
In the technical process of layer, there are the processes that H atom is rejected, and dangling bonds and cavity, the dangling bonds are formed in channel stress layer
It is cross-linked with each other；
Intrinsic layer is formed in the channel stress layer surface, and the intrinsic layer fills the full groove；
Gate structure is formed in the intrinsic layer surface.
2. the forming method of semiconductor devices as described in claim 1, which is characterized in that the shape of the groove is sigma shape.
3. the forming method of semiconductor devices as claimed in claim 2, which is characterized in that form the processing step packet of the groove
It includes: after removing the dummy gate structure, pre- groove being formed using the substrate that dry etch process etches removal segment thickness；
Continue to etch the substrate along the pre- groove using wet-etching technology, forms groove in substrate.
4. the forming method of semiconductor devices as claimed in claim 2, which is characterized in that the side wall of the groove has to doping
Area's the first apex angle outstanding, and the bottom of the groove has to substrate bottom the second apex angle outstanding.
5. the forming method of semiconductor devices as claimed in claim 4, which is characterized in that the channel stress layer top surface is high
In first apex angle.
6. the forming method of semiconductor devices as described in claim 1, which is characterized in that the technique for forming the channel stress layer
Step includes: to form the channel stress layer for filling the full groove, and the channel stress layer top surface is higher than inter-level dielectric
Layer top surface；Removal is higher than the channel stress layer of interlayer dielectric layer top surface, until channel stress layer top surface and layer
Between dielectric layer top surface flush；It is etched back to the channel stress layer of removal segment thickness, is lower than channel stress layer top surface
Substrate surface.
7. the forming method of semiconductor devices as described in claim 1, which is characterized in that the material of the channel stress layer is nitrogen
SiClx.
8. the forming method of semiconductor devices as claimed in claim 7, which is characterized in that the semiconductor devices of formation is NMOS device
When part, the stress types of the channel stress layer are tensile stress；When the semiconductor devices of formation is PMOS device, the channel is answered
The stress types of power layer are compression.
9. the forming method of semiconductor devices as claimed in claim 8, which is characterized in that the stress types of the channel stress layer
When for tensile stress, using plasma enhancing chemical vapor deposition process forms the technological parameter of the channel stress layer are as follows: anti-
Answering gas includes silicon source and nitrogen source, wherein silicon source SiH4, nitrogen source NH3, silicon source and nitrogen source gas flow ratio are 2 to 10,
Reaction chamber temperature is 200 degree to 400 degree, and reaction chamber pressure is 300 millitorrs to 500 millitorrs, and reaction chamber low frequency power is
150 watts to 500 watts.
10. the forming method of semiconductor devices as claimed in claim 8, which is characterized in that the stress class of the channel stress layer
When type is compression, using plasma enhancing chemical vapor deposition process forms the technological parameter of the channel stress layer are as follows:
Reaction gas includes silicon source and nitrogen source, wherein silicon source SiH4, nitrogen source NH3, silicon source and nitrogen source gas flow ratio be 0.2 to
2, reaction chamber temperature is 250 degree to 400 degree, and reaction chamber pressure is 400 millitorrs to 2000 millitorrs, reaction chamber radio-frequency power
It is 20 watts to 500 watts.
11. the forming method of semiconductor devices as described in claim 1, which is characterized in that the material of the intrinsic layer be silicon or
Germanium.
12. the forming method of semiconductor devices as claimed in claim 11, which is characterized in that the material of the intrinsic layer is silicon
When, the technological parameter of the intrinsic layer is formed using selective epitaxial process are as follows: the technological parameter of the selective epitaxial process
Are as follows: reaction gas includes silicon source gas, H2And HCl, silicon source gas SiH4Or SiH2Cl2, wherein silicon source gas flow is
1sccm to 1000sccm, HCl flow are 1sccm to 1000sccm, H2Flow is 100sccm to 50000sccm, reaction chamber
Temperature is 400 degree to 800 degree, and chamber pressure is 1 support to 500 supports.
13. the forming method of semiconductor devices as described in claim 1, which is characterized in that the intrinsic layer with a thickness of groove
The 1/6 to 1/2 of depth.
14. the forming method of semiconductor devices as described in claim 1, which is characterized in that further comprise the steps of: the doping stress
The stress types of layer are identical with the stress types of channel stress layer, adulterate the materials of stressor layers for SiC, SiCP, SiGe or
SiGeB。
15. a kind of semiconductor devices characterized by comprising
Substrate；
Groove in the substrate；
Fill the channel stress layer of the groove；
Positioned at the intrinsic layer of the channel stress layer surface, the intrinsic layer fills the full groove；
Positioned at the gate structure of the intrinsic layer surface；
Doped region in the substrate of the gate structure two sides；
Doping stressor layers are formed in the doped region, the channel stress layer is identical as the doping stress types of stressor layers, and
The channel stress layer top surface is lower than substrate surface, and the material of the channel stress layer is insulating materials；Using plasma
Body enhancing chemical vapor deposition process forms the channel stress layer, when the stress types of the channel stress layer are tensile stress,
In the technical process that the plasma enhanced chemical vapor deposition technique forms channel stress layer, in addition into reaction chamber
Apply outside high frequency power source, apply low frequency power source also into reaction chamber, the stress types of the channel stress layer are that pressure is answered
When power, in the technical process that the plasma enhanced chemical vapor deposition technique forms channel stress layer, there are H atoms to pick
The process removed forms dangling bonds in channel stress layer and cavity, the dangling bonds is cross-linked with each other.
16. semiconductor devices as claimed in claim 15, which is characterized in that the side wall of the groove has outstanding to doped region
First apex angle, and the bottom of the groove has to substrate bottom the second apex angle outstanding, the channel stress layer top surface
Higher than the first apex angle.
17. semiconductor devices as claimed in claim 15, which is characterized in that the material of the channel stress layer is silicon nitride；Institute
When to state semiconductor devices be NMOS device, the stress types of the channel stress layer are tensile stress；The semiconductor devices is
When PMOS device, the stress types of the channel stress layer are compression.
18. semiconductor devices as claimed in claim 15, which is characterized in that the material of the intrinsic layer is silicon or germanium.
19. semiconductor devices as claimed in claim 15, which is characterized in that the intrinsic layer with a thickness of the 1/6 of trench depth
To 1/2.
20. semiconductor devices as claimed in claim 15, which is characterized in that the stress types of the doping stressor layers are answered with channel
The stress types of power layer are identical, and the material for adulterating stressor layers is SiC, SiCP, SiGe or SiGeB.
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| CN111261700A (en) * | 2020-01-21 | 2020-06-09 | 中国科学院微电子研究所 | C-channel semiconductor device, method of manufacturing the same, and electronic apparatus including the same |
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