CN103280459A - Graphic strain NMOS (N-channel Metal Oxide Semiconductor) device with deep groove structure, and manufacturing method thereof - Google Patents
Graphic strain NMOS (N-channel Metal Oxide Semiconductor) device with deep groove structure, and manufacturing method thereof Download PDFInfo
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Abstract
The invention relates to a semiconductor technique, and provides a graphic strain NMOS (N-channel Metal Oxide Semiconductor) device with a deep groove structure, and a manufacturing method thereof, which are used for solving the problems of non-uniform distribution of groove strain caused by the adoption of a local strain technique and lower design flexibility caused by the adoption of a global strain technique device in the conventional strain NMOSFET (N-channel Metal Oxide Semiconductor Field Effect Transistor). According to the technical scheme, the graphic strain NMOS device with the deep groove structure comprises a source electrode, a drain electrode, a semiconductor substrate, a grid oxide layer, a source electrode expansion region, a source electrode heavily-doped region, a drain electrode expansion region, a drain electrode heavily-doped region, a grid electrode, a side wall, a deep isolation groove, top layer strain silicon and a medium layer, wherein the deep isolation groove is formed on the outer side of an active region; the top layer strain silicon is only positioned below a groove region; the medium layer is only positioned below the top layer strain silicon; and intrinsic tensile stress silicon nitride films are covered on the upper surfaces of the deep isolation groove, the source electrode heavily-doped region, the drain electrode heavily-doped region, the grid electrode and the side wall. The graphic strain NMOS device has the beneficial effects of larger and more uniform groove strain and suitability for strain NMOS devices.
Description
Technical field
The present invention relates to semiconductor technology, particularly strain n channel metal oxide semiconductor field effect transistor (NMOSFET).
Background technology
In the epoch that semiconductor integrated circuit develops into sub-micro, can improve semiconductor device carrier mobility and current driving ability by adopting strained silicon technology.Strain gauge technique relies on it significantly to promote and receive much concern with the compatibility of traditional handicraft and to performance.Introducing the bi-axial tensile strain that is parallel to channel plane in the raceway groove of N-type mos field effect transistor (NMOSFET) can make device performance obtain to promote; Introduce the single shaft tensile stress in orientation and also can make device performance obtain to promote, and the device drive ability increases with the increase of stress.
Present strained silicon technology mainly is divided into overall strain gauge technique and local strain gauge technique.The local train technology is only introduced stress at the regional area of semiconductor device usually.The local train technology mainly contains germanium silicon source and leaks (SiGe S/D) or carbon silicon source leakage (SiC S/D), dual stressed layers (strain silicon nitride block technology CESL), stress memory technique (Stress Memorization Technique, SMT) and shallow-trench isolation (Shallow Trench Isolation, STI) etc., existing local train MOS device cross section structure schematic diagram such as Fig. 1, it wraps Semiconductor substrate 1, shallow trench isolation region 2, gate oxide 3, grid 4, source extension regions 5, drain extensions 6, side wall 7, germanium silicon or carbon silicon source leak 8, source electrode heavily doped region 9, drain electrode heavily doped region 10, strain silicon nitride block layer 11, source electrode and drain electrode.Wherein strain desalination silicon block layer 11 can also can apply to separately in the device with germanium silicon or carbon silicon source leakage 8 simultaneously.Described source extension regions 5 and source electrode heavily doped region 9 are set up in parallel in the position of substrate 1 upper surface near source electrode, described drain extensions 6 is set up in parallel in the position of substrate 1 upper surface near drain electrode with drain electrode heavily doped region 10, if this device is provided with the upper surface that germanium silicon or 8 germanium silicon of carbon silicon source leakage or carbon silicon source leakage 8 are arranged on source electrode heavily doped region 9, and contact with source extension regions 5, another germanium silicon or carbon silicon source leakage 8 are arranged on the upper surface of drain electrode heavily doped region 10, and contact with drain extensions 6, substrate 1 upper surface between source extension regions 5 and the drain extensions 6 is provided with gate oxide 3, grid 4 is arranged on gate oxide 3 tops, above source extension regions 5 and drain extensions 6, grid 4 respectively is provided with a side wall 7 near the both sides of source electrode and drain electrode, shallow trench isolation region 2 is arranged on the active area outside, be about to raceway groove, source electrode and drain region surround, shallow trench isolation region 2, germanium silicon or carbon silicon source leak 8, the upper surface of side wall 7 and grid 4 is coated with strain silicon nitride block layer 11.Wherein, channel region is the zone between finger source electrode expansion area 5 and the drain extensions 6.The local train technology is introduced simple stress usually in raceway groove, the wherein uniaxial compressive stress reduction that can not bring other performances when promoting PMOS device drive ability reduces threshold voltage fluctuation etc. as device stability; Good technology is made compatibility to local train technology in addition and manufacture method is simple owing to having with the CMOS technology, only need increase a small amount of cost when improving performance of semiconductor device, therefore is subjected to industry and favors widely.But the local train technology be indirect with stress transfer in channel region, must there be decay or the release of stress to a certain degree in the process of this transfer, thereby limit it and be mainly used in channel length less than the small size device of 130nm, and the raceway groove mean stress is less, usually less than 1GPa; To the device of channel length greater than 130nm, the device performance that the local train technology is brought promotes and is not obvious.
Overall situation strain gauge technique comprises germanium silicon virtual substrate, strained-silicon-on-insulator (SSOI), germanium on insulator silicon (SGOI) etc., existing virtual substrate overall situation strain MOS device cross section structure schematic diagram such as Fig. 2 of adopting, it comprises source electrode, drain electrode, substrate 1, germanium silicon virtual substrate 12, strained silicon layer 26, shallow trench isolation region 2, gate oxide 3, grid 4, source extension regions 5, drain extensions 6, side wall 7, source electrode heavily doped region 9, drain electrode heavily doped region 10, described germanium silicon virtual substrate 12 is arranged on substrate 1 upper surface, strained silicon layer 26 is arranged on germanium silicon virtual substrate 12 upper surfaces, source extension regions 5 and source electrode heavily doped region 9 are set up in parallel in the position of strained silicon layer 3 upper surfaces near source electrode, described drain extensions 6 is set up in parallel in the position of strained silicon layer 26 upper surfaces near drain electrode with drain electrode heavily doped region 10, strained silicon layer upper surface between source extension regions 5 and the drain extensions 6 is provided with gate oxide 3, grid 4 is arranged on gate oxide 3 tops, grid 4 respectively is provided with a side wall 7 near the both sides of source electrode and drain electrode, two side walls 7 are separately positioned on source extension regions 5 and drain extensions 6 top shallow trench isolation regions 2 are arranged on the active area outside, are about to raceway groove, source electrode and drain region surround.Overall situation strain gauge technique can be introduced bigger biaxial stress to channel region, and usually greater than 1GPa, and its stress is not subjected to the restriction of device size.But the complicated process of preparation of backing material, manufacturing cost is higher.Usually can only produce one type strain on a silicon chip, can not satisfy different components to differently strained demand, the designs flexibility is lower.For germanium silicon virtual substrate, top layer silicon 26(or strained silicon layer) stress increases with the increase of relaxation germanium silicon layer 12 Ge contents, and to make the relaxation germanium silicon layer 12 of high Ge content, the thickness of germanium silicon layer 12 can not be too little; The critical thickness of top layer strained silicon layer 26 reduces with the increase of relaxation germanium silicon layer 12 Ge contents in addition.
If overall strain gauge technique can be combined with the local train technology, overall strain gauge technique is applied to regional area, introduce bigger stress to regional area, then can in effective boost device performance, not reduce the flexibility of designs, largely the boost device performance.
Summary of the invention
The objective of the invention is to adopt local train technology channel stress skewness for overcoming present strain NMOS FET, and adopt the lower shortcoming of overall strain gauge technique designs flexibility, a kind of patterned strained nmos device with deep groove structure and preparation method thereof is provided.
The present invention solves its technical problem, the technical scheme that adopts is, patterned strained nmos device with deep groove structure, comprise source electrode, drain electrode, Semiconductor substrate, gate oxide, source extension regions, the source electrode heavily doped region, drain extensions, the drain electrode heavily doped region, grid and side wall, it is characterized in that, also comprise the deep isolation trench that is arranged on the active area outside, the top layer strained silicon that only is positioned at the channel region below reaches the dielectric layer that only is positioned at top layer strained silicon below, described deep isolation trench, the source electrode heavily doped region, the drain electrode heavily doped region, the upper surface of grid and side wall is coated with one deck intrinsic tensile stress silicon nitride film.
Concrete, the upper surface of described deep isolation trench is at least 0.4 μ m to the vertical range of lower surface.
Further, described deep isolation trench is rectangle.
Concrete, described deep isolation trench is trapezoidal or notch cuttype, described trapezoidal or step-like long limit is positioned at the upper surface of deep isolation trench.
Further again, described dielectric layer is silicon dioxide.
Have the manufacture method of the patterned strained nmos device of deep groove structure, it is characterized in that, may further comprise the steps:
Step 01, make deep isolation trench in the active area outside that will make device of Semiconductor substrate, wherein the deep isolation trench degree of depth is not less than 0.4um, adopt dry etching, pass through thermal oxide growth layer of silicon dioxide layer, deposit silicon dioxide or other dielectrics again after the deep isolation trench etching earlier;
Step 02, the semiconductor substrate region between the deep isolation trench is carried out wet etching be formed with the source region, etching depth is greater than 0.2um, less than the deep isolation trench degree of depth;
Step 03, active area is carried out the deposit of relaxation germanium silicon layer, the thickness of deposit relaxation germanium silicon layer is not less than 0.2um, and less than and near active area thickness;
Step 04, silicon epitaxial layers forms the top layer strained silicon on relaxation germanium silicon layer, its thickness greater than 15nm less than 50nm;
Step 05, on the top layer strained silicon heat growth gate oxide, deposit polysilicon on gate oxide, deposit grid silicon nitride etch barrier layer and carry out the grid etching and form polygate electrodes on polysilicon, it is grid, both sides near source electrode and drain electrode make the silicon nitride side wall on gate oxide, grid and grid silicon nitride etch barrier layer again, again at non-active area deposit silicon nitride etching barrier layer;
Step 06, be etching barrier layer with the silicon nitride, top layer strained silicon layer and relaxation germanium silicon layer are carried out dry etching, the etching total depth is greater than top layer strained silicon thickness, less than top layer strained silicon and relaxation germanium silicon layer thickness sum;
Step 07, employing wet method selective etch are removed relaxation germanium silicon layer, form the cavity district;
Step 08, by dry oxidation certain thickness silicon dioxide layer of silicon interface growth in the district of cavity, in the district of cavity, fill silicon dioxide layer as dielectric layer again;
Step 09, the silicon nitride etch barrier layer by deposit are under the mask, source-drain area silicon dioxide is carried out dry etching removes, and then with wet-cleaned not by the clean residual silicon dioxide in channel region silicon side of dry etching, the zone that is etched is leaked in the formation source;
Concrete, in the step 01, earlier by thermal oxide growth layer of silicon dioxide layer, the thickness of this silicon dioxide layer is for being not less than 5nm after the described deep isolation trench etching.
Further, in the step 08, described certain thickness is that 2nm is to 5nm.
Concrete, in the step 5, the thickness of described silicon nitride side wall greater than 10nm less than 40nm.
Further, in the step 11, described side wall is made of jointly the side wall of silicon nitride side wall and source extension regions or drain extensions doping back deposit.
The invention has the beneficial effects as follows, by above-mentioned patterned strained nmos device with deep groove structure and preparation method thereof, as can be seen, this device is different with common overall strain device drawn game portion strain device, its virtual substrate germanium silicon layer, namely relaxation germanium silicon layer is only grown at active area, and its stress only acts on the channel region of device, because big stress by the part relaxation, can again to this zone be introduced by follow-up tensile stress silicon nitride block layer at source water clock erosion back stress in the trench edges zone.Channel region stress reduces rapidly along with the increase of channel length in the local train technology, and channel region stress reduces the channel stress skewness rapidly along with leaking the increase of distance from the source; Channel stress is bigger more even among the present invention, and its stress is not subjected to the influence of device size substantially.
Description of drawings
Fig. 1 is existing local train MOS device cutaway view;
Fig. 2 is existing overall strain MOS device cutaway view;
Fig. 3 is the cutaway view of making deep isolation trench in the present embodiment in Semiconductor substrate;
Fig. 4 in the present embodiment after NMOS active area silicon carries out wet etching the cutaway view of device;
Fig. 5 is at the cutaway view of etch areas extension relaxation germanium silicon layer in the present embodiment;
Fig. 6 be in the present embodiment behind epitaxial monocrystalline silicon on the active area relaxation germanium silicon layer cutaway view of device;
Fig. 7 for carry out in the present embodiment grid make with the deposit of silicon nitride etch block mask after the cutaway view of device;
Fig. 8 is the cutaway view of device after the source-drain area top layer strained silicon etching in the present embodiment;
Fig. 9 is the cutaway view of device when forming the cavity district behind the selective etch relaxation germanium silicon layer in the present embodiment;
Figure 10 is the cutaway view that device behind the silicon dioxide is filled in cavity district in the present embodiment;
Figure 11 is for carrying out the cutaway view of device behind the dry etching in the present embodiment to source-drain area silicon dioxide;
Figure 12 is to be the cutaway view of device behind the source-drain area epitaxial monocrystalline silicon in the present embodiment;
Figure 13 has the cutaway view of the patterned strained nmos device of deep groove structure for the present invention;
Wherein, 1 is Semiconductor substrate, and 2 is shallow trench isolation region; 3 is grid oxygen, and 4 is the polycrystalline grid, and 5 is source extension regions; 6 is drain extensions, and 7 is side wall, and 8 is that leak in germanium silicon or carbon silicon source; 9 is the source electrode heavily doped region; 10 are the drain electrode heavily doped region, and 11 are strain silicon nitride block layer, and 12 is germanium silicon virtual substrate; 13 is deep isolation trench; 14 is active area, and 15 is relaxation germanium silicon layer, and 16 is top layer strained silicon layer (or top silicon layer); 17 use the silicon nitride etch barrier layer for grid etch; the 18 silicon nitride side walls of using for the grill-protected electrode, the 19 silicon nitride etch barrier layers for the non-active area of protection, 20 is etch areas; 21 is the cavity district; 22 is dielectric layer, and 23 are source water clock erosion zone, and 24 are the silicon nitride side wall by twice moulding; 25 is intrinsic tensile stress silicon nitride block layer, and 110 is top layer strained silicon stress relaxation line of demarcation after the relaxation germanium silicon layer etching.
Embodiment
Below in conjunction with drawings and Examples, describe technical scheme of the present invention in detail.
The present invention have deep groove structure patterned strained nmos device cutaway view as shown in figure 13, it comprises source electrode, drain electrode, Semiconductor substrate 1, gate oxide 3, source extension regions 5, source electrode heavily doped region 9, drain extensions 6, drain electrode heavily doped region 10, grid 4 and side wall 24, also comprise the deep isolation trench 13 that is arranged on active area 14 outsides, the top layer strained silicon 16 that only is positioned at the channel region below reaches the dielectric layer 22 that only is positioned at top layer strained silicon 16 belows, deep isolation trench 13, source electrode heavily doped region 9, drain electrode heavily doped region 10, the upper surface of grid 4 and side wall 24 is coated with one deck intrinsic tensile stress silicon nitride film 25.Manufacture method with patterned strained nmos device of deep groove structure of the present invention is: active area 14 outsides that at first will make device on Semiconductor substrate 1 make deep isolation trench 13, wherein deep isolation trench 13 degree of depth are not less than 0.4um, adopt dry etching, pass through thermal oxide growth layer of silicon dioxide layer after deep isolation trench 13 etchings earlier, deposit silicon dioxide or other dielectrics again, then the semiconductor substrate region between two deep isolation trench 13 is carried out wet etching and be formed with source region 14, etching depth is greater than 0.2um, less than deep isolation trench 13 degree of depth, again active area 14 is carried out 15 deposits of relaxation germanium silicon layer, the thickness of deposit relaxation germanium silicon layer 15 is not less than 0.2um, and less than and near active area 14 thickness, silicon epitaxial layers forms top layer strained silicon silicon 16(or top layer silicon on relaxation germanium silicon layer 15 again) and to its doping, its thickness greater than 15nm less than 50nm, and on top layer strained silicon 16 heat growth gate oxide 3, deposit polysilicon on gate oxide 3, deposit grid silicon nitride etch barrier layer 17 and carry out the grid etching and form polygate electrodes on polysilicon, it is grid 4, again at gate oxide 3, grid 4 and grid silicon nitride etch barrier layer 17 make silicon nitride side wall 18 near the both sides of source electrode and drain electrode, again at non-active area deposit silicon nitride etching barrier layer 19, be etching barrier layer then with the silicon nitride, 16 layers of top layer strained silicon and relaxation germanium silicon layer 15 are carried out dry etching, the etching total depth is greater than top layer strained silicon 16 thickness, less than top layer strained silicon 16 and relaxation germanium silicon layer 15 thickness sums, adopt the wet method selective etch to remove relaxation germanium silicon layer 15 again, form cavity district 21, then by dry oxidation certain thickness silicon dioxide layer of silicon interface growth in cavity district 21, in cavity district 21, fill silicon dioxide layer as dielectric layer 22 again, silicon nitride etch barrier layer (comprising grid silicon nitride etch barrier layer 17 and silicon nitride etch barrier layer 19) by deposit is under the mask, source-drain area silicon dioxide is carried out dry etching to be removed, and then with wet-cleaned not by the clean residual silicon dioxide in channel region silicon side of dry etching, the zone 23 that is etched is leaked in the formation source, leak the zone 23 that is etched in the source and carry out the monocrystalline silicon extension, remove silicon nitride etch barrier layer 19 and grid silicon nitride etch barrier layer 17 masks at last, carry out the doping of source extension regions 5 and drain extensions 6, make side wall 24, to source-drain area heavy doping, form source electrode heavily doped region 9 and drain electrode heavily doped region 10, again at source electrode heavily doped region 9, drain electrode heavily doped region 10, the upper surface deposition of intrinsic tensile stress silicon nitride film 25 of grid 4 and side wall 24.
Embodiment
Have in this example deep groove structure patterned strained nmos device cutaway view as shown in figure 13, deep isolation trench 13 can be rectangle, trapezoidal or notch cuttype.
The patterned strained nmos device with deep groove structure of this example, comprise source electrode, drain electrode, Semiconductor substrate 1, gate oxide 3, source extension regions 5, source electrode heavily doped region 9, drain extensions 6, drain electrode heavily doped region 10, grid 4 and side wall 24, source electrode in its position and the prior art, drain electrode, Semiconductor substrate 1, gate oxide 3, source extension regions 5, source electrode heavily doped region 9, drain extensions 6, drain electrode heavily doped region 10, grid 4 and side wall 7 corresponding (referring to Fig. 1 or Fig. 2), compared with prior art, also comprise the deep isolation trench 13 that is arranged on active area 14 outsides, this deep isolation trench 13 is about to raceway groove, source electrode and drain region surround, the top layer strained silicon 16 that only is positioned at the channel region below reaches the dielectric layer 22 that only is positioned at top layer strained silicon 16 belows, deep isolation trench 13, source electrode heavily doped region 9, drain electrode heavily doped region 10, the upper surface of grid 4 and side wall 24 is coated with one deck intrinsic tensile stress silicon nitride film 25.
Here, the upper surface of deep isolation trench 13 is at least 0.4 μ m to the vertical range of lower surface, can be rectangle, trapezoidal or notch cuttype, and when deep isolation trench 13 was trapezoidal or notch cuttype, this trapezoidal or step-like long limit was positioned at the upper surface of deep isolation trench 13.Dielectric layer 22 is silicon dioxide.
In the manufacture method of the patterned strained nmos device with deep groove structure of this example, may further comprise the steps:
Step 01, make deep isolation trench 13 in the active area that will make device 14 outsides of Semiconductor substrate 1, referring to Fig. 3, wherein deep isolation trench 13 degree of depth are not less than 0.4um, adopt dry etching, be not less than the silicon dioxide layer of 5nm after deep isolation trench 13 etchings earlier by thermal oxide growth thickness, again by method deposit silicon dioxide or other dielectrics such as CVD or LPCVD, this deep isolation trench 13 is mainly used in device isolation and the subsequent technique supporting role to grid 4.
Step 02, the semiconductor substrate region between the deep isolation trench 13 is carried out wet etching be formed with source region 14, referring to Fig. 4, this etching is same sex etching, and border stops restriction certainly by silicon dioxide around it, etching depth is greater than 0.2um, less than the degree of depth of deep isolation trench 13.
Step 03, active area 14 is carried out 15 deposits of relaxation germanium silicon layer, the thickness of deposit relaxation germanium silicon layer 15 is not less than 0.2um, and less than and near active area 14 thickness, referring to Fig. 5.
Step 04, silicon epitaxial layers forms top layer strained silicon 16 on relaxation germanium silicon layer 15, referring to Fig. 6, its thickness greater than 15nm less than 50nm.
Step 05, on top layer strained silicon 16 heat growth gate oxide 3, deposit polysilicon on gate oxide 3, deposit grid silicon nitride etch barrier layer 17 and carry out the grid etching and form polygate electrodes on polysilicon, it is grid 4, both sides near source electrode and drain electrode make silicon nitride side wall 18 on gate oxide 3, grid 4 and grid silicon nitride etch barrier layer 17 again, the thickness of this silicon nitride side wall 18 greater than 10nm less than 40nm, again at non-active area deposit silicon nitride etching barrier layer 19, referring to Fig. 7.
Step 06, be etching barrier layer with the silicon nitride, 16 layers of top layer strained silicon and relaxation germanium silicon layer 15 are carried out dry etching, the etching total depth is greater than top layer strained silicon 16 thickness, and less than top layer strained silicon 16 and relaxation germanium silicon layer 15 thickness sums, device as shown in Figure 8 after the etching.
Step 07, adopt the wet method selective etch to remove relaxation germanium silicon layer 15, form cavity district 21, referring to Fig. 9, wherein grid (comprising grid oxygen 3, polycrystalline grid 4, side wall 18) link to each other with isolation channel 13 at Width (in the channel plane perpendicular to figure The midsagittal plane direction).On Width, the strained silicon layer of bi-axial tensile strain 16 is owing to be subjected to the restriction of grid, and the stress of its Width can not relaxation; And in orientation (from the source to leak direction), strained silicon layer 16 is because below and raceway groove two ends are all free, stress is by relaxation in the silicon of stress relaxation line 110 lower zones, and the 110 upper area strains of stress relaxation line are owing to be subjected to the constraint of grid, strain can not relaxation, still remains the tensile strain state.
Step 08, by dry oxidation in cavity district 21 silicon interface growth 2nm to the thick silicon dioxide layer of 5nm, again in the cavity district 21 the filling silicon dioxide layer as dielectric layer 22, referring to Figure 10; Wherein the purpose of the silicon dioxide layer of dry method growth is to prevent because the silicon dioxide of filling and channel region silicon interface defective cause the interface electric leakage; The function of oxygen buried layer is identical in the silicon dioxide of the silicon dioxide of filling and heat growth and the SOI device, therefore with the silicon dioxide of filling and hot silicon dioxide of growing as dielectric layer 22.
Step 09, the silicon nitride etch barrier layer (comprising grid silicon nitride etch barrier layer 17 and silicon nitride etch barrier layer 19) by deposit are under the mask, source-drain area silicon dioxide is carried out dry etching to be removed, and then with wet-cleaned not by the clean residual silicon dioxide in channel region silicon side of dry etching, the zone 23 that is etched is leaked in the formation source, so that the monocrystalline silicon of extension and channel region top layer strained silicon 16 have excellent contact in the subsequent technique, referring to Figure 11.
Be that with common strained-soi device difference dielectric layer 22 is only below channel region, top layer strained silicon 16 is the nmos device channel region, and its stress is the bi-axial tensile strain of relaxation germanium silicon layer 15 introducings and the common combined stress of forming of single shaft tensile stress that intrinsic tensile stress silicon nitride film 25 is introduced.Source-drain area stress is different with the channel region stress types, and channel region is combined stress, and source-drain area is the compression that the intrinsic tensile stress silicon nitride film 25 of direct deposit on it introduced.
These device deep isolation trench 13 degree of depth are greater than 0.4um, much larger than the common isolation channel degree of depth.It act as identical with common isolation channel on the one hand, be used for device isolation, being used for the preceding silicon etching of relaxation germanium silicon layer 15 extensions on the other hand from stopping the border. this device side wall 24 is made at twice, silicon nitride side wall 18 thinner thicknesses that make the first time, its thickness is that 10nm is between the 40nm, be mainly used in etching source-drain area top layer strained silicon 16 during with relaxation germanium silicon layer 15 zones during for the protection of grid with at epitaxial monocrystalline silicon grid isolate usefulness with source-drain area, the purpose of its thinner thickness is in order to make dielectric layer 22 be limited in the channel region below, make the thickness of source extension regions 5 and drain extensions 6 bigger, thereby can reduce the resistance of source extension regions 5 and drain extensions 6; Directly link to each other with substrate 1 owing to below the source-drain area simultaneously, but the heat radiation of enhance device reduces floater effect.The top layer strained silicon 16 of this device channel region is to make by epitaxy technique, its growth quality is better, and controllable thickness can make top layer strained silicon 16 thinner built in nanoscale, allow device be operated in full spent condition, thereby can overcome the problems such as floater effect that the SOI device exists.This device only is limited in the channel region below with silica dioxide medium layer 22, and the BOX zone that is similar in the ultra-thin strained-soi device only is limited in regional area, therefore can claim that also this device is patterned strained SOI device.
This device is different with common overall strain device drawn game portion strain device, its relaxation germanium silicon layer 15 is only grown at active area, and its stress only acts on the channel region of device, because big stress by the part relaxation, can again to this zone be introduced by intrinsic tensile stress silicon nitride film 25 at source water clock erosion back stress in the trench edges zone.Channel region stress reduces rapidly along with the increase of channel length in the local train technology, and channel region stress reduces the channel stress skewness rapidly along with leaking the increase of distance from the source; Channel stress is bigger more even among the present invention, and its stress is not subjected to the influence of device size substantially.
This device and common SON(or SOA) device is different, relaxation germanium silicon layer 15 thickness germanium silicon layer thickness in the SON device in the invention; SON device germanium silicon layer thickness is usually less than 0.1um, and among the present invention relaxation germanium silicon layer 15 thickness usually greater than 0.2um; The germanium silicon layer is for the cavity of etching below raceway groove district in the SON device, and relaxation germanium silicon layer 15 forms local SOI device in order to form cavity district 21 below raceway groove to fill silicon dioxide first among the present invention, second utilizes relaxation germanium silicon layer 15 to introduce stress to channel region; The lifting of device performance is mainly caused by stress among the present invention.
Claims (10)
1. the patterned strained nmos device that has deep groove structure, comprise source electrode, drain electrode, Semiconductor substrate (1), gate oxide (3), source extension regions (5), source electrode heavily doped region (9), drain extensions (6), drain electrode heavily doped region (10), grid (4) and side wall (24), it is characterized in that, also comprise the deep isolation trench (13) that is arranged on active area (14) outside, the top layer strained silicon (16) that only is positioned at the channel region below reaches the dielectric layer (22) that only is positioned at top layer strained silicon below, described deep isolation trench (13), source electrode heavily doped region (9), drain electrode heavily doped region (10), the upper surface of grid (4) and side wall (24) is coated with one deck intrinsic tensile stress silicon nitride film (25).
2. according to the described patterned strained nmos device with deep groove structure of claim 1, it is characterized in that the upper surface of described deep isolation trench (13) is at least 0.4 μ m to the vertical range of lower surface.
3. according to the described patterned strained nmos device with deep groove structure of claim 1, it is characterized in that described deep isolation trench (13) is rectangle.
4. according to the described patterned strained nmos device with deep groove structure of claim 1, it is characterized in that described deep isolation trench (13) is trapezoidal or stairstepping, described trapezoidal or step-like long limit is positioned at the upper surface of trench structure.
5. according to claim 1 or 2 or 3 or 4 described patterned strained nmos devices with deep groove structure, it is characterized in that described dielectric layer (22) is silicon dioxide.
6. have the manufacture method of the patterned strained nmos device of deep groove structure, it is characterized in that, may further comprise the steps:
Step 01, at the active area that will make device (14) the arranged outside deep isolation trench (13) of Semiconductor substrate (1), wherein deep isolation trench (13) degree of depth is not less than 0.4um, adopt dry etching, pass through thermal oxide growth layer of silicon dioxide layer, deposit silicon dioxide or other dielectrics again after deep isolation trench (13) etching earlier;
Step 02, wet etching is carried out in Semiconductor substrate (1) zone between the deep isolation trench (13) be formed with source region (14), etching depth is greater than 0.2um, less than deep isolation trench (13) degree of depth;
Step 03, active area (14) is carried out relaxation germanium silicon layer (15) deposit, the thickness of deposit relaxation germanium silicon layer (15) is not less than 0.2um, and less than and near active area (14) thickness;
Step 04, go up silicon epitaxial layers at relaxation germanium silicon layer (15) and form top layer strained silicon (16) and mix, its thickness greater than 15nm less than 50nm;
Step 05, go up heat growth gate oxide (3) in top layer strained silicon (16), go up the deposit polysilicon at gate oxide (3), deposit grid silicon nitride etch barrier layer (17) and carry out the grid etching and form polygate electrodes on polysilicon, be grid (4), both sides near source electrode and drain electrode make silicon nitride side wall (18) on gate oxide (3), grid (4) and grid silicon nitride etch barrier layer (17) again, again at non-active area deposit silicon nitride etching barrier layer (19);
Step 06, be etching barrier layer with the silicon nitride, top layer strained silicon (16) and relaxation germanium silicon layer (15) are carried out dry etching, the etching total depth is greater than top layer strained silicon (16) thickness, less than top layer strained silicon (16) and relaxation germanium silicon layer (15) thickness sum;
Step 07, employing wet method selective etch are removed relaxation germanium silicon layer (15), form cavity district (21);
Step 08, by dry oxidation certain thickness silicon dioxide layer of silicon interface growth in cavity district (21), in cavity district (21), fill silicon dioxide layer as dielectric layer (22) again;
Step 09, the silicon nitride etch barrier layer by deposit are under the mask, source-drain area silicon dioxide is carried out dry etching to be removed, and then with wet-cleaned not by the clean residual silicon dioxide in channel region silicon side of dry etching, the zone (23) that is etched is leaked in the formation source;
Step 10, leak the zone (23) that is etched in the source and carry out the monocrystalline silicon extension;
Step 11, removal silicon nitride etch barrier layer (19) and grid silicon nitride etch barrier layer (17) mask, carry out the doping of source extension regions (5) and drain extensions (6), make side wall (24), to source-drain area heavy doping, form source electrode heavily doped region (9) and drain electrode heavily doped region (10), again at the upper surface deposition of intrinsic tensile stress silicon nitride film (25) of source electrode heavily doped region (9), drain electrode heavily doped region (10), grid (4) and side wall (24).
7. according to the described manufacture method with patterned strained nmos device of deep groove structure of claim 6, it is characterized in that, in the step 01, earlier by thermal oxide growth layer of silicon dioxide layer, the thickness of this silicon dioxide layer is for being not less than 5nm after described deep isolation trench (13) etching.
8. according to the described manufacture method with patterned strained nmos device of deep groove structure of claim 6, it is characterized in that in the step 08, described certain thickness is that 2nm is to 5nm.
9. according to the described manufacture method with patterned strained nmos device of deep groove structure of claim 6, it is characterized in that, in the step 5, the thickness of described silicon nitride side wall (18) greater than 10nm less than 40nm.
10. according to claim 6 or 7 or 8 or 9 described manufacture methods with patterned strained nmos device of deep groove structure, it is characterized in that, in the step 11, the side wall of deposit was formed jointly after described side wall (24) was mixed by silicon nitride side wall (18) and source extension regions (8) or drain extensions (10).
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| CN104576372A (en) * | 2013-10-10 | 2015-04-29 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and a manufacturing method thereof |
| CN105448723A (en) * | 2014-08-22 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and forming method thereof |
| CN108028278A (en) * | 2015-09-25 | 2018-05-11 | 英特尔公司 | For stress enhancing and the deep EPI for appearing realization by dorsal part contacted |
| CN111081764A (en) * | 2019-12-30 | 2020-04-28 | 深圳第三代半导体研究院 | Transistor with embedded source and drain and preparation method thereof |
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| US20060118880A1 (en) * | 2004-12-08 | 2006-06-08 | Kabushiki Kaisha Toshiba | Semiconductor device including field-effect transistor |
| CN101300670A (en) * | 2005-10-31 | 2008-11-05 | 先进微装置公司 | An embedded strain layer in thin soi transistor and a method of forming the same |
| CN102339859A (en) * | 2010-07-16 | 2012-02-01 | 中国科学院微电子研究所 | Metal-oxide-semiconductor (MOS) transistor and formation method thereof |
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| US20060118880A1 (en) * | 2004-12-08 | 2006-06-08 | Kabushiki Kaisha Toshiba | Semiconductor device including field-effect transistor |
| CN101300670A (en) * | 2005-10-31 | 2008-11-05 | 先进微装置公司 | An embedded strain layer in thin soi transistor and a method of forming the same |
| CN102339859A (en) * | 2010-07-16 | 2012-02-01 | 中国科学院微电子研究所 | Metal-oxide-semiconductor (MOS) transistor and formation method thereof |
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| CN104576372A (en) * | 2013-10-10 | 2015-04-29 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and a manufacturing method thereof |
| CN105448723A (en) * | 2014-08-22 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and forming method thereof |
| CN105448723B (en) * | 2014-08-22 | 2019-07-30 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
| CN108028278A (en) * | 2015-09-25 | 2018-05-11 | 英特尔公司 | For stress enhancing and the deep EPI for appearing realization by dorsal part contacted |
| CN111081764A (en) * | 2019-12-30 | 2020-04-28 | 深圳第三代半导体研究院 | Transistor with embedded source and drain and preparation method thereof |
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| CN103280459B (en) | 2016-10-05 |
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