US9425198B2 - Semiconductor device having strain-relaxed buffer layer and method of manufacturing the same - Google Patents

Semiconductor device having strain-relaxed buffer layer and method of manufacturing the same Download PDF

Info

Publication number
US9425198B2
US9425198B2 US14/289,672 US201414289672A US9425198B2 US 9425198 B2 US9425198 B2 US 9425198B2 US 201414289672 A US201414289672 A US 201414289672A US 9425198 B2 US9425198 B2 US 9425198B2
Authority
US
United States
Prior art keywords
strain
buffer layer
relaxed buffer
channel layer
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US14/289,672
Other versions
US20140361378A1 (en
Inventor
Dong-Kyu Lee
Jae-Hwan Lee
Tae-yong Kwon
Sang-Su Kim
Jung-Dal Choi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Assigned to SAMSUNG ELECTRONICS CO., LTD. reassignment SAMSUNG ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHOI, JUNG-DAL, LEE, DONG-KYU, KIM, SANG-SU, KWON, TAE-YONG, LEE, JAE-HWAN
Publication of US20140361378A1 publication Critical patent/US20140361378A1/en
Priority to US15/212,367 priority Critical patent/US20160329333A1/en
Application granted granted Critical
Publication of US9425198B2 publication Critical patent/US9425198B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8252—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8258—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213, H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds

Definitions

  • the inventive concept relates to a semiconductor device and to a method of manufacturing the same. More particularly, the inventive concept relates to a semiconductor device comprising a transistor having a channel region in which a stress has been induced and to a method of manufacturing the same.
  • the width and length of a channel of a MOS transistor are becoming smaller (for both NMOS and PMOS transistors) in response to the growing demands for smaller semiconductor devices.
  • a reduction in the length of the channel of a MOS transistor increases the likelihood that the device will exhibit certain defective performance characteristics known as short-channel effects.
  • Improved transistor structures such as an RCAT (Recess Channel Array Transistor) or a SRCAT (Sphere-shaped Recess Channel Array Transistor), have allowed for greater channel lengths without compromising an overall reduction in size of the transistor.
  • semiconductor devices may employ an RCAT or SRCAT to prevent short-channel effects, i.e., to ensure a high degree of performance.
  • the performance of a MOS transistor is generally compromised if the width of the channel of the MOS transistor is reduced because narrower channels reduce the amount of current flowing through the channel.
  • the scaling down of the MOS transistor will worsen the reliability of the semiconductor device.
  • a semiconductor device including a substrate, a strain-relaxed buffer layer on the substrate, a first well in the strain-relaxed buffer layer and located in a first region of the device, a second well in the strain-relaxed buffer layer and located in a second region of the device, a first channel layer on the first well, and a second channel layer on the second well, and in which a lattice constant of material constituting the first channel layer is less than a lattice constant of material constituting the strain-relaxed buffer layer, and a lattice constant of material constituting the second channel layer is greater than said lattice constant of the material constituting the strain-relaxed buffer layer.
  • a semiconductor device including a substrate, a strain-relaxed buffer layer having a p-type impurity on the substrate, a first channel layer on the strain-relaxed buffer layer and located in a first region of the device, an n-type well in the strain-relaxed buffer layer and located in a second region of the device, a second channel layer on the n-type well, and a gate dielectric disposed directly on the first and second channel layers, and in which a lattice constant of material constituting the first channel layer is less than a lattice constant of material constituting the strain-relaxed buffer layer, but a lattice constant of material constituting the second channel layer is greater than said lattice constant of material constituting the strain-relaxed buffer layer.
  • a semiconductor device including a substrate, a strain-relaxed buffer layer on the substrate, an NMOS transistor having a tensile-stressed channel region on the strain-relaxed buffer layer, and a PMOS transistor having a tensile stressed channel region on the strain-relaxed buffer layer.
  • a first channel layer is disposed on the strain-relaxed buffer layer and extends in a lengthwise direction between the source and drain of the NMOS transistor.
  • a gate electrode of the NMOS transistor is disposed on the first channel layer.
  • a second channel layer is disposed on the strain-relaxed buffer layer and extends in a lengthwise direction between the source and drain of the PMOS transistor.
  • a gate electrode of the PMOS transistor is disposed on the first channel layer.
  • a lattice constant of material constituting the first channel layer is less than a lattice constant of material constituting the strain-relaxed buffer layer.
  • a lattice constant of material constituting the second channel layer is greater than the lattice constant of the material constituting the strain-relaxed buffer layer.
  • a method of manufacturing a semiconductor device which includes forming a strain-relaxed buffer layer on a substrate, forming a first well in the strain-relaxed buffer layer in a first region, forming a second well in the strain-relaxed buffer layer in a second region, forming a first channel layer simultaneously on the first well and the second well and wherein the first channel layer is formed of a material having a lattice constant less than that of a lattice constant of material constituting the strain-relaxed buffer layer, forming a first mask that covers the first channel layer on the first well and exposes the first channel layer on the second well, removing the first channel layer from over the second well, forming a second channel layer on the second well and wherein the second channel layer is formed of a material having a lattice constant greater than that of material constituting the strain-relaxed buffer layer, and removing the first mask.
  • a method of manufacturing a semiconductor device which includes providing a substrate, forming a strain-relaxed buffer layer on the substrate, forming an n-type well in the strain-relaxed buffer layer, forming a first channel layer on the strain-relaxed buffer layer in a first region and wherein the first channel layer is formed of a material having a lattice constant less than that of a lattice constant of material constituting the strain-relaxed buffer layer, forming a second channel layer on the n-type well in a second region and wherein the second channel layer is formed of a material having a lattice constant greater than that of material constituting the strain-relaxed buffer layer, and forming a gate dielectric layer directly on the first and second channel layers.
  • FIGS. 1 through 17 illustrate an embodiment of a method of manufacturing a semiconductor device according to the inventive concept, wherein each of FIGS. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17 is a cross-sectional view of the device during the course of its manufacture.
  • FIGS. 18 through 33 illustrate another embodiment of a method of manufacturing a semiconductor device according to f the inventive concept, wherein each of FIGS. 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 and 32 is a cross-sectional view of the device during the course of its manufacture and FIG. 33 is a cross-sectional view of the device itself.
  • spatially relative terms such as “upper,” and “lower” are used to describe an element's and/or feature's relationship to another element(s) and/or feature(s) as illustrated in the figures.
  • the spatially relative terms may apply to orientations in use which differ from the orientation depicted in the figures.
  • all such spatially relative terms refer to the orientation shown in the drawings for ease of description and are not necessarily limiting as embodiments according to the inventive concept can assume orientations different than those illustrated in the drawings when in use.
  • top or bottom as used to describe a surface generally refer not only to the orientation depicted in the drawings but to the fact that the surface is the uppermost or bottommost surface in the orientation depicted, as would be clear from the drawings and context of the written description.
  • strain-relaxed as used to describe a layer will be understood as generally referring to the fact that the layer has no intrinsic stress, i.e., no internal stress as the result of the way in which it was produced. That is, the term “strain-relaxed” will be understood as meaning substantially stress free.
  • a description of the inventive concept includes examples in which the crystal lattice of material constituting key layers has a cubic lattice structure and so, the term “a lattice constant” may be understood as referring to all of the constants of the units making up the crystal lattice.
  • FIGS. 1 through 17 A first embodiment of a method of manufacturing a semiconductor device according to the inventive concept will now be described in detail with reference to FIGS. 1 through 17 .
  • the substrate 100 may be a rigid substrate, e.g., a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a silicon germanium substrate, an indium antimonide substrate, a lead telluride substrate, an indium arsenide substrate, an indium phosphorus substrate, a gallium arsenide substrate, or an antimony gallium substrate.
  • SOI silicon-on-insulator
  • a strain-relaxed buffer layer 110 is formed on the substrate 100 .
  • the strain-relaxed buffer layer 110 may comprise at least one material selected from the group consisting of compounds including a semiconductor from group 3, 4 or 5, silicon germanium (SiGe), and germanium (Ge).
  • Compounds including a semiconductor from group 3, 4 or 5 include gallium arsenic antimonide (GaAsSb), indium gallium arsenide (InGaAs), indium antimonide (InSb), gallium antimonide (GaSb), and indium arsenide (InAs).
  • the strain-relaxed buffer layer 110 may be formed by an epitaxial growth process which is not accompanied by any doping process (i.e., without doping the epitaxially grown material with n-type or p-type dopants). Such a process may be conducted in a temperature range of 450-1200° C. Also, the strain-relaxed buffer layer 110 is preferably formed to a thickness of 300 to 1000 nm.
  • a sacrificial layer 120 is formed on the strain-relaxed buffer layer 110 .
  • the sacrificial layer 120 may comprise a silicon oxide layer, having a thickness of 10 to 100 nm, formed by a thermal oxidation process or chemical vapor deposition (CVD) process.
  • the first mask layer(s) 130 may comprise at least one layer of material selected from the group consisting of silicon nitride (SiN) and silicon oxynitride (SiON).
  • a photoresist pattern 140 is formed on the first mask layer(s) 130 .
  • the photoresist pattern 140 exposes a portion of the upper surface of the first mask layer(s) 130 formed at a boundary between a first region I and a second region II of the device.
  • a trench 150 is formed in the strain-relaxed buffer layer 110 at the boundary between the first region I and the second region II.
  • the trench 150 is formed by etching the first mask layer(s) 130 , the sacrificial layer 120 , and the strain-relaxed buffer layer 110 .
  • a first mask 131 is formed by etching the first mask layer(s) 130 using the photoresist pattern 140 as an etching mask.
  • the photoresist pattern 140 is then removed after the first mask 131 is formed, and the strain-relaxed buffer layer 110 is then etched using the first mask 131 as an etching mask.
  • the photoresist pattern 140 is removed after the trench 150 is formed in the strain-relaxed buffer layer 110 . In either of these cases, the sacrificial layer 120 is etched to form a sacrificial layer pattern 121 .
  • a device isolation layer 160 is formed in the trench 150 and on the first mask 131 .
  • the device isolation layer 160 may comprise a silicon oxide layer formed by a high-density plasma (HDP) process or a flowable chemical vapor deposition (FCVD) process.
  • HDP high-density plasma
  • FCVD flowable chemical vapor deposition
  • a device isolation region 161 is formed at the boundary between the first region I and the second region II by planarizing the device isolation layer 160 until an upper surface of the first mask 131 is exposed.
  • the planarizing of the device isolation layer 160 may be effected by an etch-back process or a chemical mechanical polishing (CMP) process. Also, at this time, the bottom surface of the device isolation region 161 may be disposed above the upper surface of the substrate 100 .
  • a second mask 170 is formed to cover the first mask 131 in the second region II and expose the first mask 131 in the first region I.
  • the second mask 170 may be a photoresist pattern, i.e., the second mask 170 may be formed by forming a layer of photoresist on the substrate 100 and then patterning the layer of photoresist.
  • the first mask 131 is removed from the first region I.
  • a first well 180 is formed in the strain-relaxed buffer layer 110 in the first region I, using a first ion implantation process.
  • the first ion implantation process may implant a p-type dopant, e.g., boron fluoride (BF2) or boron (B) into the strain-relaxed buffer layer 110 . That is, the first well 180 may be a p-type well.
  • the second mask pattern 170 may then be removed from the second region II.
  • the device at this point in the process may be subjected to a first heat treatment which causes the implanted (p-type) dopant to diffuse in the strain-relaxed buffer layer 110 in the second region II.
  • the first well 180 may be formed such that its lowermost boundary is disposed below the level of the bottom surface of the device isolation region 161 .
  • a third mask 190 is formed to cover the sacrificial layer pattern 121 in the first region I.
  • the third mask 190 is preferably of material having a good etching selectivity with respect to the second mask 170 , e.g., preferably consists of silicon oxide or a photoresist.
  • a second well 200 is formed in the strain-relaxed buffer layer 110 in the second region II, using a second ion implantation process.
  • the second ion implantation process may implant an n-type dopant, e.g., phosphorus (Ph) or arsenic (As), into the strain-relaxed buffer layer 110 .
  • the second well 200 may be an n-type well.
  • the third mask 190 may be removed after the second ion implantation process. Furthermore, at this point in the process, the structure is subjected to a second heat treatment to cause the implanted dopant (n-type) to diffuse in the strain-relaxed buffer layer 110 in the second region II. Accordingly, the second well 200 may be formed such that its lower boundary is disposed below level of the bottom surface of the device isolation region 161 .
  • the sacrificial layer pattern 121 is removed to expose the upper surface of the strain-relaxed buffer layer 110 in the first and second regions I and II.
  • the sacrificial layer pattern 121 may be removed by a wet etching process or a dry etching process.
  • a first channel layer 210 is formed on the first well 180 in the first region I and the second well 200 in the second region II.
  • the first channel layer 210 may comprise at least one material selected from the group consisting of a compound including a semiconductor from group 3, 4 or 5, silicon germanium (SiGe), and silicon (Si).
  • the first channel layer 210 may be formed by a selective epitaxial growth process which is not accompanied by any doping process (i.e., by any process of doping the material being grown with n-type or p-type dopants). In this case, the selective epitaxial growth process is preferably performed in a temperature range of 450-800° C.
  • the first channel layer 210 is preferably formed to a thickness of 25 to 35 nm. Finally, in this respect, the first channel layer 210 may be formed until its upper surface is disposed at a level higher than that of the upper surface of the device isolation region 161 .
  • the first channel layer 210 is planarized by a chemical mechanical polishing (CMP) process.
  • CMP chemical mechanical polishing
  • segments of the device isolation region 161 at opposite sides of each region I and II may be used as to stop the CMP process. That is, the device isolation region 161 may serve as a CMP etch stop layer in the CMP process.
  • the planarized upper surface of the first channel layer 210 is disposed at substantially the same level as, i.e., coplanar with, the upper surface of the adjacent device isolation region 161 .
  • the CMP process is skipped at this time, and the first channel layer 210 is planarized with a second channel layer 230 (later formed as described with reference to FIG. 15 ).
  • a fourth mask 220 is formed to cover the first channel layer 210 in the first region I and leave the second region II exposed.
  • the fourth mask 220 may be formed of at least one layer of material selected from the group consisting of silicon nitride, silicon oxynitride, and silicon oxide.
  • the first channel layer 210 is removed from the second region II by a wet etch process or a dry etch process using the fourth mask 220 as an etching mask, thereby exposing the upper surface of the second well 200 .
  • a second channel layer 230 is then formed on the second well 200 by a selective epitaxial growth process.
  • the second channel layer 230 may comprise at least one material selected from the group consisting of compounds including a semiconductor selected from group 3, 4 or 5, silicon germanium (SiGe), and germanium (Ge).
  • the second channel layer 230 may be formed by a selective epitaxial growth process which is not accompanied by any doping process, i.e., in which the material being grown is not doped with n-type or p-type dopants.
  • the selective epitaxial growth process is preferably performed in a temperature range of 450-800° C.
  • the second channel layer 230 is formed to a thickness of 25 to 35 nm.
  • the second channel layer 230 may be formed such that its upper surface is disposed at a level higher than that of the upper surface of the device isolation region 161 .
  • the fourth mask 220 is then removed by a dry etch process or a wet etch process.
  • the second channel layer 230 may be planarized by a chemical mechanical polishing (CMP) process.
  • CMP chemical mechanical polishing
  • the device isolation region 161 may serve as a CMP etch stop layer.
  • the planarized upper surface of the second channel layer 230 is disposed at substantially the same level as, i.e., coplanar with, the upper surface of the device isolation region 161 .
  • the first channel layer 210 may be planarized by the same CMP process such that its upper surface is disposed at substantially the same level as that of the upper surface of the second channel layer 230 .
  • a gate dielectric layer, a gate electrode structure, and source/drain regions are formed at each of the first and second regions I and II.
  • interconnections including contact plugs and bit lines, etc. may be formed to complete a semiconductor device according to the inventive concept.
  • the first well 180 is a p-type well, and an NMOS transistor is formed in the first well 180 . Furthermore, tensile stress is induced in the first channel layer 210 to increase the mobility of electrons which are the majority of charge carriers in an NMOS transistor. To this end, a lattice constant of material constituting the first channel layer 210 is lower than a lattice constant of material constituting the strain-relaxed buffer layer 110 (in a direction corresponding to the lengthwise direction of the channel of the NMOS transistor in the case in which the lattice structures are not cubic or in all directions in cases of cubic lattice structures).
  • the second well 200 is an n-type well
  • a PMOS transistor is formed in the second well 200
  • compressive stress is induced in the second channel layer 230 to increase the mobility of holes which are the majority of charge carriers in a PMOS transistor.
  • a lattice constant of material constituting the second channel layer 230 higher than a lattice constant of material constituting the strain-relaxed buffer layer 110 in a direction corresponding to the lengthwise direction of the channel of the PMOS transistor in the case in which the lattice structures are not cubic or in all directions in cases of cubic lattice structures).
  • the strain-relaxed buffer layer 110 , the first channel layer 210 , and the second channel layer 230 all comprise silicon germanium (SiGe) but have different lattice constants.
  • the strain-relaxed buffer layer 110 is formed of Si (1-x) Ge x
  • the first channel layer 210 comprises Si (1-y) Ge y
  • the second channel layer 230 comprises Si (1-z) Ge z , wherein y is greater than x such that lattice constant of the first channel layer 210 is lower than the lattice constant of the strain-relaxed buffer layer 110
  • z is greater than x such that the lattice constant of the second channel layer 230 is higher than the lattice constant of the strain-relaxed buffer layer 110 .
  • y and z are greater than or equal to 0 but less than or equal to 1, respectively, and x is greater than y but less than z. Accordingly, tensile stress is induced in the first channel layer 210 , and compressive stress is induced in the second channel layer 230 .
  • the composition of the silicon germanium of the first channel layer 210 is Si 0.8 Ge 0.2 and the composition of the silicon germanium of the strain-relaxed buffer layer 110 is Si 0.5 Ge 0.5 .
  • the composition of the silicon germanium of the second channel layer 230 is Si 0.2 Ge 0.8 and the composition of the silicon germanium of the strain-relaxed buffer layer 110 is Si 0.5 Ge 0.5 .
  • x minus y is in a range of 0.2-0.4 and z minus x is in a range of 0.2-0.4.
  • FIGS. 18 through 33 Another embodiment of a method of manufacturing a semiconductor device according to of the inventive concept will now be described with reference to FIGS. 18 through 33 .
  • the substrate 300 may be a rigid substrate, e.g., a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a silicon germanium substrate, an indium antimonide substrate, a lead telluride substrate, an indium arsenide substrate, an indium phosphorus substrate, a gallium arsenide substrate, or an antimony gallium substrate.
  • SOI silicon-on-insulator
  • a strain-relaxed buffer layer 310 is formed on the substrate 300 .
  • the strain-relaxed buffer layer 310 may comprise at least one material selected from the group consisting of compounds including a semiconductor from group 3, 4 or 5, silicon germanium (SiGe), and germanium (Ge). Examples of the compounds include gallium arsenic antimonide (GaAsSb), indium gallium arsenide (InGaAs), indium antimonide (InSb), gallium antimonide (GaSb), and indium arsenide (InAs).
  • the strain-relaxed buffer layer 310 may be formed by an epitaxial growth process which is accompanied by a doping process of introducing p-type dopants, e.g., boron fluoride (BF2) or boron (B), into the material being grown.
  • the epitaxial growth process may be carried out in a temperature range of 450-1200° C.
  • the strain-relaxed buffer layer 310 is preferably formed to a thickness of 300 to 1000 nm.
  • a sacrificial layer 320 is formed on the strain-relaxed buffer layer 310 .
  • the sacrificial layer 320 may comprise a silicon oxide layer, having a thickness of 10 to 100 nm, formed by a thermal oxidation process or chemical vapor deposition (CVD) process.
  • a first mask layer(s) 330 may be formed on the sacrificial layer 320 .
  • the first mask layer(s) 330 may comprise at least one layer of material selected from the group consisting of silicon nitride (SiN) and silicon oxynitride (SiON).
  • a photoresist pattern 340 is formed on the first mask layer(s) 330 .
  • the photoresist pattern 340 expose a portion of the upper surface of the first mask layer(s) 330 at a boundary between a first region I and a second region II of the device.
  • a trench 350 is formed in the strain-relaxed buffer layer 310 at the boundary between the first region I and the second region II.
  • the trench 350 may be formed by etching the first mask layer(s) 330 , the sacrificial layer 320 , and the strain-relaxed buffer layer 310 in a single etch process in which the photoresist pattern 340 serves as an etching mask. As a result, a first mask 331 is formed.
  • the photoresist pattern 340 may then be removed, i.e., after the trench 350 is formed in the strain-relaxed buffer layer 310 .
  • the photoresist pattern 340 may be removed after the first mask 331 is formed, and the sacrificial layer 320 and the strain-relaxed buffer layer 310 are etched by a second etching process in which the first mask 331 serves as an etching mask.
  • a device isolation layer 360 is formed in the trench 350 and on the first mask 331 .
  • the device isolation layer 360 may comprise a silicon oxide layer formed by a high-density plasma (HDP) process or a flowable chemical vapor deposition (FCVD) process.
  • HDP high-density plasma
  • FCVD flowable chemical vapor deposition
  • a device isolation region 361 is formed at the boundary between the first region I and the second region II.
  • the device isolation region 361 may be formed by planarizing the device isolation layer 360 until the upper surface of the first mask pattern 331 is exposed.
  • An etch-back process or a chemical mechanical polishing (CMP) process may be used to planarize the device isolation layer 360 .
  • the device isolation region 361 may be formed such that its bottom surface is above the upper surface of the substrate 300 .
  • a second mask 370 is formed to cover the first mask 331 in the first region I.
  • the second mask 170 may be comprise a photoresist.
  • the first mask 331 is then removed the second region II by a dry etch process or a wet etch process.
  • a well 380 is formed in the strain-relaxed buffer layer 310 in the second region II using a first ion implantation process.
  • the first ion implantation process may implant an n-type dopant, e.g., phosphorus (Ph) or arsenic (As), into the strain-relaxed buffer layer 310 .
  • the well 380 is an n-type well.
  • the second mask 370 and the first mask 331 are removed from the first region I after the first ion implantation process has been performed, and then the resulting structure is heat treated to cause the implanted dopants to diffuse in the strain-relaxed buffer layer 310 .
  • the lower boundary of the well 380 may be disposed at a level lower than the level of the bottom surface of the device isolation region 361 .
  • the sacrificial layer 320 is removed to expose the upper surface of the strain-relaxed buffer layer 310 in the first and second regions I and II.
  • the sacrificial layer 320 may be removed by a wet etching process or a dry etching process.
  • a first channel layer 390 is formed on the strain-relaxed buffer layer 310 in the first region I and the well 380 in the second region II.
  • the first channel layer 390 may comprise at least one material selected from the group consisting of compounds including a semiconductor from group 3, 4 or 5, silicon germanium (SiGe), and silicon (Si).
  • the first channel layer 390 may be formed by a selective epitaxial growth process which is not accompanied by any doping process, i.e., in which the material being grown is not doped with n-type or p-type dopants.
  • the selective epitaxial growth process may be performed in a temperature range of 450-800° C.
  • the first channel layer 390 is grown to a thickness of 25 to 35 nm.
  • the upper surface of the first channel layer 390 may be disposed at a level above the upper surface of the device isolation region 361 .
  • the first channel layer 390 may be planarized by a chemical mechanical polishing (CMP) process.
  • CMP chemical mechanical polishing
  • the device isolation region 361 may serve as a CMP etch stop layer.
  • the planarized upper surface of the first channel layer 390 is disposed at substantially the same level as, i.e., coplanar with, the upper surface of the device isolation region 161 .
  • the CMP process may be skipped at this point in the process and the first channel layer 390 may be simultaneously planarized with a second channel layer 410 (shown in FIG. 31 ) formed later on in the process.
  • a third mask 400 is formed to expose the second region II and cover the first channel layer 390 in the first region I.
  • the third mask 400 may be formed of at least one layer of material selected from the group consisting of silicon nitride, silicon oxynitride, and silicon oxide.
  • the first channel layer 390 is removed from the second region II by a wet etch process or a dry etch process using the third mask 400 as an etching mask. As a result, the upper surface of the well 380 is exposed.
  • a second channel layer 410 is formed on the second well 380 by a selective epitaxial growth process.
  • the second channel layer 410 may comprise at least one material selected from the group consisting of compounds including a semiconductor from group 3, 4 or 5, silicon germanium (SiGe), and germanium (Ge).
  • the second channel layer 410 may be formed by a selective epitaxial growth process which is not accompanied by any process of doping the material being grown with n-type or p-type dopants.
  • the selective epitaxial growth process may be performed in a temperature range of 450-800° C.
  • the second channel layer 410 is formed to a thickness of 25 to 35 nm.
  • the upper surface of the second channel layer 410 may be disposed at a level higher than that at which the upper surface of the device isolation region 361 is disposed.
  • the third mask 400 is removed by a dry etch process or a wet etch process.
  • the second channel layer 410 is planarized by a chemical mechanical polishing (CMP) process.
  • CMP chemical mechanical polishing
  • the device isolation region 361 may be serve as a CMP etch stop layer.
  • the planarized upper surface of the second channel layer 410 may be disposed at substantially the same level as, i.e., coplanar with, the upper surface of the device isolation region 361 .
  • the first channel layer 390 may be planarized at this point in the process along with the second channel layer 410 . In any case, the upper surfaces of the planarized first channel layer 390 second channel layer 410 may be coplanar.
  • a gate dielectric 420 may be formed directly on the first channel layer 390 and the second channel layer 410 .
  • the gate dielectric 420 may be formed of at least one layer of material selected from the group consisting of a silicon oxide layer and a high-k dielectric layer.
  • a first gate electrode 431 may be formed on the gate dielectric 420 in the first region I and a second gate electrode structure 432 may be formed on the gate dielectric 420 in the second region II.
  • a first source/drain region 441 may be formed at both sides of the first gate electrode structure 431 and a second source/drain region 442 may be formed at both sides of the second gate electrode structure 432 .
  • an interlayer dielectric layer may be formed on the substrate 300 over the first and second gate electrode structures 431 and 432 , and interconnections including contact plugs in the interlayer dielectric layer and bit lines, etc., may be formed to complete a semiconductor device according to the inventive concept.
  • the strain-relaxed buffer layer 310 has a p-type dopant
  • an NMOS transistor is formed in the strain-relaxed buffer layer 310 in the first region I
  • tensile stress is induced in the first channel layer 390 to increase the mobility of electrons which are the majority of charge carriers in an NMOS transistor.
  • a lattice constant of material constituting the first channel layer 390 is lower than a corresponding lattice constant of material constituting the strain-relaxed buffer layer 310 .
  • the well 380 is an n-type well
  • a PMOS transistor is formed in the well 380
  • compressive stress is induced in the second channel layer 410 to increase the mobility of holes which are the majority of charge carriers in a PMOS transistor.
  • the lattice constant of material constituting the second channel layer 410 is higher than a corresponding lattice constant of material constituting the strain-relaxed buffer layer 310 .
  • the strain-relaxed buffer layer 310 , the first channel layer 390 , and the second channel layer 410 are all formed of silicon germanium (SiGe) but have different lattice constants.
  • the strain-relaxed buffer layer 310 is formed of Si (1-x) Ge x
  • the first channel layer 390 comprises Si (1-y) Ge y
  • the second channel layer 410 comprises Si (1-z) Ge z
  • y is greater than x such that the lattice constant of the first channel layer 390 is lower than the lattice constant of the strain-relaxed buffer layer 310
  • z is greater than x such that the lattice constant of the second channel layer 410 is higher than the lattice constant of the strain-relaxed buffer layer 310 .
  • y and z are greater than or equal to 0 but less than or equal to 1, respectively, and x is greater than y but less than z. Accordingly, tensile stress is induced in the first channel layer 390 and compressive stress is induced in the second channel layer 410 .
  • the composition of the silicon germanium of the first channel layer 390 is Si 0.8 Ge 0.2 and the composition of the silicon germanium of the strain-relaxed buffer layer 310 is Si 0.5 Ge 0.5 .
  • the composition of the silicon germanium of the second channel layer 410 is Si 0.2 Ge 0.8 and the composition of the silicon germanium of the strain-relaxed buffer layer 310 is Si 0.5 Ge 0.5 .
  • x minus y is in a range of 0.2-0.4 and z minus x is also in a range of 0.2-0.4.
  • inventive concept and examples thereof have been described above in detail.
  • inventive concept may, however, be embodied in many different forms and should not be construed as being limited to the embodiments described above. Rather, these embodiments were described so that this disclosure is thorough and complete, and fully conveys the inventive concept to those skilled in the art. Thus, the true spirit and scope of the inventive concept is not limited by the embodiment and examples described above but by the following claims.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Element Separation (AREA)

Abstract

A semiconductor device includes a substrate, a strain-relaxed buffer layer on the substrate, at least one well in the strain-relaxed buffer layer, a first channel layer on the strain-relaxed buffer layer, and a second channel layer on the well. A lattice constant of material constituting the first well is less than a lattice constant of the material constituting the strain-relaxed buffer layer, but a lattice constant of material constituting the second well is greater than the lattice constant of the material constituting the strain-relaxed buffer layer.

Description

PRIORITY STATEMENT
This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2013-0065419, filed on Jun. 7, 2013, in the Korean Intellectual Property Office (KIPO), the contents of which are hereby incorporated by reference in their entirety.
BACKGROUND
1. Field
The inventive concept relates to a semiconductor device and to a method of manufacturing the same. More particularly, the inventive concept relates to a semiconductor device comprising a transistor having a channel region in which a stress has been induced and to a method of manufacturing the same.
2. Description of the Related Art
The width and length of a channel of a MOS transistor are becoming smaller (for both NMOS and PMOS transistors) in response to the growing demands for smaller semiconductor devices. However, it is well known that a reduction in the length of the channel of a MOS transistor increases the likelihood that the device will exhibit certain defective performance characteristics known as short-channel effects.
Improved transistor structures, such as an RCAT (Recess Channel Array Transistor) or a SRCAT (Sphere-shaped Recess Channel Array Transistor), have allowed for greater channel lengths without compromising an overall reduction in size of the transistor. Thus, semiconductor devices may employ an RCAT or SRCAT to prevent short-channel effects, i.e., to ensure a high degree of performance. Regardless, the performance of a MOS transistor is generally compromised if the width of the channel of the MOS transistor is reduced because narrower channels reduce the amount of current flowing through the channel. Ultimately, the scaling down of the MOS transistor will worsen the reliability of the semiconductor device.
With these considerations in mind, instead of looking at ways to further reduce the physical dimensions of the channel, some research in the field has been aimed at increasing the mobility of charge carriers (electrons in the NMOS transistor or holes in the PMOS transistor) by applying a tensile stress or a compressive stress to the channel.
SUMMARY
In accordance with one aspect of the inventive concept, there is provided a semiconductor device including a substrate, a strain-relaxed buffer layer on the substrate, a first well in the strain-relaxed buffer layer and located in a first region of the device, a second well in the strain-relaxed buffer layer and located in a second region of the device, a first channel layer on the first well, and a second channel layer on the second well, and in which a lattice constant of material constituting the first channel layer is less than a lattice constant of material constituting the strain-relaxed buffer layer, and a lattice constant of material constituting the second channel layer is greater than said lattice constant of the material constituting the strain-relaxed buffer layer.
In accordance with another aspect of the inventive concept, there is provided a semiconductor device including a substrate, a strain-relaxed buffer layer having a p-type impurity on the substrate, a first channel layer on the strain-relaxed buffer layer and located in a first region of the device, an n-type well in the strain-relaxed buffer layer and located in a second region of the device, a second channel layer on the n-type well, and a gate dielectric disposed directly on the first and second channel layers, and in which a lattice constant of material constituting the first channel layer is less than a lattice constant of material constituting the strain-relaxed buffer layer, but a lattice constant of material constituting the second channel layer is greater than said lattice constant of material constituting the strain-relaxed buffer layer.
In accordance with still another aspect of the inventive concept, there is provided a semiconductor device including a substrate, a strain-relaxed buffer layer on the substrate, an NMOS transistor having a tensile-stressed channel region on the strain-relaxed buffer layer, and a PMOS transistor having a tensile stressed channel region on the strain-relaxed buffer layer. A first channel layer is disposed on the strain-relaxed buffer layer and extends in a lengthwise direction between the source and drain of the NMOS transistor. A gate electrode of the NMOS transistor is disposed on the first channel layer. A second channel layer is disposed on the strain-relaxed buffer layer and extends in a lengthwise direction between the source and drain of the PMOS transistor. A gate electrode of the PMOS transistor is disposed on the first channel layer. A lattice constant of material constituting the first channel layer is less than a lattice constant of material constituting the strain-relaxed buffer layer. A lattice constant of material constituting the second channel layer is greater than the lattice constant of the material constituting the strain-relaxed buffer layer.
In accordance with another aspect of the inventive concept, there is provided a method of manufacturing a semiconductor device, which includes forming a strain-relaxed buffer layer on a substrate, forming a first well in the strain-relaxed buffer layer in a first region, forming a second well in the strain-relaxed buffer layer in a second region, forming a first channel layer simultaneously on the first well and the second well and wherein the first channel layer is formed of a material having a lattice constant less than that of a lattice constant of material constituting the strain-relaxed buffer layer, forming a first mask that covers the first channel layer on the first well and exposes the first channel layer on the second well, removing the first channel layer from over the second well, forming a second channel layer on the second well and wherein the second channel layer is formed of a material having a lattice constant greater than that of material constituting the strain-relaxed buffer layer, and removing the first mask.
In accordance with another aspect of the inventive concept, there is provided a method of manufacturing a semiconductor device, which includes providing a substrate, forming a strain-relaxed buffer layer on the substrate, forming an n-type well in the strain-relaxed buffer layer, forming a first channel layer on the strain-relaxed buffer layer in a first region and wherein the first channel layer is formed of a material having a lattice constant less than that of a lattice constant of material constituting the strain-relaxed buffer layer, forming a second channel layer on the n-type well in a second region and wherein the second channel layer is formed of a material having a lattice constant greater than that of material constituting the strain-relaxed buffer layer, and forming a gate dielectric layer directly on the first and second channel layers.
BRIEF DESCRIPTION OF THE DRAWINGS
The foregoing and other features and advantages of the inventive concept will be apparent from the more detailed description of preferred embodiments, as illustrated in the accompanying drawings. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the inventive concept.
FIGS. 1 through 17 illustrate an embodiment of a method of manufacturing a semiconductor device according to the inventive concept, wherein each of FIGS. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17 is a cross-sectional view of the device during the course of its manufacture.
FIGS. 18 through 33 illustrate another embodiment of a method of manufacturing a semiconductor device according to f the inventive concept, wherein each of FIGS. 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 and 32 is a cross-sectional view of the device during the course of its manufacture and FIG. 33 is a cross-sectional view of the device itself.
 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Various embodiments and examples of embodiments of the inventive concept will be described more fully hereinafter with reference to the accompanying drawings. In the drawings, the sizes and relative sizes and shapes of elements, layers and regions, such as implanted regions, shown in section may be exaggerated for clarity. In particular, the cross-sectional illustrations of the semiconductor devices and intermediate structures fabricated during the course of their manufacture are schematic. Also, like numerals are used to designate like elements throughout the drawings.
Furthermore, spatially relative terms, such as “upper,” and “lower” are used to describe an element's and/or feature's relationship to another element(s) and/or feature(s) as illustrated in the figures. Thus, the spatially relative terms may apply to orientations in use which differ from the orientation depicted in the figures. Obviously, though, all such spatially relative terms refer to the orientation shown in the drawings for ease of description and are not necessarily limiting as embodiments according to the inventive concept can assume orientations different than those illustrated in the drawings when in use. In addition, the terms “top” or “bottom” as used to describe a surface generally refer not only to the orientation depicted in the drawings but to the fact that the surface is the uppermost or bottommost surface in the orientation depicted, as would be clear from the drawings and context of the written description.
It will also be understood that when an element or layer is referred to as being “on” or “connected to” another element or layer, it can be directly on or directly connected to the other element or layer or an intervening element(s) or layer(s) may be present. In contrast, when an element or layer is referred to as being “directly on” or “directly connected to” another element or layer, there is no intervening element or layer present. Likewise, when an element is referred to as being “between” other elements, it can be in contact with the other elements or an intervening element(s) may be present.
Other terminology used herein for the purpose of describing particular examples or embodiments of the inventive concept is to be taken in context. For example, the terms “comprises” or “comprising” when used in this specification specifies the presence of stated features or processes but does not preclude the presence or additional features or processes. The term “strain-relaxed” as used to describe a layer will be understood as generally referring to the fact that the layer has no intrinsic stress, i.e., no internal stress as the result of the way in which it was produced. That is, the term “strain-relaxed” will be understood as meaning substantially stress free. Furthermore, a description of the inventive concept includes examples in which the crystal lattice of material constituting key layers has a cubic lattice structure and so, the term “a lattice constant” may be understood as referring to all of the constants of the units making up the crystal lattice.
A first embodiment of a method of manufacturing a semiconductor device according to the inventive concept will now be described in detail with reference to FIGS. 1 through 17.
Referring first to FIG. 1, a substrate 100 is provided. The substrate 100 may be a rigid substrate, e.g., a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a silicon germanium substrate, an indium antimonide substrate, a lead telluride substrate, an indium arsenide substrate, an indium phosphorus substrate, a gallium arsenide substrate, or an antimony gallium substrate.
A strain-relaxed buffer layer 110 is formed on the substrate 100. The strain-relaxed buffer layer 110 may comprise at least one material selected from the group consisting of compounds including a semiconductor from group 3, 4 or 5, silicon germanium (SiGe), and germanium (Ge). Compounds including a semiconductor from group 3, 4 or 5 include gallium arsenic antimonide (GaAsSb), indium gallium arsenide (InGaAs), indium antimonide (InSb), gallium antimonide (GaSb), and indium arsenide (InAs). The strain-relaxed buffer layer 110 may be formed by an epitaxial growth process which is not accompanied by any doping process (i.e., without doping the epitaxially grown material with n-type or p-type dopants). Such a process may be conducted in a temperature range of 450-1200° C. Also, the strain-relaxed buffer layer 110 is preferably formed to a thickness of 300 to 1000 nm.
Referring to FIG. 2, a sacrificial layer 120 is formed on the strain-relaxed buffer layer 110. The sacrificial layer 120 may comprise a silicon oxide layer, having a thickness of 10 to 100 nm, formed by a thermal oxidation process or chemical vapor deposition (CVD) process.
Then a first mask layer(s) 130 is formed on the sacrificial layer 120. The first mask layer(s) 130 may comprise at least one layer of material selected from the group consisting of silicon nitride (SiN) and silicon oxynitride (SiON).
Referring to FIG. 3, a photoresist pattern 140 is formed on the first mask layer(s) 130. The photoresist pattern 140 exposes a portion of the upper surface of the first mask layer(s) 130 formed at a boundary between a first region I and a second region II of the device.
Referring to FIG. 4, a trench 150 is formed in the strain-relaxed buffer layer 110 at the boundary between the first region I and the second region II. In this embodiment, the trench 150 is formed by etching the first mask layer(s) 130, the sacrificial layer 120, and the strain-relaxed buffer layer 110. For example, a first mask 131 is formed by etching the first mask layer(s) 130 using the photoresist pattern 140 as an etching mask. The photoresist pattern 140 is then removed after the first mask 131 is formed, and the strain-relaxed buffer layer 110 is then etched using the first mask 131 as an etching mask. Alternatively, the photoresist pattern 140 is removed after the trench 150 is formed in the strain-relaxed buffer layer 110. In either of these cases, the sacrificial layer 120 is etched to form a sacrificial layer pattern 121.
Referring to FIG. 5, a device isolation layer 160 is formed in the trench 150 and on the first mask 131. The device isolation layer 160 may comprise a silicon oxide layer formed by a high-density plasma (HDP) process or a flowable chemical vapor deposition (FCVD) process.
Referring to FIG. 6, a device isolation region 161 is formed at the boundary between the first region I and the second region II by planarizing the device isolation layer 160 until an upper surface of the first mask 131 is exposed. The planarizing of the device isolation layer 160 may be effected by an etch-back process or a chemical mechanical polishing (CMP) process. Also, at this time, the bottom surface of the device isolation region 161 may be disposed above the upper surface of the substrate 100.
Referring to FIG. 7, a second mask 170 is formed to cover the first mask 131 in the second region II and expose the first mask 131 in the first region I. The second mask 170 may be a photoresist pattern, i.e., the second mask 170 may be formed by forming a layer of photoresist on the substrate 100 and then patterning the layer of photoresist.
Referring to FIG. 8, the first mask 131 is removed from the first region I. Then a first well 180 is formed in the strain-relaxed buffer layer 110 in the first region I, using a first ion implantation process. The first ion implantation process may implant a p-type dopant, e.g., boron fluoride (BF2) or boron (B) into the strain-relaxed buffer layer 110. That is, the first well 180 may be a p-type well. The second mask pattern 170 may then be removed from the second region II. In addition, the device at this point in the process may be subjected to a first heat treatment which causes the implanted (p-type) dopant to diffuse in the strain-relaxed buffer layer 110 in the second region II. Accordingly, the first well 180 may be formed such that its lowermost boundary is disposed below the level of the bottom surface of the device isolation region 161.
Referring to FIG. 9, after the second mask 170 has been removed from the second region II, a third mask 190 is formed to cover the sacrificial layer pattern 121 in the first region I. The third mask 190 is preferably of material having a good etching selectivity with respect to the second mask 170, e.g., preferably consists of silicon oxide or a photoresist. Then a second well 200 is formed in the strain-relaxed buffer layer 110 in the second region II, using a second ion implantation process. The second ion implantation process may implant an n-type dopant, e.g., phosphorus (Ph) or arsenic (As), into the strain-relaxed buffer layer 110. That is, the second well 200 may be an n-type well. The third mask 190 may be removed after the second ion implantation process. Furthermore, at this point in the process, the structure is subjected to a second heat treatment to cause the implanted dopant (n-type) to diffuse in the strain-relaxed buffer layer 110 in the second region II. Accordingly, the second well 200 may be formed such that its lower boundary is disposed below level of the bottom surface of the device isolation region 161.
Referring to FIG. 10, the sacrificial layer pattern 121 is removed to expose the upper surface of the strain-relaxed buffer layer 110 in the first and second regions I and II. The sacrificial layer pattern 121 may be removed by a wet etching process or a dry etching process.
Referring to FIG. 11, a first channel layer 210 is formed on the first well 180 in the first region I and the second well 200 in the second region II. The first channel layer 210 may comprise at least one material selected from the group consisting of a compound including a semiconductor from group 3, 4 or 5, silicon germanium (SiGe), and silicon (Si). The first channel layer 210 may be formed by a selective epitaxial growth process which is not accompanied by any doping process (i.e., by any process of doping the material being grown with n-type or p-type dopants). In this case, the selective epitaxial growth process is preferably performed in a temperature range of 450-800° C. Furthermore, the first channel layer 210 is preferably formed to a thickness of 25 to 35 nm. Finally, in this respect, the first channel layer 210 may be formed until its upper surface is disposed at a level higher than that of the upper surface of the device isolation region 161.
Referring to FIG. 12, in one example of this embodiment, the first channel layer 210 is planarized by a chemical mechanical polishing (CMP) process. In this respect, segments of the device isolation region 161 at opposite sides of each region I and II may be used as to stop the CMP process. That is, the device isolation region 161 may serve as a CMP etch stop layer in the CMP process. In this case, the planarized upper surface of the first channel layer 210 is disposed at substantially the same level as, i.e., coplanar with, the upper surface of the adjacent device isolation region 161. In another example of this embodiment, the CMP process is skipped at this time, and the first channel layer 210 is planarized with a second channel layer 230 (later formed as described with reference to FIG. 15).
Referring to FIG. 13, a fourth mask 220 is formed to cover the first channel layer 210 in the first region I and leave the second region II exposed. The fourth mask 220 may be formed of at least one layer of material selected from the group consisting of silicon nitride, silicon oxynitride, and silicon oxide.
Referring to FIG. 14, the first channel layer 210 is removed from the second region II by a wet etch process or a dry etch process using the fourth mask 220 as an etching mask, thereby exposing the upper surface of the second well 200.
Referring to FIG. 15, a second channel layer 230 is then formed on the second well 200 by a selective epitaxial growth process. The second channel layer 230 may comprise at least one material selected from the group consisting of compounds including a semiconductor selected from group 3, 4 or 5, silicon germanium (SiGe), and germanium (Ge). The second channel layer 230 may be formed by a selective epitaxial growth process which is not accompanied by any doping process, i.e., in which the material being grown is not doped with n-type or p-type dopants. In this case, the selective epitaxial growth process is preferably performed in a temperature range of 450-800° C. Preferably, the second channel layer 230 is formed to a thickness of 25 to 35 nm. Finally, in this respect, the second channel layer 230 may be formed such that its upper surface is disposed at a level higher than that of the upper surface of the device isolation region 161.
Referring to FIG. 16, the fourth mask 220 is then removed by a dry etch process or a wet etch process.
Referring to FIG. 17, the second channel layer 230 may be planarized by a chemical mechanical polishing (CMP) process. During the CMP process, the device isolation region 161 may serve as a CMP etch stop layer. In this case, the planarized upper surface of the second channel layer 230 is disposed at substantially the same level as, i.e., coplanar with, the upper surface of the device isolation region 161. Also, as was mentioned earlier, the first channel layer 210 may be planarized by the same CMP process such that its upper surface is disposed at substantially the same level as that of the upper surface of the second channel layer 230.
Next, conventional processes per se for completing transistors of the device are performed. For example, a gate dielectric layer, a gate electrode structure, and source/drain regions are formed at each of the first and second regions I and II. In addition, interconnections including contact plugs and bit lines, etc., may be formed to complete a semiconductor device according to the inventive concept.
In an example of a semiconductor device formed according to the above-described method, the first well 180 is a p-type well, and an NMOS transistor is formed in the first well 180. Furthermore, tensile stress is induced in the first channel layer 210 to increase the mobility of electrons which are the majority of charge carriers in an NMOS transistor. To this end, a lattice constant of material constituting the first channel layer 210 is lower than a lattice constant of material constituting the strain-relaxed buffer layer 110 (in a direction corresponding to the lengthwise direction of the channel of the NMOS transistor in the case in which the lattice structures are not cubic or in all directions in cases of cubic lattice structures).
Furthermore, in this example, the second well 200 is an n-type well, a PMOS transistor is formed in the second well 200, and compressive stress is induced in the second channel layer 230 to increase the mobility of holes which are the majority of charge carriers in a PMOS transistor. To this end, a lattice constant of material constituting the second channel layer 230 higher than a lattice constant of material constituting the strain-relaxed buffer layer 110 (in a direction corresponding to the lengthwise direction of the channel of the PMOS transistor in the case in which the lattice structures are not cubic or in all directions in cases of cubic lattice structures).
Referring still to FIG. 17, in one embodiment, the strain-relaxed buffer layer 110, the first channel layer 210, and the second channel layer 230 all comprise silicon germanium (SiGe) but have different lattice constants. For example, the strain-relaxed buffer layer 110 is formed of Si(1-x)Gex, the first channel layer 210 comprises Si(1-y)Gey and the second channel layer 230 comprises Si(1-z)Gez, wherein y is greater than x such that lattice constant of the first channel layer 210 is lower than the lattice constant of the strain-relaxed buffer layer 110, and z is greater than x such that the lattice constant of the second channel layer 230 is higher than the lattice constant of the strain-relaxed buffer layer 110. In other words, in an example of this embodiment, y and z are greater than or equal to 0 but less than or equal to 1, respectively, and x is greater than y but less than z. Accordingly, tensile stress is induced in the first channel layer 210, and compressive stress is induced in the second channel layer 230.
It was verified experimentally that the higher the tensile stress induced in the first channel layer 210 was, the fewer were the stacking faults and dislocation defects, when the difference of germanium concentration between the first channel layer 210 and the strain-relaxed buffer layer 110 is about 30%. As an example of such a case, the composition of the silicon germanium of the first channel layer 210 is Si0.8Ge0.2 and the composition of the silicon germanium of the strain-relaxed buffer layer 110 is Si0.5Ge0.5. It was also verified experimentally that the higher the compressive stress induced in the second channel layer 230 was, the fewer were the stacking faults and the dislocation defects, when the difference of germanium concentration between the second channel layer 230 and the strain-relaxed buffer layer 110 is about 30%. As an example of such a case, the composition of the silicon germanium of the second channel layer 230 is Si0.2Ge0.8 and the composition of the silicon germanium of the strain-relaxed buffer layer 110 is Si0.5Ge0.5. In other words, x minus y is in a range of 0.2-0.4 and z minus x is in a range of 0.2-0.4.
Another embodiment of a method of manufacturing a semiconductor device according to of the inventive concept will now be described with reference to FIGS. 18 through 33.
Referring first to FIG. 18, a substrate 300 is provided. The substrate 300 may be a rigid substrate, e.g., a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a silicon germanium substrate, an indium antimonide substrate, a lead telluride substrate, an indium arsenide substrate, an indium phosphorus substrate, a gallium arsenide substrate, or an antimony gallium substrate.
A strain-relaxed buffer layer 310 is formed on the substrate 300. The strain-relaxed buffer layer 310 may comprise at least one material selected from the group consisting of compounds including a semiconductor from group 3, 4 or 5, silicon germanium (SiGe), and germanium (Ge). Examples of the compounds include gallium arsenic antimonide (GaAsSb), indium gallium arsenide (InGaAs), indium antimonide (InSb), gallium antimonide (GaSb), and indium arsenide (InAs). The strain-relaxed buffer layer 310 may be formed by an epitaxial growth process which is accompanied by a doping process of introducing p-type dopants, e.g., boron fluoride (BF2) or boron (B), into the material being grown. In this case, the epitaxial growth process may be carried out in a temperature range of 450-1200° C. Also, the strain-relaxed buffer layer 310 is preferably formed to a thickness of 300 to 1000 nm.
Referring to FIG. 19, a sacrificial layer 320 is formed on the strain-relaxed buffer layer 310. The sacrificial layer 320 may comprise a silicon oxide layer, having a thickness of 10 to 100 nm, formed by a thermal oxidation process or chemical vapor deposition (CVD) process.
A first mask layer(s) 330 may be formed on the sacrificial layer 320. The first mask layer(s) 330 may comprise at least one layer of material selected from the group consisting of silicon nitride (SiN) and silicon oxynitride (SiON).
Referring to FIG. 20, a photoresist pattern 340 is formed on the first mask layer(s) 330. The photoresist pattern 340 expose a portion of the upper surface of the first mask layer(s) 330 at a boundary between a first region I and a second region II of the device.
Referring to FIG. 21, a trench 350 is formed in the strain-relaxed buffer layer 310 at the boundary between the first region I and the second region II. The trench 350 may be formed by etching the first mask layer(s) 330, the sacrificial layer 320, and the strain-relaxed buffer layer 310 in a single etch process in which the photoresist pattern 340 serves as an etching mask. As a result, a first mask 331 is formed. The photoresist pattern 340 may then be removed, i.e., after the trench 350 is formed in the strain-relaxed buffer layer 310. Alternatively, the photoresist pattern 340 may be removed after the first mask 331 is formed, and the sacrificial layer 320 and the strain-relaxed buffer layer 310 are etched by a second etching process in which the first mask 331 serves as an etching mask.
Referring to FIG. 22, a device isolation layer 360 is formed in the trench 350 and on the first mask 331. The device isolation layer 360 may comprise a silicon oxide layer formed by a high-density plasma (HDP) process or a flowable chemical vapor deposition (FCVD) process.
Referring to FIG. 23, a device isolation region 361 is formed at the boundary between the first region I and the second region II. The device isolation region 361 may be formed by planarizing the device isolation layer 360 until the upper surface of the first mask pattern 331 is exposed. An etch-back process or a chemical mechanical polishing (CMP) process may be used to planarize the device isolation layer 360. Furthermore, the device isolation region 361 may be formed such that its bottom surface is above the upper surface of the substrate 300.
Referring to FIG. 24, a second mask 370 is formed to cover the first mask 331 in the first region I. The second mask 170 may be comprise a photoresist. The first mask 331 is then removed the second region II by a dry etch process or a wet etch process. Next, a well 380 is formed in the strain-relaxed buffer layer 310 in the second region II using a first ion implantation process. The first ion implantation process may implant an n-type dopant, e.g., phosphorus (Ph) or arsenic (As), into the strain-relaxed buffer layer 310. In this case, the well 380 is an n-type well. Furthermore, the second mask 370 and the first mask 331 are removed from the first region I after the first ion implantation process has been performed, and then the resulting structure is heat treated to cause the implanted dopants to diffuse in the strain-relaxed buffer layer 310. Accordingly, the lower boundary of the well 380 may be disposed at a level lower than the level of the bottom surface of the device isolation region 361.
Referring to FIG. 25, the sacrificial layer 320 is removed to expose the upper surface of the strain-relaxed buffer layer 310 in the first and second regions I and II. The sacrificial layer 320 may be removed by a wet etching process or a dry etching process.
Referring to FIG. 26, a first channel layer 390 is formed on the strain-relaxed buffer layer 310 in the first region I and the well 380 in the second region II. The first channel layer 390 may comprise at least one material selected from the group consisting of compounds including a semiconductor from group 3, 4 or 5, silicon germanium (SiGe), and silicon (Si). The first channel layer 390 may be formed by a selective epitaxial growth process which is not accompanied by any doping process, i.e., in which the material being grown is not doped with n-type or p-type dopants. The selective epitaxial growth process may be performed in a temperature range of 450-800° C. Preferably, the first channel layer 390 is grown to a thickness of 25 to 35 nm. Also, using this technique, the upper surface of the first channel layer 390 may be disposed at a level above the upper surface of the device isolation region 361.
Referring to FIG. 27, the first channel layer 390 may be planarized by a chemical mechanical polishing (CMP) process. In this case, the device isolation region 361 may serve as a CMP etch stop layer. In this case, the planarized upper surface of the first channel layer 390 is disposed at substantially the same level as, i.e., coplanar with, the upper surface of the device isolation region 161. Alternatively, the CMP process may be skipped at this point in the process and the first channel layer 390 may be simultaneously planarized with a second channel layer 410 (shown in FIG. 31) formed later on in the process.
Referring to FIG. 28, a third mask 400 is formed to expose the second region II and cover the first channel layer 390 in the first region I. The third mask 400 may be formed of at least one layer of material selected from the group consisting of silicon nitride, silicon oxynitride, and silicon oxide.
Referring to FIG. 29, the first channel layer 390 is removed from the second region II by a wet etch process or a dry etch process using the third mask 400 as an etching mask. As a result, the upper surface of the well 380 is exposed.
Referring to FIG. 30, a second channel layer 410 is formed on the second well 380 by a selective epitaxial growth process. The second channel layer 410 may comprise at least one material selected from the group consisting of compounds including a semiconductor from group 3, 4 or 5, silicon germanium (SiGe), and germanium (Ge). The second channel layer 410 may be formed by a selective epitaxial growth process which is not accompanied by any process of doping the material being grown with n-type or p-type dopants. The selective epitaxial growth process may be performed in a temperature range of 450-800° C. Preferably, the second channel layer 410 is formed to a thickness of 25 to 35 nm. Also, using this technique, the upper surface of the second channel layer 410 may be disposed at a level higher than that at which the upper surface of the device isolation region 361 is disposed.
Referring to FIG. 31, the third mask 400 is removed by a dry etch process or a wet etch process.
Referring to FIG. 32, the second channel layer 410 is planarized by a chemical mechanical polishing (CMP) process. Once again, in this CMP process, the device isolation region 361 may be serve as a CMP etch stop layer. As a result, the planarized upper surface of the second channel layer 410 may be disposed at substantially the same level as, i.e., coplanar with, the upper surface of the device isolation region 361. Furthermore, as was mentioned earlier, the first channel layer 390 may be planarized at this point in the process along with the second channel layer 410. In any case, the upper surfaces of the planarized first channel layer 390 second channel layer 410 may be coplanar.
Referring to FIG. 33, a gate dielectric 420 may be formed directly on the first channel layer 390 and the second channel layer 410. In this case, the gate dielectric 420 may be formed of at least one layer of material selected from the group consisting of a silicon oxide layer and a high-k dielectric layer. A first gate electrode 431 may be formed on the gate dielectric 420 in the first region I and a second gate electrode structure 432 may be formed on the gate dielectric 420 in the second region II. Still further, a first source/drain region 441 may be formed at both sides of the first gate electrode structure 431 and a second source/drain region 442 may be formed at both sides of the second gate electrode structure 432.
Next, an interlayer dielectric layer may be formed on the substrate 300 over the first and second gate electrode structures 431 and 432, and interconnections including contact plugs in the interlayer dielectric layer and bit lines, etc., may be formed to complete a semiconductor device according to the inventive concept.
In an example of this embodiment, the strain-relaxed buffer layer 310 has a p-type dopant, an NMOS transistor is formed in the strain-relaxed buffer layer 310 in the first region I, and tensile stress is induced in the first channel layer 390 to increase the mobility of electrons which are the majority of charge carriers in an NMOS transistor. To this end, a lattice constant of material constituting the first channel layer 390 is lower than a corresponding lattice constant of material constituting the strain-relaxed buffer layer 310.
Also, in this example, the well 380 is an n-type well, a PMOS transistor is formed in the well 380, and compressive stress is induced in the second channel layer 410 to increase the mobility of holes which are the majority of charge carriers in a PMOS transistor. To this end, the lattice constant of material constituting the second channel layer 410 is higher than a corresponding lattice constant of material constituting the strain-relaxed buffer layer 310.
Still further, in one embodiment, the strain-relaxed buffer layer 310, the first channel layer 390, and the second channel layer 410 are all formed of silicon germanium (SiGe) but have different lattice constants. For example, the strain-relaxed buffer layer 310 is formed of Si(1-x)Gex, the first channel layer 390 comprises Si(1-y)Gey and the second channel layer 410 comprises Si(1-z)Gez, wherein y is greater than x such that the lattice constant of the first channel layer 390 is lower than the lattice constant of the strain-relaxed buffer layer 310, and z is greater than x such that the lattice constant of the second channel layer 410 is higher than the lattice constant of the strain-relaxed buffer layer 310. That is, y and z are greater than or equal to 0 but less than or equal to 1, respectively, and x is greater than y but less than z. Accordingly, tensile stress is induced in the first channel layer 390 and compressive stress is induced in the second channel layer 410.
It was verified experimentally that the higher tensile stress induced in the first channel layer 390 was, the fewer were the stacking faults and the dislocation defects, when the difference of germanium concentration between the first channel layer 390 and the strain-relaxed buffer layer 310 is about 30%. As an example of such a case, the composition of the silicon germanium of the first channel layer 390 is Si0.8Ge0.2 and the composition of the silicon germanium of the strain-relaxed buffer layer 310 is Si0.5Ge0.5. It was also verified experimentally that the higher compressive stress induced in the second channel layer 410 was, the fewer were the stacking faults and the dislocation defects, when the difference of germanium concentration between the second channel layer 390 and the strain-relaxed buffer layer 310 is about 30%. As an example of such a case, the composition of the silicon germanium of the second channel layer 410 is Si0.2Ge0.8 and the composition of the silicon germanium of the strain-relaxed buffer layer 310 is Si0.5Ge0.5. In other words, x minus y is in a range of 0.2-0.4 and z minus x is also in a range of 0.2-0.4.
Finally, embodiments of the inventive concept and examples thereof have been described above in detail. The inventive concept may, however, be embodied in many different forms and should not be construed as being limited to the embodiments described above. Rather, these embodiments were described so that this disclosure is thorough and complete, and fully conveys the inventive concept to those skilled in the art. Thus, the true spirit and scope of the inventive concept is not limited by the embodiment and examples described above but by the following claims.

Claims (17)

What is claimed is:
1. A semiconductor device, comprising:
a substrate;
a strain-relaxed buffer layer having a p-type impurity on the substrate;
a first channel layer on the strain-relaxed buffer layer and located in a first region of the device;
an n-type well in the strain-relaxed buffer layer and located in a second region of the device;
a second channel layer on an upper bound of the n-type well;
a gate dielectric disposed directly on the first and second channel layers;
a device isolation region comprising insulation material in the strain-relaxed buffer layer at a boundary between the first region and the second region; and
wherein a lattice constant of the first channel layer is less than a lattice constant of the strain-relaxed buffer layer, but a lattice constant of the second channel layer is greater than said lattice constant of the strain-relaxed buffer layer,
the bottom surface of the device isolation region is disposed above the upper surface of the substrate, and
the lowermost bound of said n-type well is disposed at a level above the substrate and below the level of the bottom surface of the device isolation region.
2. The semiconductor device as claimed in claim 1, wherein the strain-relaxed buffer layer comprises at least one material selected from the group consisting of compounds including a semiconductor from group 3, 4 or 5, silicon germanium (SiGe), and germanium (Ge).
3. The semiconductor device as claimed in claim 1, wherein the first and second channel layers each have a thickness of 25 to 35 nm.
4. The semiconductor device as claimed in claim 1, wherein the strain-relaxed buffer layer comprises Si(1-x)Gex, the first channel layer comprises Si(1-y)Gey, and the second channel layer comprises Si(1-z)Gez,
wherein y and z are greater than or equal to 0 but less than or equal to 1; and
wherein x is greater than y but less than z.
5. A semiconductor device, comprising:
a substrate;
a strain-relaxed buffer layer having a p-type impurity on the substrate;
a source and a drain of an NMOS transistor, a first channel layer disposed on the strain-relaxed buffer layer and extending in a lengthwise direction between the source and drain of the NMOS transistor, and a gate electrode of the NMOS transistor disposed on the first channel layer; and
a source and a drain of a PMOS transistor, a second channel layer disposed on the strain-relaxed buffer layer and extending in a lengthwise direction between the source and drain of the PMOS transistor, and a gate electrode of the PMOS transistor disposed on the second channel layer, and
wherein a lattice constant of the first channel layer is less than a lattice constant of the strain-relaxed buffer layer, and a lattice constant of the second channel layer is greater than said lattice constant of the strain-relaxed buffer layer, and
the source and drain of the NMOS transistor, the source and drain of the PMOS transistor, the first channel layer, and the second channel layer have upper surfaces, respectively, that are coplanar,
the semiconductor device further comprises a device isolation region comprising insulation material in the strain-relaxed buffer layer at a boundary between the NMOS transistor and the PMOS transistor, and
the strain-relaxed buffer layer has at least one well containing a dopant of a respective conductivity type, a respective one of said channel layers is disposed on each said well, the bottom surface of the device isolation region is disposed above the upper surface of the substrate, and the lowermost bound of each said well is disposed at a level below the level of the bottom surface of the device isolation region.
6. The semiconductor device as claimed in claim 5, wherein the strain-relaxed buffer layer comprises at least one material selected from the group consisting of compounds including a semiconductor from group 3, 4 or 5, silicon germanium (SiGe), and germanium (Ge).
7. The semiconductor device as claimed in claim 6, wherein the first channel layer comprises at least one material selected from the group consisting of compounds including a semiconductor from group 3, 4 or 5, silicon germanium (SiGe), and silicon (Si).
8. The semiconductor device as claimed in claim 6, wherein the second channel layer comprises at least one material selected from the group consisting of compounds including a semiconductor from group 3, 4 or 5, silicon germanium (SiGe), and germanium (Ge).
9. The semiconductor device as claimed in claim 5, wherein the strain-relaxed buffer layer comprises Si(1-x)GEx, the first channel layer comprises Si(1-y)Gey, and the second channel layer comprises Si(1-z)Gez,
wherein y and z are greater than or equal to 0 but less than or equal to 1, respectively, and
x is greater than y but less than z.
10. The semiconductor device as claimed in claim 9, wherein x minus y is in a range of 0.2 to 0.4.
11. The semiconductor device as claimed in claim 1, wherein the strain-relaxed buffer layer comprises at least one material selected from the group consisting of gallium arsenic antimonide (GaAsSb), indium gallium arsenide (InGaAs), indium antimonide (InSb), gallium antimonide (GaSb), and indium arsenide (InAs).
12. The semiconductor device as claimed in claim 4, wherein x minus y is in a range of 0.2 to 0.4, and z-x is a range of 0.2 to 0.4.
13. The semiconductor device as claimed in claim 5, wherein the strain-relaxed buffer layer comprises at least one material selected from the group consisting of gallium arsenic antimonide (GaAsSb), indium gallium arsenide (InGaAs), indium antimonide (InSb), gallium antimonide (GaSb), and indium arsenide (InAs).
14. The semiconductor device as claimed in claim 5, wherein the strain-relaxed buffer layer has at least one well containing a dopant of a respective conductivity type,
a respective one of said channel layers is disposed on each said well, the bottom surface of the device isolation region is disposed above the upper surface of the substrate, and
the lowermost bound of each said well is disposed at a level above the substrate and below the level of the bottom surface of the device isolation region.
15. The semiconductor device as claimed in claim 10, wherein z minus x is in a range of 0.2 to 0.4.
16. The semiconductor device as claimed in claim 1, wherein the first channel layer, and the second channel layer and the device isolation layer have upper surfaces, respectively, that are coplanar.
17. The semiconductor device as claimed in claim 1, wherein the upper bound of the n-type well and the lowermost bound of the second channel region are both disposed at a level below that of the upper surface of the device isolation region.
US14/289,672 2013-06-07 2014-05-29 Semiconductor device having strain-relaxed buffer layer and method of manufacturing the same Active US9425198B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/212,367 US20160329333A1 (en) 2013-06-07 2016-07-18 Semiconductor device having strain-relaxed buffer layer and method of manufacturing the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020130065419A KR102069275B1 (en) 2013-06-07 2013-06-07 Semiconductor device having strained channel layer and method of manufacturing the same
KR10-2013-0065419 2013-06-07

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US15/212,367 Division US20160329333A1 (en) 2013-06-07 2016-07-18 Semiconductor device having strain-relaxed buffer layer and method of manufacturing the same

Publications (2)

Publication Number Publication Date
US20140361378A1 US20140361378A1 (en) 2014-12-11
US9425198B2 true US9425198B2 (en) 2016-08-23

Family

ID=52004756

Family Applications (2)

Application Number Title Priority Date Filing Date
US14/289,672 Active US9425198B2 (en) 2013-06-07 2014-05-29 Semiconductor device having strain-relaxed buffer layer and method of manufacturing the same
US15/212,367 Abandoned US20160329333A1 (en) 2013-06-07 2016-07-18 Semiconductor device having strain-relaxed buffer layer and method of manufacturing the same

Family Applications After (1)

Application Number Title Priority Date Filing Date
US15/212,367 Abandoned US20160329333A1 (en) 2013-06-07 2016-07-18 Semiconductor device having strain-relaxed buffer layer and method of manufacturing the same

Country Status (2)

Country Link
US (2) US9425198B2 (en)
KR (1) KR102069275B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160329333A1 (en) * 2013-06-07 2016-11-10 Samsung Electronics Co., Ltd. Semiconductor device having strain-relaxed buffer layer and method of manufacturing the same
US10644155B2 (en) 2017-05-30 2020-05-05 Korea Institute Of Science And Technology Method for manufacturing a semiconductor device with horizontally aligned semiconductor channels

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102056874B1 (en) * 2013-07-31 2019-12-17 삼성전자주식회사 Semiconductor device having fin field effect transistors and methods of forming the same
KR20170036966A (en) 2015-09-24 2017-04-04 삼성전자주식회사 Method of fabricating semiconductor device
US9818825B2 (en) * 2015-10-27 2017-11-14 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same
US10424585B2 (en) * 2016-01-21 2019-09-24 International Business Machines Corporation Decoupling capacitor on strain relaxation buffer layer
KR102401579B1 (en) * 2016-02-12 2022-05-24 삼성전자주식회사 Semiconductor devices and method of manufacturing the same
US10840350B2 (en) * 2016-10-31 2020-11-17 Taiwan Semiconductor Manufacturing Co., Ltd. Nanolaminate structure, semiconductor device and method of forming nanolaminate structure
US10854455B2 (en) * 2016-11-21 2020-12-01 Marvell Asia Pte, Ltd. Methods and apparatus for fabricating IC chips with tilted patterning
US10249757B2 (en) * 2016-12-21 2019-04-02 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same
WO2018125081A1 (en) * 2016-12-28 2018-07-05 Intel Corporation Transistors employing blanket-grown metamorphic buffer layer
JP6814965B2 (en) * 2017-03-06 2021-01-20 パナソニックＩｐマネジメント株式会社 Semiconductor epitaxial wafers, semiconductor devices, and methods for manufacturing semiconductor devices
US10553495B2 (en) * 2017-10-19 2020-02-04 International Business Machines Corporation Nanosheet transistors with different gate dielectrics and workfunction metals
US11670637B2 (en) * 2019-02-19 2023-06-06 Intel Corporation Logic circuit with indium nitride quantum well

Citations (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5442205A (en) 1991-04-24 1995-08-15 At&T Corp. Semiconductor heterostructure devices with strained semiconductor layers
US6339232B1 (en) 1999-09-20 2002-01-15 Kabushika Kaisha Toshiba Semiconductor device
US6682965B1 (en) * 1997-03-27 2004-01-27 Sony Corporation Method of forming n-and p- channel field effect transistors on the same silicon layer having a strain effect
US20040135138A1 (en) * 2003-01-15 2004-07-15 Sharp Laboratories Of America, Inc. System and method for isolating silicon germanium dislocation regions in strained-silicon CMOS applications
JP2004538639A (en) 2001-08-09 2004-12-24 アンバーウェーブ システムズ コーポレイション Double layer COMS device and method of manufacturing the same
US20050133819A1 (en) * 2003-11-07 2005-06-23 Hirohisa Kawasaki Semiconductor device using strained silicon layer and method of manufacturing the same
US20050136584A1 (en) * 2003-12-23 2005-06-23 Boyan Boyanov Strained transistor integration for CMOS
US20060068557A1 (en) * 2003-08-05 2006-03-30 Fujitsu Limited Semiconductor device and method for fabricating the same
US20060081836A1 (en) * 2004-10-14 2006-04-20 Yoshinobu Kimura Semiconductor device and method of manufacturing the same
US20060094193A1 (en) 2004-10-29 2006-05-04 Manfred Horstmann Semiconductor device including semiconductor regions having differently strained channel regions and a method of manufacturing the same
US7071014B2 (en) 2002-10-30 2006-07-04 Amberwave Systems Corporation Methods for preserving strained semiconductor substrate layers during CMOS processing
US20060289916A1 (en) * 2004-10-07 2006-12-28 Chanho Park Power Trench MOSFETs Having SiGe/Si Channel Structure
US20070164364A1 (en) * 2006-01-06 2007-07-19 Hirohisa Kawasaki Semiconductor device using sige for substrate and method for fabricating the same
US7303949B2 (en) 2003-10-20 2007-12-04 International Business Machines Corporation High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture
US20070298561A1 (en) * 2006-06-21 2007-12-27 Texas Instruments Deutschland Gmbh INTEGRATED SiGe NMOS AND PMOS TRANSISTORS
US20080079084A1 (en) * 2006-09-28 2008-04-03 Micron Technology, Inc. Enhanced mobility MOSFET devices
US20090095981A1 (en) * 2007-10-16 2009-04-16 Samsung Electronics Co., Ltd. Complementary metal oxide semiconductor device and method of manufacturing the same
US7525161B2 (en) 2007-01-31 2009-04-28 International Business Machines Corporation Strained MOS devices using source/drain epitaxy
US7586153B2 (en) 2005-08-31 2009-09-08 Advanced Micro Devices, Inc. Technique for forming recessed strained drain/source regions in NMOS and PMOS transistors
US20100078682A1 (en) * 2008-09-29 2010-04-01 Tat Ngai Power mosfet having a strained channel in a semiconductor heterostructure on metal substrate
US7728387B1 (en) * 2006-06-13 2010-06-01 The Board Of Trustees Of The Leland Stanford Junior University Semiconductor device with high on current and low leakage
US7741167B2 (en) 2006-10-31 2010-06-22 Advanced Micro Devices, Inc. Semiconductor device comprising NMOS and PMOS transistors with embedded Si/Ge material for creating tensile and compressive strain
US7777250B2 (en) 2006-03-24 2010-08-17 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures and related methods for device fabrication
US20100219475A1 (en) 2009-02-27 2010-09-02 Stephan Kronholz Integration of semiconductor alloys in pmos and nmos transistors by using a common cavity etch process
EP1644980B1 (en) 2003-07-07 2011-03-30 Micron Technology, Inc. Pixel with strained silicon layer for improving carrier mobility and blue response in imagers
US20130045579A1 (en) * 2011-08-17 2013-02-21 Chin-Cheng Chien Method of forming semiconductor device
US20130299895A1 (en) * 2012-05-09 2013-11-14 Taiwan Semiconductor Manufacturing Co., Ltd. Iii-v compound semiconductor device having dopant layer and method of making the same
US20140008730A1 (en) * 2012-07-03 2014-01-09 Imec Complementary Metal-Oxide-Semiconductor Device Comprising Silicon and Germanium and Method for Manufacturing Thereof

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6963078B2 (en) * 2003-03-15 2005-11-08 International Business Machines Corporation Dual strain-state SiGe layers for microelectronics
US20090130826A1 (en) * 2004-10-11 2009-05-21 Samsung Electronics Co., Ltd. Method of Forming a Semiconductor Device Having a Strained Silicon Layer on a Silicon-Germanium Layer
US7470972B2 (en) * 2005-03-11 2008-12-30 Intel Corporation Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stress
US9214555B2 (en) * 2013-03-12 2015-12-15 Taiwan Semiconductor Manufacturing Co., Ltd. Barrier layer for FinFET channels
KR102069275B1 (en) * 2013-06-07 2020-01-22 삼성전자주식회사 Semiconductor device having strained channel layer and method of manufacturing the same
US9196710B2 (en) * 2014-02-11 2015-11-24 GlobalFoundries, Inc. Integrated circuits with relaxed silicon / germanium fins

Patent Citations (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5442205A (en) 1991-04-24 1995-08-15 At&T Corp. Semiconductor heterostructure devices with strained semiconductor layers
US6682965B1 (en) * 1997-03-27 2004-01-27 Sony Corporation Method of forming n-and p- channel field effect transistors on the same silicon layer having a strain effect
US6339232B1 (en) 1999-09-20 2002-01-15 Kabushika Kaisha Toshiba Semiconductor device
JP2004538639A (en) 2001-08-09 2004-12-24 アンバーウェーブ システムズ コーポレイション Double layer COMS device and method of manufacturing the same
US7071014B2 (en) 2002-10-30 2006-07-04 Amberwave Systems Corporation Methods for preserving strained semiconductor substrate layers during CMOS processing
US20040135138A1 (en) * 2003-01-15 2004-07-15 Sharp Laboratories Of America, Inc. System and method for isolating silicon germanium dislocation regions in strained-silicon CMOS applications
EP1644980B1 (en) 2003-07-07 2011-03-30 Micron Technology, Inc. Pixel with strained silicon layer for improving carrier mobility and blue response in imagers
US20060068557A1 (en) * 2003-08-05 2006-03-30 Fujitsu Limited Semiconductor device and method for fabricating the same
US7303949B2 (en) 2003-10-20 2007-12-04 International Business Machines Corporation High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture
US20050133819A1 (en) * 2003-11-07 2005-06-23 Hirohisa Kawasaki Semiconductor device using strained silicon layer and method of manufacturing the same
US20050136584A1 (en) * 2003-12-23 2005-06-23 Boyan Boyanov Strained transistor integration for CMOS
US7662689B2 (en) 2003-12-23 2010-02-16 Intel Corporation Strained transistor integration for CMOS
US20060289916A1 (en) * 2004-10-07 2006-12-28 Chanho Park Power Trench MOSFETs Having SiGe/Si Channel Structure
US20060081836A1 (en) * 2004-10-14 2006-04-20 Yoshinobu Kimura Semiconductor device and method of manufacturing the same
US20060094193A1 (en) 2004-10-29 2006-05-04 Manfred Horstmann Semiconductor device including semiconductor regions having differently strained channel regions and a method of manufacturing the same
US7586153B2 (en) 2005-08-31 2009-09-08 Advanced Micro Devices, Inc. Technique for forming recessed strained drain/source regions in NMOS and PMOS transistors
US20070164364A1 (en) * 2006-01-06 2007-07-19 Hirohisa Kawasaki Semiconductor device using sige for substrate and method for fabricating the same
US7777250B2 (en) 2006-03-24 2010-08-17 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures and related methods for device fabrication
US7728387B1 (en) * 2006-06-13 2010-06-01 The Board Of Trustees Of The Leland Stanford Junior University Semiconductor device with high on current and low leakage
US20070298561A1 (en) * 2006-06-21 2007-12-27 Texas Instruments Deutschland Gmbh INTEGRATED SiGe NMOS AND PMOS TRANSISTORS
US20080079084A1 (en) * 2006-09-28 2008-04-03 Micron Technology, Inc. Enhanced mobility MOSFET devices
US7741167B2 (en) 2006-10-31 2010-06-22 Advanced Micro Devices, Inc. Semiconductor device comprising NMOS and PMOS transistors with embedded Si/Ge material for creating tensile and compressive strain
US7525161B2 (en) 2007-01-31 2009-04-28 International Business Machines Corporation Strained MOS devices using source/drain epitaxy
US20090095981A1 (en) * 2007-10-16 2009-04-16 Samsung Electronics Co., Ltd. Complementary metal oxide semiconductor device and method of manufacturing the same
US20100078682A1 (en) * 2008-09-29 2010-04-01 Tat Ngai Power mosfet having a strained channel in a semiconductor heterostructure on metal substrate
US20100219475A1 (en) 2009-02-27 2010-09-02 Stephan Kronholz Integration of semiconductor alloys in pmos and nmos transistors by using a common cavity etch process
US20130045579A1 (en) * 2011-08-17 2013-02-21 Chin-Cheng Chien Method of forming semiconductor device
US20130299895A1 (en) * 2012-05-09 2013-11-14 Taiwan Semiconductor Manufacturing Co., Ltd. Iii-v compound semiconductor device having dopant layer and method of making the same
US20140008730A1 (en) * 2012-07-03 2014-01-09 Imec Complementary Metal-Oxide-Semiconductor Device Comprising Silicon and Germanium and Method for Manufacturing Thereof

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
M. L. Lee and E. A. Fitsgerald, "Strained Si, SiGe, and Ge channels for high-mobility metal-oxide-semiconductor field-effect transistors,"J. Appl. Phys. 97, 101101 (2005).
M. V. Fischetti,"On the enhanced electron mobility in strained-silicon inversion layers," J. Appl. Phys. 92, 7320 (2002).

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160329333A1 (en) * 2013-06-07 2016-11-10 Samsung Electronics Co., Ltd. Semiconductor device having strain-relaxed buffer layer and method of manufacturing the same
US10644155B2 (en) 2017-05-30 2020-05-05 Korea Institute Of Science And Technology Method for manufacturing a semiconductor device with horizontally aligned semiconductor channels

Also Published As

Publication number Publication date
US20140361378A1 (en) 2014-12-11
KR20140143869A (en) 2014-12-18
KR102069275B1 (en) 2020-01-22
US20160329333A1 (en) 2016-11-10

Similar Documents

Publication Publication Date Title
US9425198B2 (en) Semiconductor device having strain-relaxed buffer layer and method of manufacturing the same
US10720496B2 (en) FinFET structures and methods of forming the same
US10861972B2 (en) Channel strain inducing architecture and doping technique at replacement poly gate (RPG) stage
US10164022B2 (en) FinFETs with strained well regions
US9508849B2 (en) Device having source/drain regions regrown from un-relaxed silicon layer
US7700452B2 (en) Strained channel transistor
US20140209976A1 (en) Transistors and methods of manufacturing the same
US9711417B2 (en) Fin field effect transistor including a strained epitaxial semiconductor shell
US9472470B2 (en) Methods of forming FinFET with wide unmerged source drain EPI
US9385234B2 (en) FinFETs with strained well regions
CN106328538A (en) A self-aligned SiGe FinFET
US11688741B2 (en) Gate-all-around devices with isolated and non-isolated epitaxy regions for strain engineering
CN105448834A (en) Semiconductor structures with different strain states of transistor channels, and method for fabricating the same
CN105448665A (en) Method for fabricating semiconductor structures, and related semiconductor structures
KR100618827B1 (en) Semiconductor device comprising FinFET and fabricating method thereof
US20100323486A1 (en) Triple-gate transistor with reverse shallow trench isolation
US20180197780A1 (en) Field effect transistor including strained germanium fins
US9911601B2 (en) Epitaxial silicon germanium fin formation using sacrificial silicon fin templates
US20210257450A1 (en) Creation of stress in the channel of a nanosheet transistor
US20160155818A1 (en) Method for fabricating semiconductor device
US9761693B2 (en) Method for fabricating semiconductor device
CN110970300B (en) Stacked gate-all-around fin field effect transistor and forming method thereof
US20230317791A1 (en) Semiconductor device and manufacturing method thereof
US10319643B1 (en) Vertical FET with strained channel

Legal Events

Date Code Title Description
AS Assignment

Owner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LEE, DONG-KYU;LEE, JAE-HWAN;KWON, TAE-YONG;AND OTHERS;SIGNING DATES FROM 20140520 TO 20140522;REEL/FRAME:032981/0791

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 8