CN101924107A - Stress enhanced CMOS (Complementary Metal-Oxide-Semiconductor) transistor structure - Google Patents
Stress enhanced CMOS (Complementary Metal-Oxide-Semiconductor) transistor structure Download PDFInfo
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- CN101924107A CN101924107A CN 201010227112 CN201010227112A CN101924107A CN 101924107 A CN101924107 A CN 101924107A CN 201010227112 CN201010227112 CN 201010227112 CN 201010227112 A CN201010227112 A CN 201010227112A CN 101924107 A CN101924107 A CN 101924107A
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- 230000002708 enhancing effect Effects 0.000 claims description 4
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- 238000004519 manufacturing process Methods 0.000 abstract description 9
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- 229910052782 aluminium Inorganic materials 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7849—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being provided under the channel
Abstract
The invention relates to a stress enhanced CMOS (Complementary Metal-Oxide-Semiconductor) transistor structure which has the characteristics of stress enhancement. The CMOS transistor structure is characterized by introducing a stress concentration factor 40/42 below a channel, so that the stress of the channel is enhanced. The structure is used together with relevant stress introducing methods, such as double stress layer technology, embedded drain source SiGe/SiC technology and the like, the introduced stress of the channel region can be greatly increased, and thus, the drive current of the CMOS transistor is increased. The CMOS transistor structure has simple manufacturing process, not only is applicable to conventional small size strained silicon devices smaller than 90 nm, but also can promote the strained silicon technology to large size devices more than 0.18 micrometer.
Description
Affiliated technical field
The present invention relates to transistor arrangement, relate in particular to the transistor arrangement that strengthens about stress.
Background technology
The semiconductor integrated circuit manufacturing technology adopts strained silicon technology day by day near the physics limit of material and technology, under the prerequisite of reduction of device characteristic size not device performance is promoted a generation, and the cost of paying only is that existing technology is carried out a spot of change.
Known, in the raceway groove of N type metal oxide semiconductor field-effect transistor (NMOSFET), introduce the performance that tensile stress can promote NMOSFET, in the raceway groove of P-type mos field-effect transistor (PMOSFET), introduce the performance that compression can promote PMOSFET.
Present strained silicon technology mainly is divided into overall strain and local train.Overall situation strain gauge technique is meant that stress is produced by substrate, and can cover all and be produced on transistor area on the substrate, and this stress is twin shaft normally.The material that can produce overall strain comprise germanium silicon on the insulating barrier (SiGe on Insulator, SGOI), germanium silicon virtual substrate (SiGe virtual substrate) etc.The local train technology usually only in the part of semiconductor device to semiconductor channel zone stress application.The local train technology mainly contains source-drain area and embeds germanium silicon (SiGe) or carborundum (SiC), dual stressed layers (Dual Stress Layers, DSL) and shallow-trench isolation (Shallow Trench Isolation, STI) etc.Overall situation strain is made complicated, and cost is higher, and local train is with the traditional cmos manufacturing process has favorable compatibility and manufacture method is simple, thereby only need increase a small amount of cost when improving performance of semiconductor device, so is subjected to industry and uses widely.
But still there is deficiency in used local train technology at present.At first, said method all is indirectly stress transfer to be arrived channel region, must relaxation fall part stress on the Stress Transfer path.For example, germanium silicon or carbon silicon technology are leaked in embedded source, though its stress riser nestles up raceway groove, but because the body silicon below the raceway groove and the effect of the gate insulation layer above the raceway groove, the closer to the raceway groove center, stress is more little, generally is the U font and distributes, and stress riser is from raceway groove STI technology and DSL technology far away still more.Secondly, have high-temperature technology in the fabrication of semiconductor device, high temperature can cause stress part relaxation.For example after deposit comprised the SiN block layer of intrinsic stress, subsequent technique generally also comprised at least 450 ℃ high-temperature technology of multistep, therefore must make channel region stress part relaxation.In sum, said method all is subjected to the restriction of device size and manufacturing process, and device size is big more, and channel region stress is just more little.This also is that conventional strained silicon technology only is suitable for the following reason of 90 nanometer technologies.For large-size (0.18 micron more than the manufacturing process) device, the performance boost that said method brings almost disappears.
Summary of the invention
The objective of the invention is in order to overcome the decay of stress in transmitting the channel region process, the spy provides a kind of CMOS transistor arrangement that stress strengthens characteristic that has.Silicon/the germanium silicon technology is example (Fig. 1) to leak carbon with the embedded source in the stress introducing method, and this method is introduced tensile stress at the NMOS raceway groove, and the PMOS raceway groove is introduced compression, thereby has strengthened drive current.But in the Stress Transfer process, because the restriction of device size and technological temperature, the stress that causes really being passed to raceway groove is subjected to great decay (as previously mentioned, stress is the U font and distributes), adopt the present invention, can reduce the degree of decay, promote thereby obtain bigger device performance than conventional method.
Stress of the present invention strengthens cmos device structure following (Fig. 2): this cmos device includes the Semiconductor substrate (10) of making the first transistor NMOSFET and transistor seconds MOSFET, well region (20/24), source-drain area (22/26), grid (30/32), shallow trench isolation region (12) and passivation layer (50/52), be with the prior art difference: before the growth gate insulation layer, below the raceway groove between the source-drain area, the place that has with a certain distance from gate insulation layer is etched with hole, hole is generally 20nm-25nm from the distance of gate insulation layer, certain distance is arranged between the hole, its distance is 25nm-35nm, be filled with the material of low Young's modulus in the hole, the pore quantity of etching is no less than one.
As seen from Figure 2, the first transistor NMOSFET strengthens transistor with common stress and compares, and its P trap 20 increases near channel region places carves hole 40, fills the material that hangs down Young's modulus in the hole in, as silicon dioxide, and perhaps metallic aluminium etc.
Transistor seconds PMOSFET strengthens transistor with common stress and compares, and its N trap 24 increases near channel region places carves hole 42, fills the material that hangs down Young's modulus in the hole in, as silicon dioxide, and perhaps metallic aluminium etc.
The principle that its stress strengthens is: the stress concentration effect in apply materials mechanics and the structural mechanics.It is because the unexpected variation in cross section that stress is concentrated, external force inhomogeneous, exist crackle and member whether to be in that the inferior factor of fatigue load effect causes in discontinuity of material own or the member, local organization changes, unbalance stress, and producing very big stress on the small size very much, and this stress is far longer than nominal stress or mean stress, thus make stress too concentrated.In the present invention, artificial introducing material is discontinuous, at once hole (being not limited to the square opening that Fig. 2 provides), and fill the material 40/42 differ from grid 30/32 (its Young's modulus of this material should less than silicon), can produce stress concentration effect, near the scalable stress concentration point of this stress concentration effect stress can (this stress be introduced by various stress introducing methods to tens of times, carbon silicon/germanium silicon etc. is leaked in embedded as previously mentioned source), for NMOSFET, be tensile stress, for PMOSFET, be compression, because this stress concentration point is near channel region, so can promote the tensile stress of NMOSFET channel region, the compression of PMOSFET channel region respectively.
In engineering, in general stress concentration effect is harmful to, but in the present invention, the stress in the device is actually little stress, and material is in elastically-deformable category, so stress concentration effect can't cause component failure.
As seen by above-mentioned, the cmos device with stress enhancing provided by the invention can greatly reduce the stress decay degree that stress riser is passed to channel region, has promptly strengthened the stress of channel region, thereby obtains bigger drive current.The present invention especially can be used for large-size device, because device size is big, means that stress riser is far away from device channel region, so the stress decay of channel region is big, uses anti-stress decay characteristic of the present invention, can improve the negative effect that device size brings greatly.
Description of drawings
Fig. 1 has been to use the generalized section of the cmos device basic structure of existing main local stress technology.Wherein 1---embedded carborundum is leaked in the source; 2---embedded germanium silicon is leaked in the source; 3---shallow trench isolation region; 4---the tensile stress layer; 5---compressive stress layer.
Fig. 2 is one of the present invention and has the longitudinal sectional drawing that stress strengthens the cmos device structure of characteristic.
Following table is the implication explanation of one embodiment of the present of invention contrast accompanying drawing 2 sequence number of annotating.
| Sequence number | The implication explanation | Sequence number | The |
| 10 | |
32 | The |
| 12 | Shallow |
40 | NMOSFET |
| 20 | NMOSFET well region (P trap) | 42 | PMOSFET grid porose area |
| 22 | The NMOSFET source- |
50 | Tensile |
| 24 | PMOSFET well region (N trap) | 52 | |
| 26 | The PMOSFET source- |
60 | The |
| 30 | The |
62 | The PMOSFET device |
Fig. 3 is one of the present invention and has the cmos device output characteristic simulation result that stress strengthens characteristic.Wherein:
A: expression W/L=1um/0.5um, the output characteristic of ordinary construction NMOSFET.
A ': expression W/L=1um/0.5um, have the output characteristic that stress of the present invention strengthens structure NMOSFET, owing to promoted tensile stress, make drive current get a promotion.
B: expression W/L=1um/0.8um, the output characteristic of ordinary construction NMOSFET.
B ': expression W/L=1um/0.8m, have the output characteristic that stress of the present invention strengthens structure NMOSFET, owing to promoted tensile stress, make drive current get a promotion.
C: expression W/L=1um/0.5um, the output characteristic of ordinary construction PMOSFET.
C ': expression W/L=1um/0.5um, have the output characteristic that stress of the present invention strengthens structure PMOSFET, owing to promoted compression, make drive current get a promotion.
D: expression W/L=1um/0.8um, the output characteristic of ordinary construction PMOSFET.
D ': expression W/L=1um/0.8um, have the output characteristic that stress of the present invention strengthens structure PMOSFET, owing to promoted a compression, make drive current get a promotion.
As seen, the lifting effect is obvious.
Wherein W/L represents the ratio of device channel width (Width) and channel length (Length).
Embodiment
Statement: the present invention's herein execution mode only is schematically, and does not mean that the present invention only is confined to this embodiment, and perhaps this embodiment is an optimum implementation.Hole that for example the present invention carves is not limited only to square opening shown in Figure 2, as circle, and ellipse, square, rectangle, rhombus, triangle, trapezoidal; The quantity in hole that the present invention carves also is not limited only to two that Fig. 2 provides.
Claims (4)
1. CMOS transistor that strengthens channel stress.It comprises the Semiconductor substrate (10), well region (20/24), the source that generate NMOSFET device and PMOSFET device and leaks (22/26), grid (30/32), shallow trench isolation region (12), passivation layer (50/52), it is characterized in that growing before the gate insulation layer, below the raceway groove between the source-drain area, be etched with hole from gate insulation layer a distance, certain spacing is arranged between the hole, in hole, be filled with the material of low Young's modulus.
2. enhancing channel stress CMOS transistor according to claim 1, the hole that it is characterized in that etching is from gate insulation layer 20nm-25nm, and the spacing between the hole is 25nm-35nm.
3. enhancing channel stress CMOS transistor according to claim 1 is characterized in that the pore quantity of raceway groove place etching between source-drain area is no less than 1.
4. according to the CMOS transistor of right 1 described enhancing channel region stress, it is square to it is characterized in that the void shape that etches can be, rectangle, circle, ellipse, triangle, rhombus.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010227112 CN101924107B (en) | 2010-07-15 | 2010-07-15 | Stress enhanced CMOS (Complementary Metal-Oxide-Semiconductor) transistor structure |
| US13/512,415 US20130137235A1 (en) | 2010-07-15 | 2011-04-22 | Mos transistor using stress concentration effect for enhancing stress in channel area |
| PCT/CN2011/073177 WO2012006890A1 (en) | 2010-07-15 | 2011-04-22 | Mos transistor using stress concentration effect for enhancing stress in channel area |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010227112 CN101924107B (en) | 2010-07-15 | 2010-07-15 | Stress enhanced CMOS (Complementary Metal-Oxide-Semiconductor) transistor structure |
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| CN101924107A true CN101924107A (en) | 2010-12-22 |
| CN101924107B CN101924107B (en) | 2012-09-26 |
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| CN 201010227112 Expired - Fee Related CN101924107B (en) | 2010-07-15 | 2010-07-15 | Stress enhanced CMOS (Complementary Metal-Oxide-Semiconductor) transistor structure |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012006890A1 (en) * | 2010-07-15 | 2012-01-19 | 电子科技大学 | Mos transistor using stress concentration effect for enhancing stress in channel area |
| CN102683215A (en) * | 2012-05-04 | 2012-09-19 | 上海华力微电子有限公司 | Method for preparing strained silicon nanowire N-channel metal oxide semiconductor field effect transistor (NMOSFET) |
| CN102983174A (en) * | 2012-12-18 | 2013-03-20 | 电子科技大学 | Strained PMOSFET with trough-type structures and fabrication method of strain PMOSFET |
| CN103474351A (en) * | 2012-06-06 | 2013-12-25 | 中芯国际集成电路制造(上海)有限公司 | NMOS transistor and its formation method and CMOS transistor containing NMOS transistor |
| CN103996709A (en) * | 2013-02-20 | 2014-08-20 | 台湾积体电路制造股份有限公司 | Method for inducing strain in finfet channels |
| CN105448723A (en) * | 2014-08-22 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and forming method thereof |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9306066B2 (en) * | 2014-02-28 | 2016-04-05 | Qualcomm Incorporated | Method and apparatus of stressed FIN NMOS FinFET |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6563152B2 (en) * | 2000-12-29 | 2003-05-13 | Intel Corporation | Technique to obtain high mobility channels in MOS transistors by forming a strain layer on an underside of a channel |
| CN1941387A (en) * | 2005-09-29 | 2007-04-04 | 国际商业机器公司 | Semiconductor constructions and manufacturing method thereof |
| CN101064286A (en) * | 2006-04-28 | 2007-10-31 | 国际商业机器公司 | High performance stress-enhance mosfet and method of manufacture |
-
2010
- 2010-07-15 CN CN 201010227112 patent/CN101924107B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6563152B2 (en) * | 2000-12-29 | 2003-05-13 | Intel Corporation | Technique to obtain high mobility channels in MOS transistors by forming a strain layer on an underside of a channel |
| CN1941387A (en) * | 2005-09-29 | 2007-04-04 | 国际商业机器公司 | Semiconductor constructions and manufacturing method thereof |
| CN101064286A (en) * | 2006-04-28 | 2007-10-31 | 国际商业机器公司 | High performance stress-enhance mosfet and method of manufacture |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012006890A1 (en) * | 2010-07-15 | 2012-01-19 | 电子科技大学 | Mos transistor using stress concentration effect for enhancing stress in channel area |
| CN102683215A (en) * | 2012-05-04 | 2012-09-19 | 上海华力微电子有限公司 | Method for preparing strained silicon nanowire N-channel metal oxide semiconductor field effect transistor (NMOSFET) |
| CN103474351A (en) * | 2012-06-06 | 2013-12-25 | 中芯国际集成电路制造(上海)有限公司 | NMOS transistor and its formation method and CMOS transistor containing NMOS transistor |
| CN103474351B (en) * | 2012-06-06 | 2017-02-22 | 中芯国际集成电路制造(上海)有限公司 | NMOS transistor and its formation method and CMOS transistor containing NMOS transistor |
| CN102983174A (en) * | 2012-12-18 | 2013-03-20 | 电子科技大学 | Strained PMOSFET with trough-type structures and fabrication method of strain PMOSFET |
| CN103996709A (en) * | 2013-02-20 | 2014-08-20 | 台湾积体电路制造股份有限公司 | Method for inducing strain in finfet channels |
| CN105448723A (en) * | 2014-08-22 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and forming method thereof |
| CN105448723B (en) * | 2014-08-22 | 2019-07-30 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
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