CN102064177B - CMOS (Complementary Metal Oxide Semiconductor) transistor structure with stress amplification - Google Patents
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- 230000003321 amplification Effects 0.000 title claims abstract description 10
- 238000003199 nucleic acid amplification method Methods 0.000 title claims abstract description 10
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- 150000004706 metal oxides Chemical class 0.000 title abstract description 3
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- 238000002955 isolation Methods 0.000 claims abstract description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 19
- 235000012239 silicon dioxide Nutrition 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 10
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- 238000005530 etching Methods 0.000 claims description 4
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- 238000002161 passivation Methods 0.000 claims description 2
- 229910004298 SiO 2 Inorganic materials 0.000 claims 1
- 239000011800 void material Substances 0.000 claims 1
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- 229910052681 coesite Inorganic materials 0.000 description 6
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- 229910010271 silicon carbide Inorganic materials 0.000 description 3
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- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
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- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H01L21/8232—Field-effect technology
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- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
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- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
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Abstract
The invention relates to a CMOS (Complementary Metal Oxide Semiconductor) transistor structure with stress amplification, in particular to a CMOS transistor structure with a stress amplification characteristic, which is characterized in that a stress concentration factor (40/42) is introduced in a grid (30/32) so as to amplify the stress of a trench. The structure is matched with relevant stress introduction methods for use, such as a dual-stress layer technology (60/62), a trench isolation technology (12), and the like, the stress introduced into the trench can be greatly improved, thus the drive current of the CMOS transistor is increased. The CMOS transistor structure with stress amplification has a simple manufacture process, is not only suitable for small-size elements of below 90-nano processes, but also suitable for larger elements of above 0.13-micrometer processes.
Description
Affiliated technical field
The present invention relates to transistor arrangement, relate in particular to the transistor arrangement that amplifies about stress.
Background technology
The semiconductor integrated circuit manufacturing technology has got into nanometer era, can improve the carrier mobility and the current driving ability of semiconductor device through adopting strained silicon technology, only needs simultaneously existing technology is carried out a spot of change.
Known; In the raceway groove of N type metal oxide semiconductor field-effect transistor (NMOSFET), introduce the performance that tensile stress can promote NMOSFET, in the raceway groove of P-type mos field-effect transistor (PMOSFET), introduce the performance that compression can promote PMOSFET.
Present strained silicon technology mainly is divided into overall strain and local train.Overall situation strain gauge technique is meant that stress is produced by substrate, and can cover all and be produced on the transistor area on the substrate, and this stress is twin shaft normally.The material that can produce overall strain comprise germanium silicon on the insulating barrier (SiGe on Insulator, SGOI), germanium silicon virtual substrate (SiGe virtual substrate) etc.Local train technology usually only in the part of semiconductor device to semiconductor channel zone stress application.The local train technology mainly contains source-drain area and embeds germanium silicon (SiGe) or carborundum (SiC), dual stressed layers (Dual Stress Layers, DSL), and shallow-trench isolation (Shallow Trench Isolation, STI).Overall situation strain gauge technique is made complicated, and cost is higher; Local train is technological and the CMOS technology has good processing compatibility and manufacturing approach is simple, thereby when improving performance of semiconductor device, only need increase a small amount of cost, therefore receives industry and uses widely.
But still there is deficiency in used local train technology at present.(1) stress riser of said method all has certain distance from raceway groove, and far away more apart from raceway groove, the attenuation degree of stress is high more.With the STI technology is example, and the stress that it is introduced need pass through source-drain area and could arrive trench edges; Arrive the raceway groove center from trench edges, also will receive the grid of raceway groove top and the body silicon influence of raceway groove below, so the stress distribution in the raceway groove is " U " type, or rather, channel stress and be inverse relation to the distance of stress riser.(2) have high-temperature technology in the fabrication of semiconductor device, high temperature can cause stress part relaxation.Therefore with the dual stressed layers technology is example, and its subsequent technique generally also comprises at least 450 ℃ high-temperature technology of multistep, must make channel region stress part relaxation.In sum, said method all receives the restriction of device size and manufacturing process, and device size is big more, and channel region stress is just more little.This also is that conventional strained silicon technology only is suitable for the reason below 90 nanometer technologies.For large-size (0.13 micron more than the manufacturing process) device, the performance boost that said method brings almost disappears.
Summary of the invention
The objective of the invention is in order to overcome the decay of stress in transmitting the channel region process, the spy provides a kind of MOS device with stress structure for amplifying.With the dual stressed layers method in the stress introducing method is example (Fig. 1), and this method is introduced tensile stress at the NMOS raceway groove, and the PMOS raceway groove is introduced compression, thereby has strengthened drive current.But in the Stress Transfer process, because the restriction of device size and technological temperature, the stress that causes really being passed to raceway groove receives great decay (as previously mentioned; Being " U " type distributes); Adopt the present invention, can reduce the degree of decay, thereby obtain bigger channel stress than conventional method.
Stress of the present invention amplifies cmos device structure (Fig. 2) as follows: this cmos device includes the Semiconductor substrate (10) of making the first transistor NMOSFET and transistor seconds PMOSFET; Well region (20/24); Source-drain area (22/26); Grid (30/32), shallow trench isolation region (12) and passivation layer (50/52).Be with the prior art difference: will make the grid structure and divide for 2 steps accomplished; The certain thickness grid of first step elder generation's deposit are etched with hole then in the grid of first step deposit, hole is generally 5nm-10nm from the distance of gate insulation layer; Certain distance is arranged between the hole; Its distance be 2nm-40nm, is filled with the material that hangs down Young's modulus in the hole, the pore quantity of etching at least one.Second step was continued the deposit grid again, made the thickness of overall grid reach technic index
Visible by Fig. 2, the first transistor NMOSFET strengthens transistor with common stress, and its grid 30 increase near the channel region place carves hole 40, fills the material that hangs down Young's modulus in the hole in, like silicon dioxide, and perhaps metallic aluminium etc.
Transistor seconds PMOSFET strengthens transistor with common stress, and its grid 32 increase near the channel region place carves hole 42, fills the material that hangs down Young's modulus in the hole in, like silicon dioxide, and perhaps metallic aluminium etc.
The principle that its stress amplifies is: the stress concentration effect in the mechanics of materials and the structural mechanics.It is because the unexpected variation in cross section that stress is concentrated; External force inhomogeneous; Exist crackle and member whether to be in that the inferior factor of fatigue load effect causes in discontinuity of material own or the member, local organization changes, unbalance stress; And producing very big stress on the small size very much, and this stress is far longer than nominal stress or mean stress makes stress too concentrated.In the present invention, it is discontinuous artificially to introduce material, promptly carves square opening (40/42) at grid (30/32), and filling differs from square hole (40/42) material in the grid (30/32); Like silicon dioxide/metal A l etc., can produce stress concentration effect, near the stress the scalable stress concentration point of this stress concentration effect can (this stress be introduced by various stress introducing methods to tens of times; Dual stressed layers is technological as previously mentioned, shallow-trench isolation technology etc.), for NMOSFET; Be tensile stress,, be compression for PMOSFET; Because this stress concentration point is near channel region, so can promote the tensile stress of NMOSFET channel region, the compression of PMOSFET channel region respectively.
In engineering, in general stress concentration effect is harmful to, but in the present invention, the stress in the device is actually little stress, and material is in elastically-deformable category, so stress concentration effect can't cause component failure.
By above-mentioned visible, the cmos device structure with stress amplification provided by the invention can greatly reduce the stress decay degree that stress riser is passed to channel region, has promptly amplified the stress of channel region, thereby obtains bigger drive current.And the present invention especially can be used for large-size device.Because device size is big, it is far away to mean that stress riser leaves device channel region, uses stress amplification characteristic of the present invention, can improve the stress excessive attenuation problem that device size brings greatly.
Description of drawings
Fig. 1 has been to use the generalized section of the cmos device basic structure of existing main local stress technology.Wherein 1---embedded carborundum is leaked in the source; 2---embedded germanium silicon is leaked in the source; 3---shallow trench isolation region; 4---the tensile stress layer; 5---compressive stress layer.
Fig. 2 is a longitudinal sectional drawing with cmos device structure embodiment of stress structure for amplifying of the present invention.
Following table is the implication explanation that the present invention contrasts accompanying drawing 2 sequence number of annotating.
| Sequence number | The implication explanation | Sequence number | The |
| 10 | |
32 | The |
| 12 | Shallow |
40 | NMOSFET |
| 20 | The |
42 | PMOSFET |
| 22 | The NMOSFET source- |
50 | Tensile |
| 24 | The |
52 | |
| 26 | The PMOSFET source- |
60 | The |
| 30 | The |
62 | The PMOSFET device |
Fig. 3 is the dimensional parameters explanation in the hole that grid dug (being 40/42 among Fig. 2) of device architecture of the present invention.
Fig. 4 is the simulation result (the raceway groove tensile stress with nmos device is distributed as example) that the MOS device channel stress distribution with stress amplification characteristic of employing grid perforate of the present invention is compared with common MOS device architecture channel stress distribution.
Wherein:
(1) Fig. 4 (a) is the stress distribution of the nmos device channel region of channel length L=65nm.
Wherein: A0 is that the channel stress of ordinary construction strain silicon MOS device distributes.
A1 is that the channel stress of opening the MOS device of the present invention in a hole in the grid distributes.
A2 is that the channel stress of opening the MOS device of the present invention in two holes in the grid distributes.
(2) Fig. 4 (b) is the stress distribution of the nmos device channel region of channel length L=90nm.
Wherein: B0 is that the channel stress of ordinary construction strain silicon MOS device distributes.
B1 is that the channel stress of opening the MOS device of the present invention in a hole in the grid distributes.
B2 is that the channel stress of opening the MOS device of the present invention in two holes in the grid distributes.
(3) Fig. 4 (c) is the stress distribution of the nmos device channel region of channel length L=180nm.
Wherein: C0 is that the channel stress of ordinary construction strain silicon MOS device distributes.
C1 is that the channel stress of opening the MOS device of the present invention in a hole in the grid distributes.
C2 is that the channel stress of opening the MOS device of the present invention in three holes in the grid distributes.
Embodiment
In following each embodiment, have the manufacture craft basically identical of stress structure for amplifying cmos device of the present invention, only the parameter in hole is different.The manufacture craft of following examples is explained as follows: the certain thickness grid of first step elder generation's deposit; Be etched with hole then therein; Hole is generally 5nm-10nm from the distance of gate insulation layer, and certain distance is arranged between the hole, and its distance is 2nm-40nm; Be filled with the material of low Young's modulus in the hole, the pore quantity of etching at least one.Second step was continued the deposit grid again, made the thickness of overall grid reach technic index.The size in hole will change according to the different of embodiment with quantity to some extent, concrete parameter explanation separately in an embodiment.
Visible through embodiment; Adopt the present invention in grid, to carve the hole and in carving the hole, be filled with and hang down the Young's modulus material; Compare with common strained silicon; Stress all has amplification, so the present invention can overcome the decay of stress in being passed to the channel region process, to improve the carrier mobility and the current driving ability of semiconductor device.
Statement: the present invention's here execution mode is merely schematically, and does not mean that the present invention only is confined to this embodiment, and perhaps this embodiment is an optimum implementation.Hole that for example the present invention carves is not limited only to square opening shown in Figure 2, also can be circle or ellipse or square or rectangular or rhombus or triangle or trapezoidal; The quantity in hole that the present invention carves also is not limited only to two that Fig. 3 provides.
Claims (5)
1. the CMOS transistor that amplifies of a stress; It comprises the Semiconductor substrate (10), well region (20/24), the source that generate NMOSFET device and PMOSFET device and leaks (22/26), grid (30/32), shallow trench isolation region (12), passivation layer (50/52); When it is characterized in that making grid; In grid, be etched with hole (40/42), in hole, be filled with the material of low Young's modulus, utilize the difference of the inside and outside Young's modulus of hole and the sudden change in cross section to produce the stress amplification; Amplify channel stress, improve device performance.
2. the CMOS transistor that stress according to claim 1 amplifies, the hole that it is characterized in that etching is from gate insulation layer 5nm-10nm.
3. according to the amplification CMOS transistor of claim 1 or 2 described stress, it is characterized in that the pore quantity of etching is at least 1 in grid, when pore quantity greater than 1 the time, the spacing between the hole is 20nm-35nm.
4. the CMOS transistor that stress according to claim 1 amplifies is characterized in that the material of the low Young's modulus of filling in the hole is silicon dioxide (SiO
2) or metallic aluminium (Al).
5. the CMOS transistor that amplifies according to right 1 described stress is characterized in that the void shape that etches can be square or rectangle or circular or oval or triangle or rhombus.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010539413A CN102064177B (en) | 2010-11-11 | 2010-11-11 | CMOS (Complementary Metal Oxide Semiconductor) transistor structure with stress amplification |
| US13/512,415 US20130137235A1 (en) | 2010-07-15 | 2011-04-22 | Mos transistor using stress concentration effect for enhancing stress in channel area |
| PCT/CN2011/073177 WO2012006890A1 (en) | 2010-07-15 | 2011-04-22 | Mos transistor using stress concentration effect for enhancing stress in channel area |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010539413A CN102064177B (en) | 2010-11-11 | 2010-11-11 | CMOS (Complementary Metal Oxide Semiconductor) transistor structure with stress amplification |
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| CN102064177A CN102064177A (en) | 2011-05-18 |
| CN102064177B true CN102064177B (en) | 2012-09-26 |
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| CN102290352B (en) * | 2011-09-09 | 2013-02-06 | 电子科技大学 | Introducing technology of local stress of MOS (Metal Oxide Semiconductor) transistor |
| CN117497605A (en) * | 2023-12-29 | 2024-02-02 | 深圳天狼芯半导体有限公司 | PMOS with low on-resistance at high temperature and preparation method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6563152B2 (en) * | 2000-12-29 | 2003-05-13 | Intel Corporation | Technique to obtain high mobility channels in MOS transistors by forming a strain layer on an underside of a channel |
| CN1941387A (en) * | 2005-09-29 | 2007-04-04 | 国际商业机器公司 | Semiconductor constructions and manufacturing method thereof |
| CN101064286A (en) * | 2006-04-28 | 2007-10-31 | 国际商业机器公司 | High performance stress-enhance mosfet and method of manufacture |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6563152B2 (en) * | 2000-12-29 | 2003-05-13 | Intel Corporation | Technique to obtain high mobility channels in MOS transistors by forming a strain layer on an underside of a channel |
| CN1941387A (en) * | 2005-09-29 | 2007-04-04 | 国际商业机器公司 | Semiconductor constructions and manufacturing method thereof |
| CN101064286A (en) * | 2006-04-28 | 2007-10-31 | 国际商业机器公司 | High performance stress-enhance mosfet and method of manufacture |
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