CN103928336B - PMOS transistor and manufacturing method thereof - Google Patents
PMOS transistor and manufacturing method thereof Download PDFInfo
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- CN103928336B CN103928336B CN201310015010.8A CN201310015010A CN103928336B CN 103928336 B CN103928336 B CN 103928336B CN 201310015010 A CN201310015010 A CN 201310015010A CN 103928336 B CN103928336 B CN 103928336B
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- 238000004519 manufacturing process Methods 0.000 title abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 79
- 230000001105 regulatory effect Effects 0.000 claims description 249
- 239000000463 material Substances 0.000 claims description 31
- 238000002360 preparation method Methods 0.000 claims description 28
- 229910020328 SiSn Inorganic materials 0.000 claims description 20
- 239000004065 semiconductor Substances 0.000 claims description 15
- 239000000126 substance Substances 0.000 claims description 14
- 229910006992 Si1-xCx Inorganic materials 0.000 claims description 6
- 230000000574 ganglionic effect Effects 0.000 claims description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract description 17
- 238000000034 method Methods 0.000 abstract description 8
- 230000003139 buffering effect Effects 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 15
- 229910052710 silicon Inorganic materials 0.000 description 15
- 239000010703 silicon Substances 0.000 description 15
- 230000000694 effects Effects 0.000 description 13
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 6
- 239000007789 gas Substances 0.000 description 5
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- 230000009977 dual effect Effects 0.000 description 2
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- 229910052738 indium Inorganic materials 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
Abstract
The invention provides a PMOS transistor and a manufacturing method of the PMOS transistor. When source electrode areas and drain electrode areas of the PMOS transistor are formed, a method that a first stress adjusting layer, a second stress adjusting layer and a stress maintaining layer sequentially grow in an epitaxial mode is adopted. The lattice constant of the first stress adjusting layer and the lattice constant of the second stress adjusting layer gradually increase. When the second stress adjusting layer is formed in an epitaxial mode, an element with the lattice constant larger than that of the Ge element for doping, so that the second stress adjusting layer forms most of the source electrode areas and the drain electrode areas, and larger pressure stress is provided for a channel so that the channel can have higher carrier mobility and work current of a device can be improved; the first stress adjusting layer between the second stress adjusting layer and a substrate serves as a stress buffering layer, and defects caused by too large lattice mismatch between the second stress adjusting layer and the substrate are reduced; a sandwich structure formed by the first stress adjusting layer and the second stress adjusting layer which are spaced is adopted, so that the defects caused by too large lattice mismatch between the second stress adjusting layer and the substrate are further reduced.
Description
Technical field
The invention belongs to technical field of semiconductor device, it is related to a kind of transistor and preparation method thereof, more particularly to one
Plant PMOS transistor and preparation method thereof.
Background technology
Within following a period of time, silicon-based complementary formula metal-oxide semiconductor (MOS) (CMOS) transistor is modem logic electricity
Elementary cell in road, wherein comprising PMOS and NMOS, and each PMOS or nmos pass transistor are all located on impure well, and all
By the raceway groove that p-type in the substrate of grid (Gate) both sides or n-type source area, drain region and source area are interval with drain electrode
(Channel) constitute.
In existing semiconductor technology, the method for forming transistor is generally：Silicon base is provided, trap is formed in silicon base
Area and isolation structure；Gate dielectric layer and grid are sequentially formed on silicon substrate surface；Formed around gate dielectric layer and grid
Side wall；Ion implanting is carried out to silicon base as mask with side wall, gate medium and grid and forms source electrode and drain electrode, source electrode and drain electrode
Between well region be channel region.
With the development of semiconductor technology, the characteristic size of device is less and less in integrated circuit.When complementary metal oxygen
The processing technology of compound quasiconductor is advanced to after micron order, because the raceway groove between source/drain regions shortens therewith, works as raceway groove
When the length in area is reduced to certain value, short-channel effect (Short Channel Effect) and hot carrier's effect can be produced
(Hot Carrier Effect) and and then element is caused to operate.In other words, because the presence of short-channel effect can affect
The performance of device, therefore also just hinder the further diminution of device feature size in integrated circuit.
In order to avoid the generation of short-channel effect and hot carrier's effect, the source of micron order and the CMOS of following processing technology
Lightly doped drain (Lightly Doped Drain, LDD) structure can be adopted in pole/drain electrode design, that is, below grid structure
The part formation depth of adjacent source/drain regions is shallower, and dopant profile and source/drain regions identical doped regions, to drop
The electric field of low channel region.
Aiming at for current research integrated circuit basic technology obtains higher unit integrated level, higher circuit speed
Degree, the power consumption of lower unit function and unit functional cost.During device size Scaling, higher integrated level
Mean bigger power consumption with operating frequency, it is to reduce being typically chosen for circuit power consumption to reduce supply voltage VDD, but the drop of VDD
The low driving force that can cause device and speed decline.Reducing threshold voltage, thinning grid medium thickness can improve the electric current of device
Driving force, but while the increase of sub-threshold current leakage and grid leakage current can be caused, so as to increase quiescent dissipation, here it is mesh
" power consumption-speed " predicament that front IC faces.
It is the key for solving above-mentioned predicament to improve device channel mobility.On the basis that channel mobility is significantly lifted
On, relatively low VDD and higher threshold value drain voltage on the one hand can be adopted, while and can ensure that device there are enough electric currents to drive
Kinetic force and speed.
, it is known that introduce tensile stress in the raceway groove of N-type mos field effect transistor (NMOSFET) can be with
The channel mobility of NMOSFET is lifted, is drawn in the raceway groove of P-type mos field-effect transistor (PMOSFET)
Entering compressive stress can lift the channel mobility of PMOSFET.
Current strained silicon technology is broadly divided into global strain and local train.Global strain gauge technique refers to stress by substrate
Produce, and all transistor areas being produced on substrate can be covered, this stress is typically twin shaft.The overall situation can be produced
The material of strain includes germanium silicon (SiGe on Insulator, SGOI) on insulating barrier, SiGe virtual substrate (SiGe virtual
Substrate) etc..Local train technology is generally only in the local of semiconductor device to semiconducting channel region applying stress.Office
Portion's strain gauge technique mainly has embedded germanium silicon (SiGe) of source-drain area or carborundum (SiC), dual stressed layers (Dual Stress
Layers, DSL) and shallow-trench isolation (Shallow Trench Isolation, STI) etc..Overall situation strain manufacture is complicated, cost compared with
Height, local train has good compatibility with traditional cmos manufacturing process and manufacture method is simple, so as to improve quasiconductor
A small amount of cost need to only be increased during device performance, industry is therefore suffered from and be widely applied.
For PMOS transistor, embedded germanium silicon (SiGe) technology can effectively improve hole mobility, so as to improve
The performance of PMOS transistor.So-called embedded germanium silicon technology is referred to and forms SiGe in the silicon substrate close to PMOS transistor raceway groove
Epitaxial layer, SiGe epitaxial layers can produce compressive stress to raceway groove, so as to improve the mobility in hole.
But, in order to realize that the purpose of carrier mobility is further improved in smaller size of device, then need to seek
Asking strengthens device channel stress aspect new breakthrough.
The content of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to provide a kind of PMOS transistor and its preparation
Method, present invention solves the technical problem that being to further enhance the pressure that source region and drain region produce raceway groove in device to answer
Power, so as to further improve carrier mobility in raceway groove, to increase the operating current of device.
For achieving the above object and other related purposes, the present invention provides a kind of preparation method of PMOS transistor, described
Preparation method is at least comprised the following steps：Semi-conductive substrate is provided, at the top of the Semiconductor substrate of pre-prepared PMOS transistor
Formation includes the active area of source region, drain region and channel region, and the source region and drain region are to the ditch
Road region applies compressive stress；Wherein, concretely comprising the following steps for the source region and drain region is prepared：
1）Groove is formed respectively in the position of the pre-prepared source region of the substrate top and drain region；
2）In the trench, the first stress of first epitaxial growth regulating course, then epitaxial growth the second stress regulating course, its
In, the lattice paprmeter of described substrate, the first stress regulating course and the second stress regulating course increases successively；
3）Repeat step 2）N time, n is for integer and more than or equal to 0；
4）When the second stress regulating course upper surface and the substrate upper surface at grade when, described
Groove upper surface epitaxial growth stress retaining layer filled with the first stress regulating course and the second stress regulating course, wherein, it is described
The material of stress retaining layer is consistent with the material of the first described stress regulating course or the second stress regulating course.
Alternatively, the step 3）When middle n is more than or equal to 1, adjust epitaxial growth the first stress in the trench
Layer and the second stress regulating course are spaced forming sandwich structure.
Alternatively, the step 2）When middle epitaxial growth the first stress regulating course and/or the second stress regulating course also simultaneously
The gas containing B element is passed through, to form the first stress regulating course and/or the second stress regulating course doped with B element.
Alternatively, the thickness of the stress retaining layer is 10 ~ 20nm.
Alternatively, the thickness of the first stress regulating course is 2 ~ 10nm.
Alternatively, the thickness of the second stress regulating course between two the first stress regulating courses is 20 ~ 30nm.
Alternatively, the backing material is Si, Si1-xCxOr Si1-x-yGeyCxAny one, wherein, the scope of x is
The scope of 0.01 ~ 0.1, y is 0.1 ~ 0.3；The first stress regulating course is SiGe layer；The second stress regulating course is SiSn
Layer or SiPb layers.
The present invention also provides a kind of PMOS transistor, and the PMOS transistor at least includes：
It is formed with the active area of channel region, source region and drain region, and the source region and drain region pair
The channel region applies compressive stress, and the source region and drain region are formed in Semiconductor substrate top；
The source region and drain region include that stress retaining layer and the m groups under the stress retaining layer are folded successively
Plus the first stress regulating course and the second stress regulating course for being formed on the first stress regulating course, wherein, m be integer and
The lattice paprmeter of substrate, the first stress regulating course and the second stress regulating course more than or equal to 1 and described increases successively, described
The material of stress retaining layer is consistent with the material of the first described stress regulating course or the second stress regulating course.
Alternatively, when m is more than or equal to 2, spaced the first stress regulating course and the three of the second stress regulating course composition
Mingzhi's structure.
Alternatively, B doped chemicals are contained in the first stress regulating course and/or the second stress regulating course.
Alternatively, the thickness of the stress retaining layer is 10 ~ 20nm.
Alternatively, the thickness of the first stress regulating course is 2 ~ 10nm.
Alternatively, the thickness of the second stress regulating course between two the first stress regulating courses is 20 ~ 30nm.
Alternatively, the backing material is Si, Si1-xCxOr Si1-x-yGeyCxAny one, wherein, the scope of x is
The scope of 0.01 ~ 0.1, y is 0.1 ~ 0.3；The first stress regulating course is SiGe layer；The second stress regulating course is SiSn
Layer or SiPb layers.
As described above, a kind of PMOS transistor of the present invention and preparation method thereof, has the advantages that：In order to enter one
Step improves the compressive stress of source region and drain region to raceway groove in PMOS transistor, then the present invention is in source region and drain region
During zone epitaxial growth, adopt atomic weight and lattice paprmeter bigger than Ge element and with substrate for same family Sn elements or Pb
Unit usually replaces Ge elements to be doped, therefore, source region and drain region produce pressure and answer to raceway groove from PMOS transistor
For the angle of power, with prior art using simple SiGe as source region and drain region compared with, the present invention is adopted
The source region and drain region of the overwhelming majority are formed with second stress regulating course of the lattice paprmeter more than SiGe, can be raceway groove
Bigger compressive stress is provided, carrier mobility higher in raceway groove is further realized, and then improves the operating current of device；Separately
Outward, the present invention is formed with the first stress regulating course as stress-buffer layer between the second stress regulating course and substrate, to reduce
Excessive lattice mismatch between second stress regulating course and substrate and the defect that causes；Meanwhile, the present invention adopts stress retaining layer
Stress holding is carried out to the epitaxially grown first, second stress regulating course in source region and drain region, it is to avoid source area
Domain and drain region Stress Release；Further, source region of the invention and drain region, also using spaced first,
The sandwich structure that second stress regulating course is constituted, is further reducing between the second stress regulating course and substrate due to excessive
Lattice mismatch and cause defect while, it is ensured that the present invention sandwich structure source region and drain region with it is existing
Technology compares can provide larger compressive stress for raceway groove.
Description of the drawings
Fig. 1 to Fig. 4 is shown as a kind of structure of each step of the preparation method of PMOS transistor in the embodiment of the present invention one and shows
It is intended to, wherein, Fig. 4 is shown as the structural representation of the PMOS transistor that the preparation method is formed.
Fig. 5 to Fig. 7 is shown as a kind of structure of each step of the preparation method of PMOS transistor in the embodiment of the present invention two and shows
It is intended to, wherein, Fig. 7 is shown as the structural representation of the PMOS transistor that the preparation method is formed.
Component label instructions
1 substrate
2 grooves
3 gate dielectric layers
4 grids
5 source regions, drain region
51 first stress regulating courses
52 second stress regulating courses
53 stress retaining layers
Specific embodiment
Embodiments of the present invention are illustrated below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands easily other advantages and effect of the present invention.The present invention can also pass through concrete realities different in addition
The mode of applying is carried out or applies, the every details in this specification can also based on different viewpoints with application, without departing from
Various modifications and changes are carried out under the spirit of the present invention.
Refer to Fig. 1 to Fig. 7.It should be noted that the diagram provided in the present embodiment only illustrates in a schematic way this
The basic conception of invention, only shows with relevant component in the present invention rather than according to package count during actual enforcement in schema then
Mesh, shape and size are drawn, and the kenel of each component, quantity and ratio can be a kind of random change during its actual enforcement, and its
Assembly layout kenel is likely to increasingly complex.
For PMOS transistor, embedded germanium silicon (SiGe) technology can effectively improve hole mobility, so as to improve
The performance of PMOS transistor.So-called embedded germanium silicon technology is referred to and forms SiGe in the silicon substrate close to PMOS transistor raceway groove
Epitaxial layer, SiGe epitaxial layers can produce compressive stress to raceway groove, so as to improve the mobility in hole.
But, in order to realize that the purpose of carrier mobility is further improved in smaller size of device, then need to seek
Asking strengthens device channel stress aspect new breakthrough.
In view of this, the invention provides a kind of preparation method of PMOS transistor, at least comprises the following steps：There is provided one
Semiconductor substrate, being formed at the top of the Semiconductor substrate of pre-prepared PMOS transistor includes source region, drain region and raceway groove
The active area in region, and the source region and drain region apply compressive stress to the channel region；Wherein, the source is prepared
Polar region domain and drain region concretely comprise the following steps：1）In the pre-prepared source region of the substrate top and the position of drain region
Put and formed respectively groove；2）In the trench, the first stress of first epitaxial growth regulating course, the stress of then epitaxial growth second is adjusted
Ganglionic layer, wherein, the lattice paprmeter of described substrate, the first stress regulating course and the second stress regulating course increases successively；3）Repeat
Step 2）N time, n is for integer and more than or equal to 0；4）When the upper surface of upper surface and the substrate of the second stress regulating course
When at grade, in the groove upper surface epitaxial growth for being filled with the first stress regulating course and the second stress regulating course
Stress retaining layer, wherein, the material of the stress retaining layer and the first described stress regulating course or the second stress regulating course
Material is consistent.
The present invention is mixed in epitaxial growth the second stress regulating course using the lattice paprmeter element bigger than Ge element
It is miscellaneous, make the second stress regulating course form the source region and drain region of the overwhelming majority, bigger compressive stress is provided for raceway groove, make
It has higher carrier mobility, and then improves the operating current of device；Formed between second stress regulating course and substrate
The first stress regulating course as stress-buffer layer, the defect caused with reducing lattice mismatch excessive therebetween；Meanwhile,
The present invention is carried out using stress retaining layer to the epitaxially grown first, second stress regulating course in source region and drain region
Stress keeps, it is to avoid source region and drain region Stress Release；The source region and drain region of the present invention is also using mutual
The sandwich structure that the first, second stress regulating course at interval is constituted, further reduces between the second stress regulating course and substrate
Excessive lattice mismatch and the defect that causes.
Embodiment one
As shown in Figures 1 to 4, the present invention provides a kind of preparation method of PMOS transistor, and the preparation method is at least wrapped
Include following steps：Semi-conductive substrate 1 is provided, being formed at the top of substrate 1 of pre-prepared PMOS transistor includes source region, leakage
Polar region domain and the active area of channel region, and the source region and drain region apply compressive stress to the channel region；Its
In, prepare concretely comprising the following steps for the source region and drain region：
Step 1 is first carried out）, as shown in figure 1, in the pre-prepared source region in the top of the substrate 1 and drain region
Position form groove 2 respectively, wherein, the shape in the section of the groove 2 is not limited, and can be circular or sigma shapes etc., at this
In embodiment, the cross sectional shape of groove 2 is as shown in Figure 1.It is pointed out that in Fig. 1, between the groove 2 and formed
In the surface of substrate 1 be gate dielectric layer 3 and grid 4.
It should be noted that the material of the substrate 1 is Si, Si1-xCx, Si1-x-yGeyCx, wherein, the scope of x is 0.01 ~
0.1, y scope is 0.1 ~ 0.3.In the present embodiment one, the substrate 1 is body silicon substrate, but is not limited thereto, another
In embodiment, when backing material is silicon, the substrate can also be the top layer silicon in the Semiconductor substrate with insulating buried layer.
Then execution step 2）.
In step 2）In, as shown in Figures 2 and 3, in the groove 2, the first stress of first epitaxial growth regulating course 51, and
The second stress of epitaxial growth regulating course 52 afterwards, wherein, described substrate 1, the first stress regulating course 51 and the second stress regulating course
52 lattice paprmeter increases successively；The first stress regulating course 51 is SiGe layer, and the second stress regulating course 52 is SiSn
Layer or SiPb layers；The thickness of the first stress regulating course is 2 ~ 10nm；The first stress of epitaxial growth regulating course 51 and/or second
Also simultaneously be passed through the gas containing B element during stress regulating course 52, with formed doped with B element the first stress regulating course 51 and/
Or the second stress regulating course 52, to reduce the resistance of the source region and drain region.
In the present embodiment one, the first stress regulating course 51 is SiGe layer, and the second stress regulating course 52 is
SiSn layers.In the present embodiment one, when temperature is 500 ~ 800 DEG C, in the substrate 1（Si）Groove 2 in epitaxial growth first should
Power regulating course 51, at the same using with substrate 1（Si）It is that the Ge elements of same family are doped growth, wherein, this contains the doping of Ge
Source flux is 0.1slm～1.0slm, is passed through the time for 10min ~ 30min；Further, in above-mentioned epitaxial process, also lead to
Enter the gas containing B element, to form the first stress regulating course 51 doped with B element（SiGe）, to reduce by first stress
The resistance of regulating course 51, in the present embodiment one, the first stress regulating course 51（SiGe）Thickness be preferably 6nm；Then
When temperature is 500 ~ 800 DEG C, the second stress of epitaxial growth regulating course 52 is continued on the first stress regulating course 51, using original
Son amount and lattice paprmeter is bigger than Ge element and and substrate（Si）Be same family Sn unit usually replace Ge elements mixed
It is miscellaneous, wherein, the doping source flux for containing Sn is 0.1slm ~ 1.0slm, and the time that is passed through is 10min ~ 60min, while in extension life
In growth process, also simultaneously the gas containing B element is passed through, to form the second stress regulating course 52 doped with B element（SiSn）, with
Reduce the resistance of the second stress regulating course 52.It should be noted that in another embodiment, when second stress is adjusted
When layer is SiPb, then Ge elements are usually replaced to be doped using Pb units.
It is pointed out that due to Sn atomic weighies and lattice paprmeter it is bigger than Ge element, therefore in the present embodiment, described
Two stress regulating courses 52（SiSn）Than the first stress regulating course 51（SiGe）It is bigger to the compressive stress of channel region, further
Carrier mobility higher in raceway groove is realized, and then improves the operating current of device；But, during epitaxial growth, if atom is brilliant
Lattice mismatch is excessive, then epitaxial layer can produce slight crack, forms excessive defect, not only affects the effect of extension, and cause source electrode,
Defect is very big at the PN junction position of drain region, causes device creepage to increase, therefore, the epitaxial growth institute in the groove 2
State the second stress regulating course 52（SiSn）Before, first in the substrate（Si）First stress regulating course 51 described in Epitaxial growth
（SiGe）, make the first stress regulating course 51（SiGe）The second stress regulating course 52 is formed at as stress-buffer layer
（SiSn）With substrate 1（Si）Between, to reduce the second stress regulating course 52（SiSn）With substrate（Si）Between excessive crystalline substance
Lattice mismatch and the defect that causes, so as to avoid device creepage from increasing；Further, the first stress regulating course 51（SiGe）Limit
The thin layer of 2 ~ 10nm thickness is made as, to ensure in the composite bed of the first stress regulating course 51 and the second stress regulating course 52, institute
Proportion that the second stress regulating course 52 accounts for is stated much larger than the proportion shared by the first stress regulating course 51, so that described compound
Effect of the layer than traditional simple use SiGe in terms of compressive stress is strengthened becomes apparent from.Then execution step 3）.
In step 3）In, repeat step 2）N time, n is for integer and more than or equal to 0；The step 3）When middle n is more than or equal to 1,
Make first stress regulating course and second stress regulating course of the epitaxial growth in the groove 2 spaced to form sandwich knot
Structure；The thickness of the second stress regulating course 52 between two the first stress regulating courses 51 is 20 ~ 30nm.In the present embodiment one
In, the n is 0, then in the groove 2, the first stress regulating course 51 and each epitaxial growth of the second stress regulating course 52
One layer.It is pointed out that the concrete condition when n is more than 0 refers to embodiment two.Then execution step 4）.
In step 4）In, as shown in figure 4, when the upper surface of the second stress regulating course 52 described in epitaxial growth and the substrate
1 upper surface at grade when, in the groove 2 for being filled with the first stress regulating course 51 and the second stress regulating course 52
Upper surface epitaxial growth stress retaining layer 53, so as to formed in the substrate 1 include the first stress regulating course 51, second should
The source region 5 and drain region 5 of power regulating course 52 and stress retaining layer 53.Wherein, the material of the stress retaining layer 53 with
Described the first stress regulating course 51 or the material of the second stress regulating course 52 is consistent, in other words, epitaxial growth stress retaining layer
Also the gas containing B element can be simultaneously passed through when 53, to form the stress retaining layer 53 doped with B element, to reduce the stress
The contact resistance of retaining layer 53；The thickness of the stress retaining layer 53 is 10 ~ 20nm.
It should be noted that the present invention is epitaxially grown in source region and drain region using stress retaining layer 53 pairs
First stress regulating course 51 and the second stress regulating course 52 carry out stress holding, it is to avoid the source region and drain region stress
Release.
In the present embodiment one, the material of the stress retaining layer 53 is the SiGe containing B doped chemicals, and it is with described first
The material of stress regulating course 51 is consistent, and the thickness of the stress retaining layer 53 is preferably 15nm.
As shown in figure 4, the present invention also provides a kind of PMOS transistor, the PMOS transistor at least includes：It is formed with ditch
The active area of road region, source region and drain region, and the source region and drain region apply to the channel region
Compressive stress, the source region and drain region are formed in the top of Semiconductor substrate 1.
The source region 5 and drain region 5 include stress retaining layer 53 and the m groups under the stress retaining layer 53
The first stress regulating course 51 being sequentially overlapped and the second stress regulating course 52 being formed on the first stress regulating course 51, its
In, m is the lattice of integer and substrate 1 more than or equal to 1 and described, the first stress regulating course 51 and the second stress regulating course 52
Constant increases successively, the material of the stress retaining layer 53 and described the first stress regulating course 51 or the second stress regulating course 52
Material it is consistent；When m is more than or equal to 2, spaced the first stress regulating course 51 and the three of the composition of the second stress regulating course 52
Mingzhi's structure, wherein, the source region 5 and drain region 5 it is undermost be the first stress regulating course 51, should try hard to keep with described
Hold that layer 53 contacts for the second stress of m groups regulating course 52, now, second between two the first stress regulating courses 51
The thickness of stress regulating course 52 is 20 ~ 30nm；The material of the substrate 1 is Si, Si1-xCx, Si1-x-yGeyCx, wherein, the scope of x
Scope for 0.01 ~ 0.1, y is 0.1 ~ 0.3；The first stress regulating course 51 is SiGe layer；The second stress regulating course 52
For SiSn layers or SiPb layers；Contain B doped chemicals in the first stress regulating course 51 and/or the second stress regulating course 52, by
It is consistent with the material of the first described stress regulating course 51 or the second stress regulating course 52 in the material of the stress retaining layer 53,
B doped chemicals then can also be contained in the stress retaining layer 53；The thickness of the first stress regulating course is 2 ~ 10nm；It is described
The thickness of stress retaining layer is 10 ~ 20nm.
It is pointed out that the upper surface of the second stress of m groups regulating course 52 is flat with the formation one of the upper surface of substrate 1
Face, and the stress retaining layer 53 is in the plane.
In the present embodiment one, as shown in figure 4, in the source region 5 and drain region 5, m values are 1, in other words,
The source region 5 and drain region 5 include stress retaining layer 53 and one layer first positioned at the stress retaining layer 53 under is answered
Power regulating course 51 and one layer of second stress regulating course 52 being formed on the first stress regulating course 51, and second stress tune
The upper surface of ganglionic layer 52 forms a plane with the upper surface of substrate 1, and the stress retaining layer 53 is located in the plane；The lining
Bottom 1 is body silicon substrate, but is not limited thereto, and in another embodiment, when backing material is silicon, the substrate can also be
Top layer silicon in Semiconductor substrate with insulating buried layer；The first stress regulating course 51 is SiGe, and preferred thickness is
6nm；The second stress regulating course 52 is SiSn layers；Contain in the first stress regulating course 51 and the second stress regulating course 52
B doped chemicals；The material of the stress retaining layer 53 is SiGe, and it keeps one with the material of the first stress regulating course 51
Cause, now the stress retaining layer 53 is the SiGe containing B doped chemicals, and the thickness of the stress retaining layer 53 is preferably
15nm.It is pointed out that concrete condition of the m values more than or equal to 2 refers to embodiment two.
A kind of PMOS transistor of the present invention and preparation method thereof, in order to further improve in PMOS transistor source region and
Compressive stress of the drain region to raceway groove, then it is of the invention at source region and drain region epitaxial growth, using atomic weight and crystalline substance
Lattice constant is bigger than Ge element and usually replaces Ge elements to be doped with the Sn elements or Pb unit that substrate is same family, because
This, from PMOS transistor source region and drain region for the angle that raceway groove produces compressive stress, with prior art in adopt
Compared with drain region as source region with simple SiGe, second stress of the present invention using lattice paprmeter more than SiGe
Regulating course forms the source region and drain region of the overwhelming majority, can provide bigger compressive stress for raceway groove, further realizes
Higher carrier mobility in raceway groove, and then improve the operating current of device；In addition, the present invention the second stress regulating course with
The first stress regulating course is formed between substrate as stress-buffer layer, it is excessive between the second stress regulating course and substrate to reduce
Lattice mismatch and the defect that causes；Meanwhile, the present invention is using stress retaining layer to the extension in source region and drain region
First, second stress regulating course of growth carries out stress holding, it is to avoid source region and drain region Stress Release；Further,
The source region and drain region of the present invention, the sandwich knot for also being constituted using first, second spaced stress regulating course
Structure, while the defect caused due to excessive lattice mismatch between the second stress regulating course and substrate is further reduced,
Ensure that the present invention sandwich structure source region and drain region compared with prior art can for raceway groove provide compared with
Big compressive stress.
Embodiment two
Embodiment two is essentially identical with the technical scheme of embodiment one, the difference is that only, preparation side in embodiment one
The step of method 3）Middle repeat step 2）N time, n values are 0；The source region and drain region of PMOS transistor in embodiment one
In domain, the m values of m groups the first stress regulating course and the second stress regulating course are 1；In the preparation method of the present embodiment two, step
Rapid 3）For repeat step 2）N time, n values are the integer more than 0；The source region of the PMOS transistor of the present embodiment two and
In drain region, the m values of m groups the first stress regulating course and the second stress regulating course are more than or equal to 2, and m is integer.This enforcement
With the something in common of embodiment one in example two, this is no longer going to repeat them, and the specific descriptions of related something in common refer to enforcement
Example one.
As shown in Figures 5 to 7, the present invention provides a kind of preparation method of PMOS transistor, the technology of the preparation method
Scheme is essentially identical with embodiment one, wherein, the concrete step for preparing the source region and drain region of the present embodiment two
In rapid, step 1）And step 2）Associated description refer to embodiment one, this is no longer going to repeat them.Then execution step 3）.
In step 3）In, repeat step 2）N time, n is for integer and more than or equal to 0；The step 3）When middle n is more than or equal to 1,
Make first stress regulating course 51 and second stress regulating course 52 of the epitaxial growth in the groove 2 spaced to form Sanming City
Control structure；The thickness of the second stress regulating course 52 between two the first stress regulating courses 51 is 20 ~ 30nm.
In the present embodiment two, as shown in Figures 5 and 6, n values are 1, then step 3）For repeat step 2）Once, so as to
In the groove 2, the first stress regulating course 51 and each epitaxial growth two-layer of the second stress regulating course 52, and described first
The spaced formation sandwich structure of 51 and second stress regulating course of stress regulating course 52；The thickness of the first stress regulating course 5
Spend for 2 ~ 10nm, preferably 6nm；The preferred thickness of the second stress regulating course 52 between two the first stress regulating courses 51
For 25nm.
It is pointed out that in the source region 5 and drain region 5 of the sandwich structure of the present embodiment two, not only
Two stress regulating courses 52（SiSn）And substrate（Si）Between be formed with the first stress regulating course 51（SiGe）, and in two-layer second
Stress regulating course 52（SiSn）Between be also formed with the first stress regulating course 51（SiGe）, reason is：Although obtaining from compressive stress
To farthest strengthening for angle, the proportion that the second stress regulating course 52 is accounted for is bigger and the first stress regulating course
Proportion shared by 51 gets over hour, then the compressive stress for providing is optimal cases, in other words, in the source region 5 and drain region 5
It is optimal cases only to include one layer of first ply stress regulating course 52 of stress regulating course 51 and（As described in embodiment one）, but have
Due to the first stress regulating course 51（SiGe）2 ~ 10nm is limited in, very thin, then the second stress of epitaxial growth regulating course 52
（SiSn）When still may there is lattice mismatch（dislocation）Defect so that source region 5 and drain region 5
Defect increase, cause device creepage to increase, therefore, sandwich structure is in order to by the second stress regulating course 52（SiSn）Pressure
The effect of stress increase produces lattice defect and is compromised and proposed with it.The sandwich structure final purpose is still to ensure
In source region 5 and drain region 5, compared with the first stress regulating course 51, occupy the second stress regulating course 52 big absolutely
Part, so as to play the effect of its compressive stress increase.
It is further noted that in the present embodiment two, positioned at the second stress regulating course 52（SiSn）And substrate（Si）
Between and positioned at the second stress of two-layer regulating course 52（SiSn）Between the first stress regulating course 51（SiGe）Play transition to delay
Punching is acted on, the mismatch excessive for adjusting lattice paprmeter, is further reduced between the second stress regulating course 52 and substrate 1 due to mistake
Big lattice mismatch and the defect that causes；Meanwhile, the first stress regulating course 51（SiGe）It is limited to the thin of 2 ~ 10nm thickness
Layer, to ensure in the composite bed of the first stress regulating course 51 and the second stress regulating course 52, the second stress regulating course 52
The proportion for accounting for is much larger than the proportion shared by the first stress regulating course 51, so that the composite bed is in terms of compressive stress is strengthened
Effect than traditional simple use SiGe becomes apparent from, therefore, the present invention sandwich structure source region and drain region with
Prior art compares can provide larger compressive stress for raceway groove.
Then perform and the identical step 4 of embodiment one）, particularly relevant description refers to embodiment one and Fig. 7.
As shown in fig. 7, the present invention also provides a kind of PMOS transistor, in the present embodiment two, the PMOS transistor
Technical scheme is essentially identical with embodiment one, the difference is that only：M groups the first stress regulating course of the present embodiment two and second
The m values of stress regulating course are more than or equal to 2, and remaining identical associated description refers to the particular content of embodiment one, and here is not
Repeat one by one again.
When m is more than or equal to 2, the sandwich that spaced the first stress regulating course 51 and the second stress regulating course 52 is constituted
Structure, wherein, the source region 5 and drain region 5 it is undermost be the first stress regulating course 51, with the stress retaining layer
53 contact for the second stress of m groups regulating course 52, now, the second stress between two the first stress regulating courses 51
The thickness of regulating course 52 is 20 ~ 30nm.
In the present embodiment two, as shown in fig. 7, in the source region 5 and drain region 5, m values are 2, in other words,
The source region 5 and drain region 5 include that stress retaining layer 53 and the two-layer first under the stress retaining layer 53 should
Power regulating course 51 and the second stress regulating course 52 being respectively formed on respectively the first stress regulating course 51, and spaced the
The sandwich structure that one stress regulating course 51 and the second stress regulating course 52 are constituted；Second group of second stress regulating course 52 it is upper
Surface forms a plane with the upper surface of substrate 1, and the stress retaining layer 53 is located in the plane；The substrate 1 is body silicon
Substrate；The first stress regulating course 51 is SiGe, and preferred thickness is 6nm；The second stress regulating course 52 is SiSn layers,
The thickness of the second stress regulating course 52 between two the first stress regulating courses 51 is preferably 25nm；First stress is adjusted
Contain B doped chemicals in the stress regulating course 52 of ganglionic layer 51 and second；The material of the stress retaining layer 53 be SiGe, its with it is described
The material of the first stress regulating course 51 is consistent, and now the stress retaining layer 53 is the SiGe containing B doped chemicals, and institute
The thickness for stating stress retaining layer 53 is preferably 15nm.
In sum, a kind of PMOS transistor of the invention and preparation method thereof, in order to further improve in PMOS transistor
The compressive stress of source region and drain region to raceway groove, then it is of the invention at source region and drain region epitaxial growth, adopt
Atomic weight and lattice paprmeter are bigger than Ge element and usually replace Ge elements to enter with Sn elements that substrate is same family or Pb units
Row doping, therefore, source region and drain region are and existing for the angle that raceway groove produces compressive stress from PMOS transistor
Compared with drain region as source region using simple SiGe in technology, the present invention is more than SiGe's using lattice paprmeter
Second stress regulating course forms the source region and drain region of the overwhelming majority, can provide bigger compressive stress for raceway groove, enters
One step realizes carrier mobility higher in raceway groove, and then improves the operating current of device；In addition, the present invention is in the second stress
The first stress regulating course is formed between regulating course and substrate as stress-buffer layer, to reduce the second stress regulating course and substrate
Between excessive lattice mismatch and the defect that causes；Meanwhile, the present invention is using stress retaining layer in source region and drain region
Epitaxially grown the one the second stress regulating course carries out stress holding in domain, it is to avoid source region and drain region Stress Release；
Further, source region of the invention and drain region, three for also being constituted using first, second spaced stress regulating course
Mingzhi's structure, in the defect for further reducing causing due to excessive lattice mismatch between the second stress regulating course and substrate
Simultaneously, it is ensured that the source region and drain region of the sandwich structure of the present invention can carry compared with prior art for raceway groove
For larger compressive stress.So, the present invention effectively overcomes various shortcoming of the prior art and has high industrial utilization.
The principle and its effect of above-described embodiment only illustrative present invention, it is of the invention not for limiting.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and the scope without prejudice to the present invention to above-described embodiment.Cause
This, such as those of ordinary skill in the art is complete with institute under technological thought without departing from disclosed spirit
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (14)
1. a kind of preparation method of PMOS transistor, it is characterised in that the preparation method is at least comprised the following steps：There is provided one
Semiconductor substrate, being formed at the top of the Semiconductor substrate of pre-prepared PMOS transistor includes source region, drain region and raceway groove
The active area in region, and the source region and drain region apply compressive stress to the channel region；Wherein, the source is prepared
Polar region domain and drain region concretely comprise the following steps：
1) groove is formed respectively in the position of the pre-prepared source region of the substrate top and drain region；
2) in the trench, the first stress of first epitaxial growth regulating course, then epitaxial growth the second stress regulating course, wherein,
The lattice paprmeter of described substrate, the first stress regulating course and the second stress regulating course increases successively；
3) repeat step 2) n time, n is for integer and more than or equal to 0；
4) when the second stress regulating course upper surface and the substrate upper surface at grade when, in the filling
There is the groove upper surface epitaxial growth stress retaining layer of the first stress regulating course and the second stress regulating course, wherein, the stress
The material of retaining layer is consistent with the material of the first described stress regulating course or the second stress regulating course；
Wherein, in the first stress regulating course Epitaxial growth the second stress regulating course, using atomic weight and lattice paprmeter
It is bigger than the first stress regulating course institute doped chemical and be usually doped with the unit that substrate is same family, so that institute
State the second stress regulating course bigger to the compressive stress of channel region than the first stress regulating course, so as to realize raceway groove in it is higher
Carrier mobility, and then improve device operating current；Wherein, the substrate is IV races element.
2. the preparation method of PMOS transistor according to claim 1, it is characterised in that：The step 3) in n more than etc.
When 1, make epitaxial growth the first stress regulating course in the trench and the second stress regulating course spaced to form three
Mingzhi's structure.
3. the preparation method of the PMOS transistor according to any one in claim 1 or 2, it is characterised in that：The step
It is rapid 2) in epitaxial growth the first stress regulating course and/or be also passed through the gas containing B element simultaneously during the second stress regulating course, with shape
Into the first stress regulating course and/or the second stress regulating course doped with B element.
4. the preparation method of PMOS transistor according to claim 1 and 2, it is characterised in that：The stress retaining layer
Thickness is 10～20nm.
5. the preparation method of PMOS transistor according to claim 1 and 2, it is characterised in that：First stress is adjusted
The thickness of layer is 2～10nm.
6. the preparation method of PMOS transistor according to claim 2, it is characterised in that：Adjust positioned at two the first stress
The thickness of the second stress regulating course between layer is 20～30nm.
7. the preparation method of PMOS transistor according to claim 1 and 2, it is characterised in that：The backing material be Si,
Si1-xCxOr Si1-x-yGeyCxAny one, wherein, the scope of x is 0.1～0.3 for the scope of 0.01～0.1, y；Described
One stress regulating course is SiGe layer；The second stress regulating course is SiSn layers or SiPb layers.
8. a kind of PMOS transistor, it is characterised in that the PMOS transistor at least includes：
The active area of channel region, source region and drain region, and the source region and drain region are formed with to described
Channel region applies compressive stress, and the source region and drain region are formed in Semiconductor substrate top；
The source region and drain region include what stress retaining layer and the m groups under the stress retaining layer were sequentially overlapped
First stress regulating course and the second stress regulating course being formed on the first stress regulating course, wherein, m is integer and is more than
The lattice paprmeter of substrate, the first stress regulating course and the second stress regulating course equal to 1 and described increases successively, the stress
The material of retaining layer is consistent with the material of the first described stress regulating course or the second stress regulating course；
Wherein, the atomic weight and lattice paprmeter of the second stress regulating course institute doped chemical is than the first stress regulating course institute
Doped chemical it is bigger and with the element that substrate is same family so that the second stress regulating course is adjusted than first stress
Layer is bigger to the compressive stress of channel region, so as to realize raceway groove in higher carrier mobility, and then improve the work of device
Electric current；Wherein, the substrate is IV races element.
9. PMOS transistor according to claim 8, it is characterised in that：When m is more than or equal to 2, spaced first should
The sandwich structure that power regulating course and the second stress regulating course are constituted.
10. PMOS transistor according to claim 8 or claim 9, it is characterised in that：The first stress regulating course and/or
Contain B doped chemicals in two stress regulating courses.
11. PMOS transistors according to claim 8 or claim 9, it is characterised in that：The thickness of the stress retaining layer be 10～
20nm。
12. PMOS transistors according to claim 8 or claim 9, it is characterised in that：The thickness of the first stress regulating course is
2～10nm.
13. PMOS transistors according to claim 9, it is characterised in that：Between two the first stress regulating courses
The thickness of the second stress regulating course is 20～30nm.
14. PMOS transistors according to claim 8 or claim 9, it is characterised in that：The backing material is Si, Si1-xCxOr
Si1-x-yGeyCxAny one, wherein, the scope of x is 0.1～0.3 for the scope of 0.01～0.1, y；First stress is adjusted
Ganglionic layer is SiGe layer；The second stress regulating course is SiSn layers or SiPb layers.
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| KR101657872B1 (en) * | 2014-12-23 | 2016-09-19 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Improved transistor channel |
| CN113948389B (en) * | 2021-08-30 | 2023-03-14 | 西安电子科技大学 | Silicon-based AlGaN/GaN HEMT based on SiSn epitaxial layer on back surface of substrate and preparation method |
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