CN102751331B - Strain SiGe square-in-square type channel NMOS (N-channel Metal Oxide Semiconductor) integrated device and preparation method thereof - Google Patents

Abstract

The invention provides a strain SiGe square-in-square type channel NMOS (N-channel Metal Oxide Semiconductor) integrated device which is suitable for an NMOS integrated device, and a preparation method of the strain SiGe square-in-square type channel NMOS integrated device by using a micron level process. The preparation method comprises the steps of: continuously growing a Si epitaxial layer, a first strain SiGe light doping drain region (LDD) electrode layer, a strain SiGe layer, a second strain SiGe LDD region layer and an N type Si layer; forming a drain region, a source region and a drain connecting region by using technical means such as chemical vapor deposition (CVD) and dry etching and finally forming an NMOS device; and photoetching a lead to form an NMOS integrated circuit. According to the invention, under the condition of no addition of any fund and equipment input, the stain SiGe square-in-square type vertical channel NMOS integrated device which is improved in property in comparison with a body Si NMOS is manufactured at low temperature.

Description

A kind of strain SiGe hollow raceway groove NMOS integrated device and preparation method

Technical field

The invention belongs to semiconductor integrated circuit technical field, particularly relate to a kind of micron order integrated circuit technology and prepare the strain SiGe hollow vertical-channel NMOS integrated device and preparation method that conducting channel length is 22 ~ 45nm.

Background technology

IC industry has the high multiplicity and degree of association for modern economy and social development.The development of integrated circuit technique and industry thereof, the development of consumer electronics industry, computer industry, communication industry and related industry can be promoted, integrated circuit (IC) chip, as the core of conventional industries intellectualized reconstruction, develops significant for the overall industrial level of lifting with promotion national economy and social informatization.As with fastest developing speed in human history, have the greatest impact, most widely used technology, integrated circuit has become the important symbol of measurement national science technical merit, overall national strength and a defense force.The technical performance of integrated circuit, industry size decide a National modern industrial or agricultural, the development level of defence equipment and the household electronic class consumer goods and international competitiveness, are the motive power of modern Economy Development.

Since first piece of silicon integrated circuit in 1958 is born, the development experience of integrated circuit integrated level is 10 ²~ 10 ³individual element little/medium-scale integration reaches 10 to current integrated level ⁹~ 10 ¹¹in multiple stages that the huge size of individual or more element is integrated, silicon materials are also impelled to become the leading role of semiconductor industry gradually.Along with researcher constantly furthers investigate the technology adopting silicon materials to manufacture integrated circuit, cause silicon technology integrated technology to reach its maturity, its improvement and bring new ideas constantly promotes integrated circuit and to march toward the new world of more high-performance, more high integration, higher reliability.At present, silicon technology has become the mainstream technology of IC industry, and silicon integrated circuit product is main product.Because this product cost is high, practical, in all microelectronic integrated circuit products, remain the monopoly position of more than 90% share., consider from the composite factor such as practicality, cost performance, system integration development trend of silicon technology integrated technology, estimate in decades to come in, other technique integrated technology still can not substitute or surmount silicon technology integrated technology meanwhile.

Continue to advance to promote semiconductor industry, the characteristic size of integrated circuit (IC)-components constantly reduces, and integration density improves constantly, and integrated scale increases rapidly.In the past few decades, with silicon be main rapidoprint microelectronics manufacture from micron technology nanometer technology till now, integrated circuit (IC) chip integrated level is more and more higher, and cost is more and more lower.But along with the characteristic line breadth of silicon integrated circuit enters nanoscale, SiO ₂the traditional materials such as gate dielectric material, polysilicon, silicide gate electrode are owing to being subject to the restriction of material behavior, cannot meet the demand of nanoscale devices and circuit, conventional device structure and technology also cannot meet the manufacture requirements of nanoscale devices and integrated circuit simultaneously, therefore, silicon microelectric technique is faced with stern challenge, and this present situation seriously constrains the development of semicon industry.

Summary of the invention

One is the object of the present invention is to provide to prepare strain SiGe hollow raceway groove NMOS integrated device preparation method with existing micro process, with realize do not change existing equipment and do not increase cost condition under, prepare the strain SiGe hollow vertical-channel NMOS integrated device that conducting channel is 22 ~ 45nm.

The object of the present invention is to provide a kind of strain SiGe hollow vertical-channel NMOS integrated device, the conducting channel of described device is hollow, and channel direction is vertical with substrate surface.

Further, channel region is strain SiGe material, and in raceway groove, Ge component changes in gradient, and is tensile strain at channel direction.

Further, described device is included in N-type Si epitaxial loayer, the first N-type strained sige layer, P type strained sige layer, the second N-type strained sige layer and N-type Si layer that substrate grows successively.

Further, described N-type Si epitaxy layer thickness is 1.5 ~ 2.5 μm, and doping content is 5 × 10 ¹⁹~ 5 × 10 ²⁰cm ^-3, as drain region; Described first N-type strain SiGe layer thickness is 3 ~ 5nm, and doping content is 5 × 10 ¹⁷~ 5 × 10 ¹⁸cm ^-3, Ge component is 10%, as the first lightly-doped source drain region (LDD) layer; Described P type strain SiGe layer thickness is 22 ~ 45nm, and doping content is 5 × 10 ¹⁶~ 5 × 10 ¹⁷cm ^-3, the gradient distribution that Ge component is lower floor is 10%, upper strata is 20 ~ 30%, as channel region; Described second N-type strain SiGe layer thickness is 3 ~ 5nm, and doping content is 5 × 10 ¹⁷~ 5 × 10 ¹⁸cm ^-3, Ge component is 20 ~ 30%, as the second lightly-doped source drain region (LDD) layer; Described N-type Si layer thickness is 200 ~ 400nm, and doping content is 5 × 10 ¹⁹~ 5 × 10 ²⁰cm ^-3, as source region.

Another object of the present invention is to provide a kind of method preparing strain SiGe hollow vertical-channel NMOS integrated device, carry out as follows:

The first step, to choose doping content be 5 × 10 ¹⁵~ 5 × 10 ¹⁶cm ^-3the P type Si substrate slice of left and right;

Second step, utilize the method for chemical vapor deposition (CVD), at 600 ~ 750 DEG C, growth five layer materials continuously on substrate: ground floor to be thickness the be N-type Si epitaxial loayer of 1.5 ~ 2.5 μm, doping content is 5 × 10 ¹⁹~ 5 × 10 ²⁰cm ^-3, as drain region; The second layer is thickness is 3 ~ 5nmN type strained sige layer, and doping content is 5 × 10 ¹⁷~ 5 × 10 ¹⁸cm ^-3, Ge component is 10%, as the first lightly-doped source drain region (LDD) layer; The P type strained sige layer of third layer to be thickness be 22 ~ 45nm, doping content is 5 × 10 ¹⁶~ 5 × 10 ¹⁷cm ^-3, Ge component is lower floor is 10%, and upper strata is the gradient distribution of 20 ~ 30%, as channel region; The N-type strained sige layer of the 4th layer of to be thickness be 3 ~ 5nm, doping content is 5 × 10 ¹⁷~ 5 × 10 ¹⁸cm ^-3, Ge component is 20 ~ 30%, as the second lightly-doped source drain region (LDD) layer; The N-type Si layer of layer 5 to be thickness be 200 ~ 400nm, doping content is 5 × 10 ¹⁹~ 5 × 10 ²⁰cm ^-3, as source region;

3rd step, photoetching isolation deep trouth district, utilize dry etch process, etch in isolated area the deep trouth that the degree of depth is 2.5 ~ 3.5 μm;

4th step, utilizing chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, is a SiO of 20 ~ 40nm at substrate surface deposition thickness ₂layer, all covers deep trouth inner surface, then deposit Poly-Si(polysilicon) fill up in deep trouth, form deep trench isolation;

5th step, photoetching source and drain isolated area, utilize dry etch process, etches in source and drain isolated area the shallow slot that the degree of depth is 0.5 ~ 0.7 μm; Recycling chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, fills SiO in shallow slot ₂; Finally, by chemico-mechanical polishing (CMP) method, remove unnecessary oxide layer, form shallow-trench isolation;

6th step, utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface deposit one deck SiO ₂and layer of sin, etch away SiN, SiO ₂formed and leak bonding pad window; Trench region is leaked in photoetching, utilizes dry etch process, etches the leakage groove that the degree of depth is 0.7 ~ 0.9 μm; Utilizing chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, is the 2nd SiO of 20 ~ 40nm at substrate surface growth thickness ₂layer, is formed and leaks trenched side-wall isolation, utilize dry etch process, remove the 2nd SiO of drain region channel bottom ₂layer.Utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, deposit doping content is 5 × 10 ¹⁹~ 5 × 10 ²⁰cm ^-3n-type Poly-Si will fill up groove, remove the Poly-Si of excess surface by chemico-mechanical polishing (CMP) method, formed and leak bonding pad;

7th step, utilize dry etch process, etch away SiN, SiO ₂barrier layer.Utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface deposit one deck SiO ₂and layer of sin, etch away SiN, SiO of gate region ₂form grid window.Utilize dry etch process, etch the gate groove that the degree of depth is 0.7 ~ 0.9 μm.Utilizing atomic layer chemical vapor deposit (ALCVD) method, at 300 ~ 400 DEG C, is the HfO of the high-k of 6 ~ 10nm at substrate surface deposition thickness ₂layer, as gate dielectric layer, at 600 ~ 800 DEG C, is 5 × 10 in substrate surface deposit one deck doping content ¹⁹~ 5 × 10 ²⁰cm ^-3n-type Poly-Si, and gate groove to be filled up, removes surface portion Poly-Si, form grid;

8th step, etching source region, formed nmos device;

9th step. utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface growth regulation four SiO ₂layer, and on grid, source and drain region lithography fair lead;

Tenth step, metallization, photoetching lead-in wire, form drain electrode, source electrode and gate metal lead-in wire, form the NMOS integrated circuit that conducting channel length is 22 ~ 45nm.

Further, channel length is determined according to the P type strain SiGe layer thickness of second step deposit.

Further, channel length gets 22 ~ 45nm.

Further, maximum temperature involved in this preparation method determines according to chemical vapor deposition (CVD) technological temperature in second, four, five, six, seven and nine steps, and maximum temperature is less than or equal to 800 DEG C.

Another object of the present invention is to the preparation method that a kind of strain SiGe hollow vertical-channel nmos device integrated circuit is provided, comprise the steps:

Step 1, epitaxial material preparation process:

(1a) choosing doping content is 5 × 10 ¹⁶cm ^-3the P type Si substrate slice of magnitude;

(1b) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, Grown a layer thickness be the N-type Si epitaxial loayer of 2 μm as drain region, doping content is 5 × 10 ²⁰cm ^-3;

(1c) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, be the first N-type strained sige layer of 3nm at Grown thickness, doping content is 5 × 10 ¹⁸cm ^-3, Ge component is 10%, as the first lightly-doped source drain region (LDD) layer;

(1d) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, Si epitaxial loayer grows a layer thickness be the P type SiGe layer of 22nm as channel region, doping content is 5 × 10 ¹⁷cm ^-3, the gradient distribution that Ge component is lower floor is 10%, upper strata is 30%;

(1e) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, be the second N-type strained sige layer of 3nm at Grown thickness, doping content is 5 × 10 ¹⁸cm ^-3, Ge component is 30%, as the second lightly-doped source drain region (LDD) layer;

(1f) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, on the sige layer grow a layer thickness be the N-type Si layer of 300nm as source region, doping content is 5 × 10 ²⁰cm ^-3;

Step 2, isolation preparation process:

(2a) photoetching isolation deep trouth district, utilizes dry etch process, etches in isolated area the deep trouth that the degree of depth is 3 μm;

(2b) utilizing chemical vapor deposition (CVD) method, at 800 DEG C, is a SiO of 40nm at substrate surface deposition thickness ₂layer, all covers deep trouth inner surface;

(2c) utilize chemical vapor deposition (CVD) method, at 800 DEG C, in deep trouth, fill Poly-Si, form deep trench isolation;

(2d) photoetching isolation deep trouth district, utilizes dry etch process, etches in source and drain isolated area the shallow slot that the degree of depth is 0.6 μm;

(2e) utilize chemical vapor deposition (CVD) method, at 800 DEG C, in shallow slot, fill SiO ₂;

(2f) by chemico-mechanical polishing (CMP) method, remove unnecessary oxide layer, form shallow-trench isolation;

Step 3, leak bonding pad preparation process:

(3a) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at substrate surface deposit one deck SiO ₂and layer of sin;

(3b) photoetching SiN and SiO ₂formed and leak bonding pad window;

(3c) utilize dry etch process, etch the leakage groove that the degree of depth is 0.8 μm;

(3d) utilizing chemical vapor deposition (CVD) method, at 800 DEG C, is the 2nd SiO of 40nm at substrate surface growth thickness ₂layer, is formed and leaks trenched side-wall isolation, utilize dry etch process, remove the 2nd SiO of drain region channel bottom ₂layer;

(3e) utilize chemical vapor deposition (CVD) method, at 800 DEG C, deposit doping content is 5 × 10 ²⁰cm ^-3n-type Poly-Si will fill up groove, remove the Poly-Si of excess surface by chemico-mechanical polishing (CMP) method, formed and leak bonding pad;

Step 4, NMOS forming step:

(4a) utilize dry etch process, etch away SiN and SiO ₂barrier layer;

(4b) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at substrate surface deposit one deck SiO ₂, then in deposit layer of sin above;

(4c) SiN and SiO of photoetching gate region ₂, form grid window;

(4d) utilize dry etch process, etch the gate groove that the degree of depth is 0.7 μm;

(4e) utilizing atomic layer chemical vapor deposit (ALCVD) method, at 400 DEG C, is the HfO of the high-k of 10nm at substrate surface growth thickness ₂layer, as gate dielectric layer;

(4f) utilizing chemical vapor deposition (CVD) method, at 800 DEG C, is 5 × 10 in substrate surface deposit doping content ²⁰cm ^-3n-type Poly-Si, and gate groove to be filled up, removes surface portion Poly-Si, form grid;

(4g) etch source region, form nmos device;

Step 5, forms NMOS integrated circuit step:

(5a) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at substrate surface growth regulation Three S's iO ₂layer;

(5b) lithography fair lead on grid, source and drain region;

(5c) metallize;

(5d) photoetching lead-in wire, forms drain metal lead-in wire, source metal lead-in wire and gate metal lead-in wire, forms the NMOS integrated circuit that conducting channel length is 22nm.

Tool of the present invention has the following advantages:

1. the strain SiGe nmos device channel direction that prepared by the present invention is the vertical direction of strained sige layer, then channel length is strain SiGe layer thickness, this thickness can be controlled by sige material growth technique, thus avoid small size photoetching, decrease the input of lithographic equipment, decrease process complexity, reduce cost;

2. in the strain SiGe nmos device prepared of the present invention, sige material is tensile strain along channel direction, tensile strain sige material electron mobility is higher than Si material, therefore, this performance such as device frequency and current driving ability is higher than the relaxation Si nmos device of same size;

3. the strain SiGe nmos device raceway groove that prepared by the present invention is hollow, namely grid can control raceway groove on four sides in the trench, therefore, this device adds the width of raceway groove in limited region, thus improve the current driving ability of device, add the integrated level of integrated circuit, reduce the manufacturing cost of lsi unit area;

4. in the strain SiGe NMOS raceway groove prepared of the present invention, Ge component changes in gradient, therefore can produce at channel direction the built-in field that is accelerated electron transport, enhance the carrier transport ability of raceway groove, thus improve frequency characteristic and the current driving ability of strain SiGe nmos device;

5., in the strain SiGe NMOS structure that prepared by the present invention, have employed the HfO of high-k ₂as gate medium, improve the grid-control ability of device, enhance the electric property of device;

6., in the strain SiGe nmos device that prepared by the present invention, in order to effectively suppress short-channel effect, introducing lightly-doped source drain region (LDD) technique, improve device performance;

7. the present invention prepares the maximum temperature related in strain SiGe vertical-channel nmos device process is 800 DEG C, lower than the technological temperature causing strain SiGe channel stress relaxation, therefore this preparation method can keep strain SiGe channel stress effectively, improves the performance of integrated circuit;

8. due to process proposed by the invention and existing micron order Si integrated circuit processing technology compatibility, therefore, can when any fund and equipment investment need not be added, prepare nmos device and integrated circuit that conducting channel length is 22 ~ 45nm, the manufacturing capacity of existing micron order Si integrated circuit technology platform is significantly improved, realizes the great-leap-forward development of domestic integrated circuit working ability.

Accompanying drawing explanation

Fig. 1 is the flow chart of the preparation method of strain SiGe hollow vertical-channel NMOS integrated device provided by the invention and circuit;

Fig. 2 is the process schematic prepared with the inventive method strain SiGe hollow raceway groove NMOS integrated device and circuit.

Embodiment

In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.

Embodiments provide a kind of strain SiGe hollow vertical-channel NMOS integrated device, the conducting channel of described device is hollow, and channel direction is vertical with substrate surface.

As a prioritization scheme of the embodiment of the present invention, channel region is strain SiGe material, and in raceway groove, Ge component changes in gradient, and is tensile strain at channel direction.

As a prioritization scheme of the embodiment of the present invention, described device is included in N-type Si epitaxial loayer, the first N-type strained sige layer, P type strained sige layer, the second N-type strained sige layer and N-type Si layer that substrate grows successively.

As a prioritization scheme of the embodiment of the present invention, described N-type Si epitaxy layer thickness is 1.5 ~ 2.5 μm, and doping content is 5 × 10 ¹⁹~ 5 × 10 ²⁰cm ^-3, as drain region; Described first N-type strain SiGe layer thickness is 3 ~ 5nm, and doping content is 5 × 10 ¹⁷~ 5 × 10 ¹⁸cm ^-3, Ge component is 10%, as the first lightly-doped source drain region (LDD) layer; Described P type strain SiGe layer thickness is 22 ~ 45nm, and doping content is 5 × 10 ¹⁶~ 5 × 10 ¹⁷cm ^-3, the gradient distribution that Ge component is lower floor is 10%, upper strata is 20 ~ 30%, as channel region; Described second N-type strain SiGe layer thickness is 3 ~ 5nm, and doping content is 5 × 10 ¹⁷~ 5 × 10 ¹⁸cm ^-3, Ge component is 20 ~ 30%, as the second lightly-doped source drain region (LDD) layer; Described N-type Si layer thickness is 200 ~ 400nm, and doping content is 5 × 10 ¹⁹~ 5 × 10 ²⁰cm ^-3, as source region.

Referring to accompanying drawing 1 and accompanying drawing 2, technological process prepared by strain SiGe hollow raceway groove NMOS integrated device of the present invention is described in further detail.

Embodiment 1: prepare strain SiGe hollow raceway groove NMOS integrated device and circuit that conducting channel is 45nm, concrete steps are as follows:

Step 1, prepared by epitaxial material, as shown in Figure 2 (a) shows.

(1a) choosing doping content is 10 ¹⁵cm ^-3the P type Si substrate slice 1 of left and right;

(1b) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, Grown a layer thickness be the N-type Si epitaxial loayer 2 of 2.5 μm as drain region, doping content is 5 × 10 ¹⁹cm ^-3;

(1c) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, be the N-type strained sige layer 3a of 5nm at Grown thickness, doping content is 5 × 10 ¹⁷cm ^-3, Ge component is 10%, as the first lightly-doped source drain region (LDD) layer;

(1d) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, Si epitaxial loayer grows a layer thickness be the P type SiGe layer 3 of 45nm as channel region, doping content is 5 × 10 ¹⁶cm ^-3, Ge component is lower floor is 10%, and upper strata is the gradient distribution of 20%;

(1e) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, be the N-type strained sige layer 3b of 5nm at Grown thickness, doping content is 5 × 10 ¹⁷cm ^-3, Ge component is 20%, as the second lightly-doped source drain region (LDD) layer;

(1f) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, on the sige layer grow a layer thickness be the N-type Si layer 4 of 400nm as source region, doping content is 5 × 10 ¹⁹cm ^-3.

Step 2, isolation preparation, as Suo Shi Fig. 2 (b) (left side is profile, and the right is vertical view).

(2a) photoetching isolation deep trouth district, utilizes dry etch process, etches in isolated area the deep trouth that the degree of depth is 3.5 μm;

(2b) utilizing chemical vapor deposition (CVD) method, at 600 DEG C, is a SiO of 20nm at substrate surface deposition thickness ₂layer 5, all covers deep trouth inner surface;

(2c) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in deep trouth, fill Poly-Si6, form deep trench isolation 7;

(2d) photoetching isolation deep trouth district, utilizes dry etch process, etches in source and drain isolated area the shallow slot that the degree of depth is 0.7 μm;

(2e) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in shallow slot, fill SiO ₂;

(2f) by chemico-mechanical polishing (CMP) method, remove unnecessary oxide layer, form shallow-trench isolation 8.

Step 3, leaks bonding pad preparation, as shown in Figure 2 (c) (left side is profile, and the right is vertical view).

(3a) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at substrate surface deposit one deck SiO ₂and layer of sin;

(3b) photoetching SiN, SiO ₂formed and leak bonding pad window;

(3c) utilize dry etch process, etch the leakage groove that the degree of depth is 0.9 μm;

(3d) utilizing chemical vapor deposition (CVD) method, at 600 DEG C, is the 2nd SiO of 20nm at substrate surface growth thickness ₂layer 9, is formed and leaks trenched side-wall isolation, utilize dry etch process, remove the 2nd SiO of drain region channel bottom ₂layer;

(3e) utilize chemical vapor deposition (CVD) method, at 600 DEG C, deposit doping content is 1 × 10 ²⁰cm ^-3n-type Poly-Si will fill up groove, remove the Poly-Si of excess surface by chemico-mechanical polishing (CMP) method, formed and leak bonding pad.

Step 4, NMOS is formed, as shown in Figure 2 (d) shows (left side is profile, and the right is vertical view).

(4a) utilize dry etch process, etch away SiN, SiO ₂barrier layer;

(4b) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at substrate surface deposit one deck SiO ₂and layer of sin;

(4c) SiN, SiO of photoetching gate region ₂, form grid window;

(4d) utilize dry etch process, etch the gate groove that the degree of depth is 0.9 μm;

(4e) utilizing atomic layer chemical vapor deposit (ALCVD) method, at 300 DEG C, is the HfO of the high-k of 6nm at substrate surface growth thickness ₂layer 11, as gate dielectric layer;

(4f) utilizing chemical vapor deposition (CVD) method, at 600 DEG C, is 1 × 10 in substrate surface deposit doping content ²⁰cm ^-3n-type Poly-Si 12, and gate groove to be filled up, removes surface portion Poly-Si, form grid;

(4g) etch source region 13, form nmos device 14.

Step 5, forms NMOS integrated circuit, as Suo Shi Fig. 2 (e) (left side is profile, and the right is vertical view).

(5a) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at substrate surface growth regulation four SiO ₂layer 15;

(5b) lithography fair lead on grid, source and drain region;

(5c) metallize;

(5d) photoetching lead-in wire, forms drain metal lead-in wire 16, source metal lead-in wire 17 and gate metal lead-in wire 18, forms the NMOS integrated circuit that conducting channel length is 45nm.

Embodiment 2: prepare strain SiGe hollow raceway groove NMOS integrated device and circuit that conducting channel is 30nm, concrete steps are as follows:

Step 1, prepared by epitaxial material, as shown in Figure 2 (a) shows.

(1a) choosing doping content is 5 × 10 ¹⁵cm ^-3the P type Si substrate slice 1 of left and right;

(1b) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, Grown a layer thickness be the N-type Si epitaxial loayer 2 of 2.5 μm as drain region, doping content is 1 × 10 ²⁰cm ^-3;

(1c) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, be the N-type strained sige layer 3a of 4nm at Grown thickness, doping content is 1 × 10 ¹⁸cm ^-3, Ge component is 10%, as the first lightly-doped source drain region (LDD) layer;

(1d) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, Si epitaxial loayer grows a layer thickness be the P type SiGe layer 3 of 30nm as channel region, doping content is 1 × 10 ¹⁷cm ^-3, Ge component is lower floor is 10%, and upper strata is the gradient distribution of 50%;

(1e) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, be the N-type strained sige layer 3b of 4nm at Grown thickness, doping content is 1 × 10 ¹⁸cm ^-3, Ge component is 50%, as the second lightly-doped source drain region (LDD) layer;

(1f) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, on the sige layer grow a layer thickness be the N-type Si layer 4 of 200nm as source region, doping content is 1 × 10 ²⁰cm ^-3.

Step 2, isolation preparation, as Suo Shi Fig. 2 (b) (left side is profile, and the right is vertical view).

(2a) photoetching isolation deep trouth district, utilizes dry etch process, etches in isolated area the deep trouth that the degree of depth is 2.5 μm;

(2b) utilizing chemical vapor deposition (CVD) method, at 700 DEG C, is a SiO of 30nm at substrate surface deposition thickness ₂layer 5, all covers deep trouth inner surface;

(2c) utilize chemical vapor deposition (CVD) method, at 700 DEG C, in deep trouth, fill Poly-Si6, form deep trench isolation 7;

(2d) photoetching isolation deep trouth district, utilizes dry etch process, etches in source and drain isolated area the shallow slot that the degree of depth is 0.5 μm;

(2e) utilize chemical vapor deposition (CVD) method, at 700 DEG C, in shallow slot, fill SiO ₂;

(2f) by chemico-mechanical polishing (CMP) method, remove unnecessary oxide layer, form shallow-trench isolation 8.

Step 3, leaks bonding pad preparation, as shown in Figure 2 (c) (left side is profile, and the right is vertical view).

(3a) chemical vapor deposition (CVD) method is utilized, at 700 DEG C, at substrate surface deposit one deck SiO ₂, and layer of sin;

(3b) photoetching SiN, SiO ₂formed and leak bonding pad window;

(3c) utilize dry etch process, etch the leakage groove that the degree of depth is 0.7 μm;

(3d) utilizing chemical vapor deposition (CVD) method, at 700 DEG C, is the 2nd SiO of 30nm at substrate surface growth thickness ₂layer 9, is formed and leaks trenched side-wall isolation, utilize dry etch process, remove the 2nd SiO of drain region channel bottom ₂layer;

(3e) utilize chemical vapor deposition (CVD) method, at 700 DEG C, deposit doping content is 5 × 10 ¹⁹cm ^-3n-type Poly-Si will fill up groove, remove the Poly-Si of excess surface by chemico-mechanical polishing (CMP) method, formed and leak bonding pad.

Step 4, NMOS is formed, as shown in Figure 2 (d) shows (left side is profile, and the right is vertical view).

(4a) utilize dry etch process, etch away SiN, SiO ₂barrier layer;

(4b) chemical vapor deposition (CVD) method is utilized, at 700 DEG C, at substrate surface deposit one deck SiO ₂and layer of sin;

(4c) SiN, SiO of photoetching gate region ₂, form grid window;

(4d) utilize dry etch process, etch the gate groove that the degree of depth is 0.7 μm;

(4e) utilizing atomic layer chemical vapor deposit (ALCVD) method, at 350 DEG C, is the HfO of the high-k of 8nm at substrate surface growth thickness ₂layer 11, as gate dielectric layer;

(4f) utilizing chemical vapor deposition (CVD) method, at 700 DEG C, is 5 × 10 in substrate surface deposit doping content ¹⁹cm ^-3n-type Poly-Si12, and gate groove to be filled up, removes surface portion Poly-Si, form grid;

(4g) etch source region 13, form nmos device 14.

Step 5, forms NMOS integrated circuit, as Suo Shi Fig. 2 (e) (left side is profile, and the right is vertical view).

(5a) chemical vapor deposition (CVD) method is utilized, at 700 DEG C, at substrate surface growth regulation four SiO ₂layer 15;

(5b) lithography fair lead on grid, source and drain region;

(5c) metallize;

(5d) photoetching lead-in wire, forms drain metal lead-in wire 16, source metal lead-in wire 17 and gate metal lead-in wire 18, forms the NMOS integrated circuit that conducting channel length is 30nm.

Embodiment 3: prepare strain SiGe hollow raceway groove NMOS integrated device and circuit that conducting channel is 22nm, concrete steps are as follows:

Step 1, prepared by epitaxial material, as shown in Figure 2 (a) shows.

(1a) choosing doping content is 10 ¹⁶cm ^-3the P type Si substrate slice 1 of left and right;

(1b) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, Grown a layer thickness be the N-type Si epitaxial loayer 2 of 2 μm as drain region, doping content is 5 × 10 ²⁰cm ^-3;

(1c) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, be the N-type strained sige layer 3a of 3nm at Grown thickness, doping content is 5 × 10 ¹⁸cm ^-3, Ge component is 10%, as the first lightly-doped source drain region (LDD) layer;

(1d) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, Si epitaxial loayer grows a layer thickness be the P type SiGe layer 3 of 22nm as channel region, doping content is 5 × 10 ¹⁷cm ^-3, Ge component is lower floor is 10%, and upper strata is the gradient distribution of 30%;

(1e) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, be the N-type strained sige layer 3b of 3nm at Grown thickness, doping content is 5 × 10 ¹⁸cm ^-3, Ge component is 30%, as the second lightly-doped source drain region (LDD) layer;

(1f) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, on the sige layer grow a layer thickness be the N-type Si layer 4 of 300nm as source region, doping content is 5 × 10 ²⁰cm ^-3.

Step 2, isolation preparation, as Suo Shi Fig. 2 (b) (left side is profile, and the right is vertical view).

(2a) photoetching isolation deep trouth district, utilizes dry etch process, etches in isolated area the deep trouth that the degree of depth is 3 μm;

(2b) utilizing chemical vapor deposition (CVD) method, at 800 DEG C, is a SiO of 40nm at substrate surface deposition thickness ₂layer 5, all covers deep trouth inner surface;

(2c) utilize chemical vapor deposition (CVD) method, at 800 DEG C, in deep trouth, fill Poly-Si6, form deep trench isolation 7;

(2d) photoetching isolation deep trouth district, utilizes dry etch process, etches in source and drain isolated area the shallow slot that the degree of depth is 0.6 μm;

(2e) utilize chemical vapor deposition (CVD) method, at 800 DEG C, in shallow slot, fill SiO ₂;

(2f) by chemico-mechanical polishing (CMP) method, remove unnecessary oxide layer, form shallow-trench isolation 8.

Step 3, leaks bonding pad preparation, as shown in Figure 2 (c) (left side is profile, and the right is vertical view).

(3a) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at substrate surface deposit one deck SiO ₂and layer of sin;

(3b) photoetching SiN, SiO ₂formed and leak bonding pad window;

(3c) utilize dry etch process, etch the leakage groove that the degree of depth is 0.8 μm;

(3d) utilizing chemical vapor deposition (CVD) method, at 800 DEG C, is the 2nd SiO of 40nm at substrate surface growth thickness ₂layer 9, is formed and leaks trenched side-wall isolation, utilize dry etch process, remove the 2nd SiO of drain region channel bottom ₂layer;

(3e) utilize chemical vapor deposition (CVD) method, at 800 DEG C, deposit doping content is 5 × 10 ²⁰cm ^-3n-type Poly-Si will fill up groove, remove the Poly-Si of excess surface by chemico-mechanical polishing (CMP) method, formed and leak bonding pad.

Step 4, NMOS is formed, as shown in Figure 2 (d) shows (left side is profile, and the right is vertical view).

(4a) utilize dry etch process, etch away SiN, SiO ₂barrier layer;

(4b) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at substrate surface deposit one deck SiO ₂, then in deposit layer of sin above;

(4c) SiN, SiO of photoetching gate region ₂, form grid window;

(4d) utilize dry etch process, etch the gate groove that the degree of depth is 0.7 μm;

(4e) utilizing atomic layer chemical vapor deposit (ALCVD) method, at 400 DEG C, is the HfO of the high-k of 10nm at substrate surface growth thickness ₂layer 11, as gate dielectric layer;

(4f) utilizing chemical vapor deposition (CVD) method, at 800 DEG C, is 5 × 10 in substrate surface deposit doping content ²⁰cm ^-3n-type Poly-Si 12, and gate groove to be filled up, removes surface portion Poly-Si, form grid;

(4g) etch source region 13, form nmos device 14.

Step 5, forms NMOS integrated circuit, as Suo Shi Fig. 2 (e) (left side is profile, and the right is vertical view).

(5a) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at substrate surface growth regulation four SiO ₂layer 15;

(5b) lithography fair lead on grid, source and drain region;

(5c) metallize;

(5d) photoetching lead-in wire, forms drain metal lead-in wire 16, source metal lead-in wire 17 and gate metal lead-in wire 18, forms the NMOS integrated circuit that conducting channel length is 22nm.

The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.

Claims (5)

1. a strain SiGe hollow vertical-channel NMOS integrated device, is characterized in that, the conducting channel of described device is hollow, and channel direction is vertical with substrate surface;

Channel region is strain SiGe material, and in raceway groove, Ge component changes in gradient, and is tensile strain at channel direction;

Described device is included in N-type Si epitaxial loayer, the first N-type strained sige layer, P type strained sige layer, the second N-type strained sige layer and N-type Si layer that substrate grows successively;

Described N-type Si epitaxy layer thickness is 1.5 ~ 2.5 μm, and doping content is 5 × 10 ¹⁹~ 5 × 10 ²⁰cm ^-3, as drain region; Described first N-type strain SiGe layer thickness is 3 ~ 5nm, and doping content is 5 × 10 ¹⁷~ 5 × 10 ¹⁸cm ^-3, Ge component is 10%, as the first lightly-doped source drain region (LDD) layer; Described P type strain SiGe layer thickness is 22 ~ 45nm, and doping content is 5 × 10 ¹⁶~ 5 × 10 ¹⁷cm ^-3, the gradient distribution that Ge component is lower floor is 10%, upper strata is 20 ~ 30%, as channel region; Described second N-type strain SiGe layer thickness is 3 ~ 5nm, and doping content is 5 × 10 ¹⁷~ 5 × 10 ¹⁸cm ^-3, Ge component is 20 ~ 30%, as the second lightly-doped source drain region (LDD) layer; Described N-type Si layer thickness is 200 ~ 400nm, and doping content is 5 × 10 ¹⁹~ 5 × 10 ²⁰cm ^-3, as source region.

2. a preparation method for strain SiGe hollow vertical-channel NMOS integrated device, is characterized in that, comprise the steps:

The first step, to choose doping content be 5 × 10 ¹⁵~ 5 × 10 ¹⁶cm ^-3p type Si substrate slice;

Second step, utilize the method for chemical vapor deposition (CVD), at 600 ~ 750 DEG C, growth five layer materials continuously on substrate: ground floor to be thickness the be N-type Si epitaxial loayer of 1.5 ~ 2.5 μm, doping content is 5 × 10 ¹⁹~ 5 × 10 ²⁰cm ^-3, as drain region; The first N-type strained sige layer of the second layer to be thickness be 3 ~ 5nm, doping content is 5 × 10 ¹⁷~ 5 × 10 ¹⁸cm ^-3, Ge component is 10%, as the first lightly-doped source drain region (LDD) layer; The P type strained sige layer of third layer to be thickness be 22 ~ 45nm, doping content is 5 × 10 ¹⁶~ 5 × 10 ¹⁷cm ^-3, the gradient distribution that Ge component is lower floor is 10%, upper strata is 20 ~ 30%, as channel region; The second N-type strained sige layer of the 4th layer of to be thickness be 3 ~ 5nm, doping content is 5 × 10 ¹⁷~ 5 × 10 ¹⁸cm ^-3, Ge component is 20 ~ 30%, as the second lightly-doped source drain region (LDD) layer; The N-type Si layer of layer 5 to be thickness be 200 ~ 400nm, doping content is 5 × 10 ¹⁹~ 5 × 10 ²⁰cm ^-3, as source region;

3rd step, photoetching isolation deep trouth district, utilize dry etch process, etch in isolated area the deep trouth that the degree of depth is 2.5 ~ 3.5 μm;

4th step, utilizing chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, is a SiO of 20 ~ 40nm at substrate surface deposition thickness ₂layer, all covered by deep trouth inner surface, then depositing polysilicon fills up in deep trouth, forms deep trench isolation;

5th step, photoetching source and drain isolated area, utilize dry etch process, etches in source and drain isolated area the shallow slot that the degree of depth is 0.5 ~ 0.7 μm; Recycling chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, fills SiO in shallow slot ₂; Finally, by chemico-mechanical polishing (CMP) method, remove unnecessary oxide layer, form shallow-trench isolation;

6th step, utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface deposit one deck SiO ₂and layer of sin, etch away SiN and SiO ₂formed and leak bonding pad window; Trench region is leaked in photoetching, utilizes dry etch process, etches the leakage groove that the degree of depth is 0.7 ~ 0.9 μm; Utilizing chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, is the 2nd SiO of 20 ~ 40nm at substrate surface growth thickness ₂layer, is formed and leaks trenched side-wall isolation, utilize dry etch process, remove the 2nd SiO of drain region channel bottom ₂layer; Utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, deposit doping content is 5 × 10 ¹⁹~ 5 × 10 ²⁰cm ^-3n-type polycrystalline silicon will fill up groove, remove the polysilicon of excess surface by chemico-mechanical polishing (CMP) method, formed and leak bonding pad;

7th step, utilize dry etch process, etch away SiN and SiO ₂barrier layer; Utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface deposit one deck SiO ₂and layer of sin, etch away SiN and SiO of gate region ₂form grid window; Utilize dry etch process, etch the gate groove that the degree of depth is 0.7 ~ 0.9 μm; Utilizing atomic layer chemical vapor deposit (ALCVD) method, at 300 ~ 400 DEG C, is the HfO of the high-k of 6 ~ 10nm at substrate surface deposition thickness ₂layer, as gate dielectric layer, at 600 ~ 800 DEG C, is 5 × 10 in substrate surface deposit one deck doping content ¹⁹~ 5 × 10 ²⁰cm ^-3n-type polycrystalline silicon, and gate groove to be filled up, removes surface portion polysilicon, form grid;

8th step, etching source region, form nmos device;

9th step, utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface growth regulation Three S's iO ₂layer, and on grid, source and drain region lithography fair lead;

Tenth step, metallization, photoetching lead-in wire, form drain electrode, source electrode and gate metal lead-in wire, form the NMOS integrated circuit that conducting channel length is 22 ~ 45nm.

3. the preparation method of strain SiGe hollow vertical-channel NMOS integrated device according to claim 2, is characterized in that, channel length is determined according to the P type strain SiGe layer thickness of second step deposit.

4. the preparation method of strain SiGe hollow vertical-channel NMOS integrated device according to claim 2, it is characterized in that, maximum temperature involved in this preparation method determines according to chemical vapor deposition (CVD) technological temperature in second, four, five, six, seven and nine steps, and maximum temperature is less than or equal to 800 DEG C.

5. a preparation method for strain SiGe hollow vertical-channel nmos device integrated circuit, is characterized in that, comprise the steps:

Step 1, epitaxial material preparation process:

(1a) choosing doping content is 5 × 10 ¹⁶cm ^-3the P type Si substrate slice of magnitude;

(1b) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, Grown a layer thickness be the N-type Si epitaxial loayer of 2 μm as drain region, doping content is 5 × 10 ²⁰cm ^-3;

(1c) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, be the first N-type strained sige layer of 3nm at Grown thickness, doping content is 5 × 10 ¹⁸cm ^-3, Ge component is 10%, as the first lightly-doped source drain region (LDD) layer;

(1d) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, Si epitaxial loayer grows a layer thickness be the P type SiGe layer of 22nm as channel region, doping content is 5 × 10 ¹⁷cm ^-3, the gradient distribution that Ge component is lower floor is 10%, upper strata is 30%;

(1e) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, be the second N-type strained sige layer of 3nm at Grown thickness, doping content is 5 × 10 ¹⁸cm ^-3, Ge component is 30%, as the second lightly-doped source drain region (LDD) layer;

(1f) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, on the sige layer grow a layer thickness be the N-type Si layer of 300nm as source region, doping content is 5 × 10 ²⁰cm ^-3;

Step 2, isolation preparation process:

(2a) photoetching isolation deep trouth district, utilizes dry etch process, etches in isolated area the deep trouth that the degree of depth is 3 μm;

(2b) utilizing chemical vapor deposition (CVD) method, at 800 DEG C, is a SiO of 40nm at substrate surface deposition thickness ₂layer, all covers deep trouth inner surface;

(2c) utilize chemical vapor deposition (CVD) method, at 800 DEG C, in deep trouth, fill polysilicon, form deep trench isolation;

(2d) photoetching isolation deep trouth district, utilizes dry etch process, etches in source and drain isolated area the shallow slot that the degree of depth is 0.6 μm;

(2e) utilize chemical vapor deposition (CVD) method, at 800 DEG C, in shallow slot, fill SiO ₂;

(2f) by chemico-mechanical polishing (CMP) method, remove unnecessary oxide layer, form shallow-trench isolation;

Step 3, leak bonding pad preparation process:

(3a) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at substrate surface deposit one deck SiO ₂and layer of sin;

(3b) photoetching SiN and SiO ₂formed and leak bonding pad window;

(3c) utilize dry etch process, etch the leakage groove that the degree of depth is 0.8 μm;

(3d) utilizing chemical vapor deposition (CVD) method, at 800 DEG C, is the 2nd SiO of 40nm at substrate surface growth thickness ₂layer, is formed and leaks trenched side-wall isolation, utilize dry etch process, remove the 2nd SiO of drain region channel bottom ₂layer;

(3e) utilize chemical vapor deposition (CVD) method, at 800 DEG C, deposit doping content is 5 × 10 ²⁰cm ^-3n-type polycrystalline silicon will fill up groove, remove the polysilicon of excess surface by chemico-mechanical polishing (CMP) method, formed and leak bonding pad;

Step 4, NMOS forming step:

(4a) utilize dry etch process, etch away SiN and SiO ₂barrier layer;

(4b) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at substrate surface deposit one deck SiO ₂, then in deposit layer of sin above;

(4c) SiN and SiO of photoetching gate region ₂, form grid window;

(4d) utilize dry etch process, etch the gate groove that the degree of depth is 0.7 μm;

(4e) utilizing atomic layer chemical vapor deposit (ALCVD) method, at 400 DEG C, is the HfO of the high-k of 10nm at substrate surface growth thickness ₂layer, as gate dielectric layer;

(4f) utilizing chemical vapor deposition (CVD) method, at 800 DEG C, is 5 × 10 in substrate surface deposit doping content ²⁰cm ^-3n-type polycrystalline silicon, and gate groove to be filled up, removes surface portion polysilicon, form grid;

(4g) etch source region, form nmos device;

Step 5, forms NMOS integrated circuit step:

(5a) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at substrate surface growth regulation Three S's iO ₂layer;

(5b) lithography fair lead on grid, source and drain region;

(5c) metallize;

(5d) photoetching lead-in wire, forms drain metal lead-in wire, source metal lead-in wire and gate metal lead-in wire, forms the NMOS integrated circuit that conducting channel length is 22nm.