CN103715092A - MOS tube and forming method thereof - Google Patents

MOS tube and forming method thereof Download PDF

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CN103715092A
CN103715092A CN201210379976.5A CN201210379976A CN103715092A CN 103715092 A CN103715092 A CN 103715092A CN 201210379976 A CN201210379976 A CN 201210379976A CN 103715092 A CN103715092 A CN 103715092A
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stressor layers
oxide
metal
semiconductor
semiconductor substrate
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CN103715092B (en
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赵猛
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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Abstract

Provided are a MOS tube and a forming method thereof. The forming method of the MOS tube comprises the following steps: providing a semiconductor substrate, wherein a dummy grid structure is formed on the surface of the semiconductor substrate, and a first stress layer is formed in the semiconductor substrate at the two sides of the dummy grid structure; forming an etching stop layer on the surface of the semiconductor substrate and the first stress layer, the surface of the etching stop layer being flush with the surface of the dummy grid structure; removing the dummy grid structure and forming an opening exposing part of the semiconductor substrate; forming a second stress layer in the semiconductor substrate at the bottom portion of the opening, the stress type of the second stress layer being opposite to the stress type of the first stress layer; and forming a grid structure disposed on the surface of the second stress layer, the grid structure being flush with the surface of the opening. The advantages are as follows: the carrier mobility of the formed MOS tube in a channel region is high, and the performance of the MOS tube is excellent.

Description

Metal-oxide-semiconductor and forming method thereof
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of metal-oxide-semiconductor and forming method thereof.
Background technology
In existing semiconductor device fabrication process, because stress can change energy gap and the carrier mobility of silicon materials, the performance that therefore improves metal-oxide-semiconductor by stress becomes more and more conventional means.Particularly, by suitable proof stress, can improve charge carrier (electronics in NMOS pipe, the hole in PMOS pipe) mobility, and then improve drive current, with this, greatly improve the performance of MOS transistor.
In prior art, the formation method of NMOS pipe of take describes as example, and it forms step and comprises:
Please refer to Fig. 1, p-type Semiconductor substrate 100 is provided, described p-type Semiconductor substrate 100 surfaces are formed with grid structure 101 and are positioned at the side wall 103 of described grid structure 101 both sides;
Please refer to Fig. 2, the described side wall 103 of take is mask, and p-type Semiconductor substrate 100 described in etching forms the opening 105 that is positioned at described grid structure both sides;
Please refer to Fig. 3, to described opening 105(as shown in Figure 2) the interior carbofrax material of filling, form stressor layers 107.
Yet the performance of the metal-oxide-semiconductor that prior art forms needs further to be improved.
More formation methods about metal-oxide-semiconductor, please refer to the United States Patent (USP) that the patent No. is " US6713359B1 ".
Summary of the invention
The problem that the present invention solves is to provide a kind of metal-oxide-semiconductor and forming method thereof, the superior performance of the metal-oxide-semiconductor of formation.
For addressing the above problem, embodiments of the invention provide a kind of formation method of metal-oxide-semiconductor, comprise: Semiconductor substrate is provided, and described semiconductor substrate surface is formed with dummy gate structure, and be formed with the first stressor layers in the Semiconductor substrate of described dummy gate structure both sides; Formation is positioned at the etching stop layer on described Semiconductor substrate and the first stressor layers surface, described etching stop layer and described dummy gate structure flush; Remove described dummy gate structure, form the opening that exposes part semiconductor substrate; In the Semiconductor substrate of described open bottom, form the second stressor layers, the stress types of described the second stressor layers is contrary with the stress types of the first stressor layers; Formation is positioned at the grid structure on described the second stressor layers surface, and described grid structure flushes with described open surfaces.
Alternatively, the formation step of described the second stressor layers is: along Semiconductor substrate described in described opening etching, form groove; The second stressor layers that formation is positioned at described groove and flushes with described semiconductor substrate surface.
Alternatively, also comprise: second stressor layers of returning etched portions thickness; On remaining the second stressor layers surface, form intrinsic layer.
Alternatively, the thickness of described intrinsic layer is 20 nanometer-100 nanometers.
Alternatively, when described metal-oxide-semiconductor is NMOS pipe, the material of described the first stressor layers is carborundum, and the material of described the second stressor layers is germanium silicon.
Alternatively, in described the first stressor layers, the molar percentage of carbon is 3%-10%.
Alternatively, in described the second stressor layers, the molar percentage of germanium is 20%-50%.
Alternatively, the thickness of described the first stressor layers is 50 nanometer-2 micron.
Alternatively, the thickness of described the second stressor layers is 50 nanometer-100 nanometers.
Alternatively, also comprise: before forming grid structure, to the ion that adulterates in described the second stressor layers, form voltage control layer.
Alternatively, also comprise: form the screen that is positioned at described voltage control layer bottom; Formation is positioned at the well region of described screen bottom.
Alternatively, when described metal-oxide-semiconductor is PMOS pipe, the material of described the first stressor layers is germanium silicon, and the material of described the second stressor layers is carbonization germanium.
Alternatively, the formation step of described the first stressor layers is: before forming dummy gate structure, form the first stress film that covers described Semiconductor substrate 200 surfaces; After dummy gate structure to be removed, along the first stress film described in opening etching, form the first stressor layers.
Alternatively, also comprise: form the tertiary stress layer that is positioned at described the first stressor layers surface, the material of described tertiary stress layer is silicon nitride.
Accordingly, embodiments of the invention also provide a kind of metal-oxide-semiconductor, comprising: Semiconductor substrate; Grid structure, described grid structure is positioned at described semiconductor substrate surface; The first stressor layers, described the first stressor layers is positioned at the Semiconductor substrate of described grid structure both sides; The second stressor layers, described the second stressor layers is positioned at the Semiconductor substrate of grid structure bottom, and its stress types is contrary with the stress types of the first stressor layers.
Alternatively, also comprise: be positioned at the intrinsic layer on described the second stressor layers surface, described intrinsic layer surface flushes with semiconductor substrate surface.
Alternatively, the thickness of described intrinsic layer is 20 nanometer-100 nanometers.
Alternatively, when described metal-oxide-semiconductor is NMOS pipe, the material of described the first stressor layers is carborundum, and the material of described the second stressor layers is germanium silicon.
Alternatively, in described the first stressor layers, the molar percentage of carbon is 3%-10%; In described the second stressor layers, the molar percentage of germanium is 20%-50%.
Alternatively, the thickness of described the first stressor layers is 50 nanometer-2 micron; The thickness of described the second stressor layers is 50 nanometer-100 nanometers.
Alternatively, when described metal-oxide-semiconductor is PMOS pipe, the material of described the first stressor layers is germanium silicon, and the material of described the second stressor layers is carbonization germanium.
Compared with prior art, technical scheme of the present invention has the following advantages:
While forming metal-oxide-semiconductor, on the one hand, in the Semiconductor substrate of dummy gate structure both sides, form the first stressor layers, for introducing tension stress or compression in the channel region of metal-oxide-semiconductor; On the other hand, after removing dummy gate structure formation opening, in the Semiconductor substrate of described open bottom, form the second stressor layers, be further that tension stress or compression are introduced in channel region, the carrier mobility of metal-oxide-semiconductor channel region is increased, improved the performance of metal-oxide-semiconductor.
Further, form before the second stressor layers, first along described opening etching semiconductor substrate-like, become groove, in etching semiconductor substrate-like, become in the process of groove, the first stressor layers is more obvious to the pulling force of Semiconductor substrate or pressure, is more conducive to follow-up more tension stress or the compression introduced in channel region.The carrier mobility of the metal-oxide-semiconductor forming is larger, and the performance of metal-oxide-semiconductor is more superior.
Further, return the second stressor layers of etched portions thickness, make the second stressor layers surface lower than semiconductor substrate surface, then the second stressor layers surface after etching forms intrinsic layer, because the material of intrinsic layer is comparatively pure, its inside ion that do not adulterate, is more conducive to the migration of charge carrier.The carrier mobility of the metal-oxide-semiconductor forming is larger, and the performance of metal-oxide-semiconductor is more superior.
The metal-oxide-semiconductor of the embodiment of the present invention, it is simple in structure, and source region and drain region are formed with the first stressor layers, and bottom, channel region is formed with the second stressor layers, tension stress or the compression of metal-oxide-semiconductor channel region are larger, and during work, the mobility of channel region charge carrier is higher, the superior performance of metal-oxide-semiconductor.
And, also comprise: be positioned at the intrinsic layer on described the second stressor layers surface, the ion that do not adulterate in described intrinsic layer, the carrier mobility of the channel region of metal-oxide-semiconductor is higher.
Accompanying drawing explanation
Fig. 1-Fig. 3 is the cross-sectional view of forming process of the NMOS pipe of prior art;
Fig. 4-Figure 12 is the cross-sectional view of the forming process of metal-oxide-semiconductor of the present invention;
Figure 13 is the schematic diagram that is related between the cut-off current of the metal-oxide-semiconductor that forms of prior art and the embodiment of the present invention and operating current;
Figure 14 is the schematic diagram that is related between the operating voltage of the metal-oxide-semiconductor that forms of prior art and the embodiment of the present invention and operating current.
Embodiment
As described in background, the performance of the metal-oxide-semiconductor of prior art needs further to be improved.
Through research, inventor's discovery, along with further dwindling of process node, prior art only forms stressor layers in source region and drain region, and comparatively limited for the stress that introduce channel region, although carrier mobility increases to some extent, what increase is comparatively limited.And the performance of metal-oxide-semiconductor and the carrier mobility of channel region have larger relation, therefore, it is comparatively limited that the performance of the metal-oxide-semiconductor of prior art strengthens.
After further research, inventor finds, for the corresponding position formation in the channel region germanium silicon layer of NMOS pipe, also can increase the stress of channel region charge carrier.Further, inventor finds, if in p-type Semiconductor substrate direct formation germanium silicon layer, then on described germanium silicon layer, form grid structure, be positioned at source region and the drain region of germanium silicon layer.Because described source region and drain region are also germanium silicon layer, also more limited to the stress increase of NMOS pipe channel region.
Further, inventor provides a kind of metal-oxide-semiconductor and forming method thereof, when forming metal-oxide-semiconductor, remove after the dummy gate structure of metal-oxide-semiconductor, continue downward etching semiconductor substrate-like and become groove, then in described groove, fill the material that can increase its tension stress or compression, the carrier mobility of the metal-oxide-semiconductor channel region obtaining is higher, the superior performance of metal-oxide-semiconductor.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing 4-Figure 14, the specific embodiment of the present invention is described in detail.Wherein, Fig. 4-Figure 12 is the cross-sectional view of the forming process of metal-oxide-semiconductor in the embodiment of the present invention, Figure 13 is the schematic diagram that is related between the cut-off current of the metal-oxide-semiconductor that forms of prior art and the embodiment of the present invention and operating current, and Figure 14 is the schematic diagram that is related between the operating voltage of the metal-oxide-semiconductor that forms of prior art and the embodiment of the present invention and operating current.
It should be noted that, because metal-oxide-semiconductor is according to the difference of doping type, be divided into NMOS pipe and PMOS pipe.For ease of understanding, following examples be take NMOS pipe and are carried out exemplary illustrated as example, and while forming PMOS pipe, the doping type of correspondence position and NMOS's is contrary.
Please refer to Fig. 4, Semiconductor substrate 200 is provided, described Semiconductor substrate 200 surfaces are formed with dummy gate structure 201 and are positioned at the side wall 203 of described dummy gate structure 201 both sides.
Described Semiconductor substrate 200 is used to subsequent technique that workbench is provided.Described Semiconductor substrate 200 is silicon substrate (Si) or silicon-on-insulator (SOI) substrate, and the crystal orientation of described Semiconductor substrate 200 is <110> or <100> etc.In an embodiment of the present invention, described Semiconductor substrate 200 is silicon substrate, and its material is monocrystalline silicon, and its crystal orientation is <100>.And owing to forming NMOS pipe, described Semiconductor substrate 200 is interior doped with p-type ion.
The rear extended meeting of described dummy gate structure 201 is removed, to form the second stressor layers and grid structure.The material of described dummy gate structure 201 is polysilicon or other materials, and while needing only subsequent etching, described dummy gate structure 201 is easily removed, and has larger etching selection ratio with Semiconductor substrate 200.In embodiments of the invention, the material of described dummy gate structure 201 is polysilicon.
Described side wall 203 is not damaged for follow-up grill-protected electrode structure, and for defining the position in source region and drain region.The material of described side wall 203 is silica, silicon nitride or silicon oxynitride.In an embodiment of the present invention, the material of described side wall 203 is silica.During follow-up removal dummy gate structure 201, described side wall 203 can not be damaged.
Because the formation method of dummy gate structure 201 and side wall 203 is well known to the skilled person, do not repeat them here.
It should be noted that, in embodiments of the invention, in described Semiconductor substrate 200, be also formed with fleet plough groove isolation structure 202, the material of described fleet plough groove isolation structure 202 is silica, for isolating adjacent metal-oxide-semiconductor.
Please refer to Fig. 5, the described dummy gate structure 201 of take is mask, Semiconductor substrate 200 described in etching, and interior formation the first stressor layers 205 of the Semiconductor substrate after etching 200.
The formation step of described the first stressor layers 205 is: described in etching, Semiconductor substrate 200, forms opening (not indicating); In described opening, fill stress material, form the first stressor layers 205.In embodiments of the invention, adopt dry etch process etching semiconductor substrate 200.Because the metal-oxide-semiconductor forming is NMOS pipe, the material of described the first stressor layers 205 is carborundum.Wherein the lattice constant of carbon atom is less than the lattice constant of silicon atom, can introduce tension stress to the channel region of described NMOS pipe, improves the carrier mobility of NMOS pipe channel region.
It should be noted that, when etching forms opening, not only there is longitudinally (perpendicular to the direction on Semiconductor substrate 200 surfaces) corrasion, also there is laterally (direction that is parallel to Semiconductor substrate 200 surfaces) corrasion, also can etched portions be positioned at the Semiconductor substrate 200 of side wall 203 bottoms.Therefore, part first stressor layers 205 of follow-up formation is positioned at side wall 203 bottoms.
Consider that the molar content of carbon in the first stressor layers 205 can have influence on the carrier mobility of channel region, still, if the molar content of carbon is too high, also likely bring the problems such as lattice defect.In the embodiment of the present invention, in described the first stressor layers 205, the molar percentage of carbon is 3%-10%, has both obtained higher carrier mobility, and the quality of the first stressor layers 205 forming is good.
Inventor's discovery, the thickness of the first stressor layers 205 also has impact to the carrier mobility of metal-oxide-semiconductor channel region.Described the first stressor layers 205 is too thin, and the tension stress of introducing is less; And described the first stressor layers 205 thick to a certain extent after, continue to increase, the increase of the carrier mobility of metal-oxide-semiconductor channel region is comparatively limited.For saving the process time that forms the first stressor layers 205, and make the carrier mobility of metal-oxide-semiconductor channel region reach higher, in embodiments of the invention, the thickness of described the first stressor layers 205 is 50 nanometer-2 micron.
It should be noted that, in an embodiment of the present invention, in described the first stressor layers 205, also comprise N-shaped ion, be used to form source region and drain region, described N-shaped ion can adopt the mode of Implantation to add, and does not repeat them here.
It should be noted that, in other embodiments of the invention, the formation step of described the first stressor layers 205 can also be: before forming dummy gate structure 201, form the first stress film (not shown) that covers described Semiconductor substrate 200 surfaces; After dummy gate structure 201 to be removed, along the first stress film described in opening etching and Semiconductor substrate 200, form the first stressor layers 205 and groove (as described later).Described the first stressor layers 205 is formed by the first stress film etching of one, is conducive to form in channel region stronger tension stress or compression.
Please refer to Fig. 6, form the etching stop layer 207 that is positioned at described Semiconductor substrate 200 and the first stressor layers 205 surfaces, described etching stop layer 207 and described dummy gate structure 201 flush.
Described etching stop layer 207 is not damaged in subsequent technique for the protection of the first stressor layers 205, and as the mask of etching dummy gate structure 201.The material of described etching stop layer 207 is silicon nitride, and it has larger etching selection ratio with polysilicon in etching technics.It is depositing operation that described etching stop layer 207 forms technique, does not repeat them here.
In embodiments of the invention, also comprise: form tertiary stress layer 206, described tertiary stress layer 206 is positioned at the first stressor layers 205 surfaces, for further strengthening the effect of stress to channel region, the dielectric material such as the material of described tertiary stress layer 206 is silicon nitride.
Please refer to Fig. 7, remove described dummy gate structure 201(as shown in Figure 6), form the opening 209 that exposes part semiconductor substrate 200.
Described opening 209 is for follow-up as process window, and the Semiconductor substrate 200 of etching bottom, forms the second stressor layers.The technique of removing described dummy gate structure 201 formation openings 209 is etching technics, for example anisotropic dry etch process.Because the technique of dry etching dummy gate structure 201 is well known to those skilled in the art, do not repeat them here.
It should be noted that, in other embodiments of the invention, while forming opening 209, can also remove side wall 203, so that the groove of follow-up formation 211 lateral dimensions are larger, follow-up the second stressor layers is connected with the first stressor layers 205 simultaneously.The carrier mobility of the channel region of the metal-oxide-semiconductor forming is larger.
Please refer to Fig. 8, the Semiconductor substrate 200 of opening 209 bottoms described in etching, forms groove 211.
Described groove 211 for filling germanium silicon material, forms the second stressor layers follow-up.The formation technique of described groove 211 is anisotropic dry etch process, its process parameters range is: etching gas comprises oxygen and bromize hydrogen gas, the flow of etching gas is 0.1 standard Liter Per Minute-1 standard Liter Per Minute, and the volume ratio between oxygen and hydrogen bromide is 1:0.2-1:0.4.In an embodiment of the present invention, the volume ratio of hydrogen and hydrogen bromide is 1:0.3 during described dry etch process.
It should be noted that, during due to dry etching Semiconductor substrate 200, not only Semiconductor substrate 200 to be had to etching longitudinally, it is laterally also had to certain corrasion, can etched portions be positioned at the Semiconductor substrate 200 of side wall 203 bottoms.Therefore, the lateral dimension of the groove 211 of formation is slightly larger than the lateral dimension of opening 209.
Inventor finds, at etching semiconductor substrate 200, forms in the process of groove 211, and the pulling force of 205 pairs of Semiconductor substrate 200 of the first stressor layers is more obvious, is more conducive to the follow-up more tension stress of introducing in channel region.In an embodiment of the present invention, the degree of depth of described groove 211 is 50 nanometer-100 nanometers, and the tension stress of the metal-oxide-semiconductor channel region of follow-up formation is larger.
Please refer to Fig. 9, form and to be positioned at described groove 211(as shown in Figure 8) and with the second stressor layers 213 of described Semiconductor substrate 200 flush, the stress types of described the second stressor layers 213 is contrary with the stress types of the first stressor layers 205.
Described the second stressor layers 213 is used to the channel region of metal-oxide-semiconductor that stress is provided.The formation technique of described the second stressor layers 213 is depositing operation, for example selective epitaxial depositing operation.Different from the position of the first stressor layers 205, described the second stressor layers 213 is positioned at described channel region or its bottom, for the channel region to the second metal-oxide-semiconductor provides larger stress, the stress types of described the second stressor layers 213 should be contrary with the stress types of the first stressor layers 205.In an embodiment of the present invention, the material of described the second stressor layers 213 should be selected germanium silicon.
In embodiments of the invention, because groove 211 is connected with the first stressor layers 205, therefore, in the second stressor layers 213 of groove 211 interior formation, be also connected with the first stressor layers 205.Stress in the channel region of the metal-oxide-semiconductor forming is larger, and carrier mobility during work is higher.
It should be noted that, in other embodiments of the invention, all right: between described the second stressor layers 213 and the first stressor layers 205, have part semiconductor substrate 200, the channel region of the metal-oxide-semiconductor of formation still has larger carrier mobility.
And, consider while forming NMOS pipe, the high tension stress that contributes to improve the channel region of NMOS pipe of the molar content of germanium in the second stressor layers 213, yet, when the molar content of germanium is too high, can be likely the new lattice defect of the interior introducing of Semiconductor substrate 200, the quality of the second stressor layers 213 also can be affected.Therefore,, in embodiments of the invention, in the situation that guarantee high tension stress, carrier mobility, Semiconductor substrate 200 and the second stressor layers 213, in described the second stressor layers 213, the molar percentage of germanium is 20%-50%.
For making the tension stress of metal-oxide-semiconductor channel region of follow-up formation larger, its carrier mobility is higher, and the performance of metal-oxide-semiconductor is more superior, and in embodiments of the invention, the thickness of described the second stressor layers 213 is 50 nanometer-100 nanometers.
It should be noted that, in other embodiments of the invention, can also directly on Semiconductor substrate 200 surfaces of described opening 209 bottoms, form germanium metal level (not shown); Described germanium metal level is annealed, make the germanium in germanium metal level enter interior formation the second stressor layers 213 of Semiconductor substrate 200, remove again afterwards remaining germanium metal level.
It should be noted that, in other embodiments of the invention, if while forming PMOS pipe, the material of described the first stressor layers 205 is germanium silicon, the material of described the second stressor layers is carbonization germanium.Do not repeat them here.
Please refer to Figure 10, return the second stressor layers 213(of etched portions thickness as shown in Figure 9), make remaining the second stressor layers 213a surface lower than described Semiconductor substrate 200 surfaces.
Inventor finds, when channel region exists stressor layers around, and channel region is while adopting pure semi-conducting material, and the carrier mobility of its channel region is higher.Therefore, return the second stressor layers 213 of etched portions thickness, part the second stressor layers 213 places that are etched are for follow-up formation intrinsic layer 215, to improve the carrier mobility of channel region.
It should be noted that, in embodiments of the invention, also comprise: before forming grid structure, to the ion that adulterates in described the second stressor layers, form voltage control layer (not shown), for regulating the threshold voltage (Vt) of metal-oxide-semiconductor, further to improve the performance of metal-oxide-semiconductor.
It should be noted that, in an embodiment of the present invention, also comprise: form the screen (not shown) that is positioned at described voltage control layer bottom, for isolation of semiconductor substrate 200, prevent the generation of leakage current; Formation is positioned at the well region (not shown) of described screen bottom, for further preventing the generation of leakage current, does not repeat them here.
It should be noted that, in other embodiments of the invention, also can be without etching the second stressor layers 213, but directly on the second stressor layers 213 surfaces, form grid structures, do not repeat them here.
Please refer to Figure 11, on remaining the second stressor layers 213a surface, form intrinsic layer 215.
The material of described intrinsic layer 215 is pure silicon, for the channel region as metal-oxide-semiconductor.The formation technique of described intrinsic layer 215 is depositing operation, selective epitaxial depositing operation for example, intrinsic layer 215 and described Semiconductor substrate 200 flush of formation.Inventor's discovery, channel region is usually located in the Semiconductor substrate 200 near grid structure bottom, and its thickness is less, for making position and the size of channel region just in time corresponding with size with the position of intrinsic layer 215.In embodiments of the invention, the thickness of described intrinsic layer is 20 nanometer-100 nanometers.
It should be noted that, for avoiding the interior doping ion of intrinsic layer 215, described voltage control layer, screen and well region formed before intrinsic layer 215, and preferably, described voltage control layer, screen and well region are returning shown in second stressor layers 213(Fig. 9 of etched portions thickness) rear formation.
Please refer to Figure 12, form the grid structure that is positioned at described intrinsic layer 215 surfaces, described grid structure and described opening 209(are as shown in figure 11) flush.
The step that forms grid structure comprises: form the gate dielectric layer 217 that covers described opening 209 bottoms and sidewall; Form the gate electrode layer 219 that covers described gate dielectric layer 217.Wherein, the formation technique of described gate dielectric layer 217 is depositing operation, atom layer deposition process for example, the material of described gate dielectric layer 217 is high K dielectric, for example one or more combinations in hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium oxide tantalum, hafnium oxide titanium, hafnium oxide zirconium; The formation technique of described gate electrode layer 219 is depositing operation, atom layer deposition process for example, and gate electrode layer 219 surfaces and described etching stop layer 207 flush of formation, the material of described gate electrode layer 219 is metal material, for example tungsten.
It should be noted that, in an embodiment of the present invention, also comprise: form the functional layer (not shown) between described gate dielectric layer 217 and gate electrode layer 219, for adjusting the work function of metal-oxide-semiconductor, further to improve the performance of metal-oxide-semiconductor.
After above-mentioned steps completes, the completing of the metal-oxide-semiconductor of the embodiment of the present invention.On the one hand, due to after removing dummy gate structure, continue along Semiconductor substrate described in opening etching, form groove, make the first stressor layers more obvious to the power of the fluted Semiconductor substrate of tool, follow-up more easily in larger tension stress or the compression of channel region formation; On the other hand, the second stressor layers forming in groove further forms larger tension stress or compression in channel region; Again on the one hand, the second stressor layers of follow-up time etched portions thickness, and the second stressor layers surface formation intrinsic layer after etching, described intrinsic layer is also more conducive to the carrier mobility of follow-up increase channel region.Therefore, the metal-oxide-semiconductor channel region carrier mobility that the embodiment of the present invention forms is high, and the performance of metal-oxide-semiconductor is more superior.
Accordingly, please continue to refer to Figure 12, in the embodiment of the present invention, also provide a kind of metal-oxide-semiconductor, having comprised:
Semiconductor substrate 200;
Grid structure, described grid structure is positioned at described Semiconductor substrate 200 surfaces;
The first stressor layers 205, described the first stressor layers 205 is positioned at the Semiconductor substrate 200 of described grid structure both sides;
The second stressor layers 213a, described the second stressor layers 213a is positioned at the Semiconductor substrate 200 of grid structure bottom, and its stress types is contrary with the stress types of the first stressor layers 205.
Wherein, described Semiconductor substrate 200 is silicon substrate (Si) or silicon-on-insulator (SOI), and the crystal orientation of described Semiconductor substrate 200 is <110> or <100> etc.In an embodiment of the present invention, described Semiconductor substrate 200 is silicon substrate, and its material is monocrystalline silicon, and its crystal orientation is <100>.And owing to forming NMOS pipe, described Semiconductor substrate 200 is interior doped with p-type ion.
Described grid structure comprises: cover the bottom of described opening and the gate dielectric layer of sidewall 217; Cover the gate electrode layer 219 of described gate dielectric layer 217.Wherein, the material of described gate dielectric layer 217 is high K dielectric, for example one or more combinations in hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium oxide tantalum, hafnium oxide titanium, hafnium oxide zirconium; Described gate electrode layer 219 surfaces and described etching stop layer 207 flush, the material of described gate electrode layer 219 is metal material, for example tungsten.
It should be noted that, in embodiments of the invention, also comprise: the functional layer (not shown) between described gate dielectric layer 217 and gate electrode layer 219, for adjusting the work function of metal-oxide-semiconductor, further to improve the performance of metal-oxide-semiconductor.
Described the first stressor layers 205 is for improving the carrier mobility of metal-oxide-semiconductor channel region.In embodiments of the invention, owing to forming NMOS pipe, the material of described the first stressor layers 205 is carborundum, and in described the first stressor layers 205, the molar percentage of carbon is 3%-10%, and the thickness of described the first stressor layers 205 is 50 nanometer-2 micron.And, in described the first stressor layers 205, also comprise N-shaped ion, be used to form source region and drain region, do not repeat them here.
Described the second stressor layers 213a is for improving the carrier mobility of metal-oxide-semiconductor channel region.In embodiments of the invention, the material of described the second stressor layers 213a is germanium silicon, and in described the second stressor layers 213a, the molar percentage of germanium is 20%-50%, and the thickness of described the second stressor layers 213a is 50 nanometer-100 nanometers.
It should be noted that, in an embodiment of the present invention, described the second stressor layers 213a surface is lower than described Semiconductor substrate 200 surfaces, and, described metal-oxide-semiconductor also comprises: be positioned at the intrinsic layer 215 on described the second stressor layers 213a surface, described intrinsic layer 215 surfaces and Semiconductor substrate 200 flush.The material of described intrinsic layer 215 is pure silicon, and its thickness is 20 nanometer-100 nanometers, to improve the carrier mobility of channel region.
It should be noted that, in embodiments of the invention, described the second stressor layers 213a is also doped with the p-type ion of variable concentrations, be formed be positioned at described grid structure bottom voltage control layer (not shown), be positioned at the screen of described voltage control layer bottom and be positioned at the well region of described screen bottom.More associated description please refer to the formation method of aforementioned metal-oxide-semiconductor.
It should be noted that, in other embodiments of the invention, when forming PMOS pipe, the material of described the first stressor layers 205 is germanium silicon, and the material of described the second stressor layers 213a is carborundum.
The metal-oxide-semiconductor of the embodiment of the present invention, usings intrinsic layer as channel region, and source region and drain region are formed with the first stressor layers, and bottom, channel region is formed with the second stressor layers.From a plurality of angles, be that tension stress or compression are introduced in channel region, make the channel region carrier mobility of the metal-oxide-semiconductor that forms larger, the performance of metal-oxide-semiconductor is more superior.
Incorporated by reference to reference to Figure 13 and Figure 14, Figure 13 shows respectively the schematic diagram that is related between the cut-off current of the metal-oxide-semiconductor that prior art and the embodiment of the present invention form and operating current, and Figure 14 shows the schematic diagram that is related to showing respectively between the operating voltage of the metal-oxide-semiconductor that prior art and the embodiment of the present invention form and operating current.From Figure 13 and Figure 14, under identical operating voltage or under cut-off current, the operating current of the metal-oxide-semiconductor that the embodiment of the present invention forms is larger, and performance is better.The size of described operating current is directly proportional to the height of the carrier mobility of metal-oxide-semiconductor channel region, and the metal-oxide-semiconductor that embodiment of the present invention forms is higher in the carrier mobility of channel region.
To sum up, while forming metal-oxide-semiconductor, on the one hand, in the Semiconductor substrate of dummy gate structure both sides, form the first stressor layers, for introducing tension stress or compression in the channel region of metal-oxide-semiconductor; On the other hand, after removing dummy gate structure formation opening, in the Semiconductor substrate of described open bottom, form the second stressor layers, be further that tension stress or compression are introduced in channel region, the carrier mobility of metal-oxide-semiconductor channel region is increased, improved the performance of metal-oxide-semiconductor.
Further, form before the second stressor layers, first along described opening etching semiconductor substrate-like, become groove, in etching semiconductor substrate-like, become in the process of groove, the first stressor layers is more obvious to the pulling force of Semiconductor substrate or pressure, is more conducive to follow-up more tension stress or the compression introduced in channel region.The carrier mobility of the metal-oxide-semiconductor forming is larger, and the performance of metal-oxide-semiconductor is more superior.
Further, return the second stressor layers of etched portions thickness, make the second stressor layers surface lower than semiconductor substrate surface, then the second stressor layers surface after etching forms intrinsic layer, because the material of intrinsic layer is comparatively pure, its inside ion that do not adulterate, is more conducive to the migration of charge carrier.The carrier mobility of the metal-oxide-semiconductor forming is larger, and the performance of metal-oxide-semiconductor is more superior.
The metal-oxide-semiconductor of the embodiment of the present invention, it is simple in structure, and source region and drain region are formed with the first stressor layers, and bottom, channel region is formed with the second stressor layers, tension stress or the compression of metal-oxide-semiconductor channel region are larger, and during work, the mobility of channel region charge carrier is higher, the superior performance of metal-oxide-semiconductor.
And, also comprise: be positioned at the intrinsic layer on described the second stressor layers surface, the ion that do not adulterate in described intrinsic layer, the carrier mobility of the channel region of metal-oxide-semiconductor is higher.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.

Claims (21)

1. a formation method for metal-oxide-semiconductor, is characterized in that, comprising:
Semiconductor substrate is provided, and described semiconductor substrate surface is formed with dummy gate structure, and is formed with the first stressor layers in the Semiconductor substrate of described dummy gate structure both sides;
Formation is positioned at the etching stop layer on described Semiconductor substrate and the first stressor layers surface, described etching stop layer and described dummy gate structure flush;
Remove described dummy gate structure, form the opening that exposes part semiconductor substrate;
In the Semiconductor substrate of described open bottom, form the second stressor layers, the stress types of described the second stressor layers is contrary with the stress types of the first stressor layers;
Formation is positioned at the grid structure on described the second stressor layers surface, and described grid structure flushes with described open surfaces.
2. the formation method of metal-oxide-semiconductor as claimed in claim 1, is characterized in that, the formation step of described the second stressor layers is: along Semiconductor substrate described in described opening etching, form groove; The second stressor layers that formation is positioned at described groove and flushes with described semiconductor substrate surface.
3. the formation method of metal-oxide-semiconductor as claimed in claim 2, is characterized in that, also comprises: second stressor layers of returning etched portions thickness; On remaining the second stressor layers surface, form intrinsic layer.
4. the formation method of metal-oxide-semiconductor as claimed in claim 3, is characterized in that, the thickness of described intrinsic layer is 20 nanometer-100 nanometers.
5. the formation method of metal-oxide-semiconductor as claimed in claim 1, is characterized in that, when described metal-oxide-semiconductor is NMOS pipe, the material of described the first stressor layers is carborundum, and the material of described the second stressor layers is germanium silicon.
6. the formation method of metal-oxide-semiconductor as claimed in claim 5, is characterized in that, in described the first stressor layers, the molar percentage of carbon is 3%-10%.
7. the formation method of metal-oxide-semiconductor as claimed in claim 5, is characterized in that, in described the second stressor layers, the molar percentage of germanium is 20%-50%.
8. the formation method of metal-oxide-semiconductor as claimed in claim 1, is characterized in that, the thickness of described the first stressor layers is 50 nanometer-2 micron.
9. the formation method of metal-oxide-semiconductor as claimed in claim 1, is characterized in that, the thickness of described the second stressor layers is 50 nanometer-100 nanometers.
10. the formation method of metal-oxide-semiconductor as claimed in claim 1, is characterized in that, also comprises: before forming grid structure, to the ion that adulterates in described the second stressor layers, form voltage control layer.
The formation method of 11. metal-oxide-semiconductors as claimed in claim 10, is characterized in that, also comprises: form the screen that is positioned at described voltage control layer bottom; Formation is positioned at the well region of described screen bottom.
The formation method of 12. metal-oxide-semiconductors as claimed in claim 1, is characterized in that, when described metal-oxide-semiconductor is PMOS pipe, the material of described the first stressor layers is germanium silicon, and the material of described the second stressor layers is carbonization germanium.
The formation method of 13. metal-oxide-semiconductors as claimed in claim 1, is characterized in that, the formation step of described the first stressor layers is: before forming dummy gate structure, form the first stress film that covers described Semiconductor substrate 200 surfaces; After dummy gate structure to be removed, along the first stress film described in opening etching, form the first stressor layers.
The formation method of 14. metal-oxide-semiconductors as claimed in claim 1, is characterized in that, also comprises: form the tertiary stress layer that is positioned at described the first stressor layers surface, the material of described tertiary stress layer is silicon nitride.
15. 1 kinds of metal-oxide-semiconductors, is characterized in that, comprising:
Semiconductor substrate;
Grid structure, described grid structure is positioned at described semiconductor substrate surface;
The first stressor layers, described the first stressor layers is positioned at the Semiconductor substrate of described grid structure both sides;
The second stressor layers, described the second stressor layers is positioned at the Semiconductor substrate of grid structure bottom, and its stress types is contrary with the stress types of the first stressor layers.
16. metal-oxide-semiconductors as claimed in claim 15, is characterized in that, also comprise: be positioned at the intrinsic layer on described the second stressor layers surface, described intrinsic layer surface flushes with semiconductor substrate surface.
17. metal-oxide-semiconductors as claimed in claim 16, is characterized in that, the thickness of described intrinsic layer is 20 nanometer-100 nanometers.
18. metal-oxide-semiconductors as claimed in claim 16, is characterized in that, when described metal-oxide-semiconductor is NMOS pipe, the material of described the first stressor layers is carborundum, and the material of described the second stressor layers is germanium silicon.
19. metal-oxide-semiconductors as claimed in claim 18, is characterized in that, in described the first stressor layers, the molar percentage of carbon is 3%-10%; In described the second stressor layers, the molar percentage of germanium is 20%-50%.
20. metal-oxide-semiconductors as claimed in claim 15, is characterized in that, the thickness of described the first stressor layers is 50 nanometer-2 micron; The thickness of described the second stressor layers is 50 nanometer-100 nanometers.
21. metal-oxide-semiconductors as claimed in claim 15, is characterized in that, when described metal-oxide-semiconductor is PMOS pipe, the material of described the first stressor layers is germanium silicon, and the material of described the second stressor layers is carbonization germanium.
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