CN104733311A - Fin-type field effect transistor forming method - Google Patents

Fin-type field effect transistor forming method Download PDF

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Publication number
CN104733311A
CN104733311A CN201310698622.1A CN201310698622A CN104733311A CN 104733311 A CN104733311 A CN 104733311A CN 201310698622 A CN201310698622 A CN 201310698622A CN 104733311 A CN104733311 A CN 104733311A
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fin
layer
semiconductor layer
field effect
formula field
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三重野文健
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The invention discloses a fin-type field effect transistor forming method. The forming method comprises steps: a semiconductor substrate is provided, wherein the semiconductor substrate is provided with an NMOS region and a PMOS region, a first fin part is formed on the PMOS region, and a second fin part is formed on the NMOS region; a first dielectric layer is formed on the semiconductor substrate; a gate structure crossing the first fin part and the second fin part is formed on the surface of the first dielectric layer; a mobile chemical vapor deposition process is adopted to form a second dielectric layer on the first dielectric layer; a part of the second dielectric layer at the top part of the first fin part at two sides of the gate structure is removed to enable the top surface of the first fin part to be exposed; a first semiconductor layer is formed on the surface of the first fin part; an oxide layer is formed on the surface of the second semiconductor layer; a part of the second dielectric layer at the top part of the second fin part at two sides of the gate structure is removed to enable the top surface of the second fin part to be exposed; and a second semiconductor layer is formed on the surface of the second fin part.

Description

The formation method of fin formula field effect transistor
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of formation method of fin formula field effect transistor.
Background technology
Along with the development of semiconductor process techniques, process node reduces gradually, and rear grid (gate-last) technique is widely applied, and to obtain desirable threshold voltage, improves device performance.But when the characteristic size of device declines further, even if grid technique after adopting, the structure of conventional metal-oxide-semiconductor field effect transistor also cannot meet the demand to device performance, and fin formula field effect transistor (Fin FET) obtains as a kind of multi-gate device and pays close attention to widely.
Fin formula field effect transistor is a kind of common multi-gate device, and Fig. 1 shows the perspective view of a kind of fin formula field effect transistor of prior art.
As shown in Figure 1, comprising: Semiconductor substrate 10, described Semiconductor substrate 10 is formed with the fin 11 of protrusion, fin 11 generally obtains after etching Semiconductor substrate 10; Dielectric layer 12, covers a part for the surface of described Semiconductor substrate 10 and the sidewall of fin 11; Grid structure 13, across on described fin 11, covers atop part and the sidewall of described fin 11, and grid structure 13 comprises gate dielectric layer (not shown) and is positioned at the gate electrode (not shown) on gate dielectric layer.For fin formula field effect transistor, the part that the top of fin 11 and the sidewall of both sides contact with grid structure 13 all becomes channel region, namely has multiple grid, is conducive to increasing drive current, improves device performance.
The performance of described fin formula field effect transistor needs further to be improved.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of fin formula field effect transistor, improves the performance of fin formula field effect transistor.
For solving the problem, the invention provides a kind of formation method of fin formula field effect transistor, comprise: Semiconductor substrate is provided, described Semiconductor substrate has NMOS area and PMOS area, and be positioned at the first fin in described PMOS area and the second fin in NMOS area, described Semiconductor substrate also has the first medium layer of surface lower than the top surface of the first fin and the second fin; The grid structure across described first fin and the second fin is formed on described first medium layer surface; First medium layer is formed the second dielectric layer of covering first fin and the second fin; Remove the second dielectric layer at the first fin top of grid structure both sides, expose the top surface of described first fin; Form the first semiconductor layer in described first fin portion surface, the overhead height of described first semiconductor layer is less than the height of grid structure; Remove the second dielectric layer at the second fin top of grid structure both sides, expose the top surface of the second fin; Form the second semiconductor layer in described second fin portion surface, the height of described second semiconductor layer is less than the height of grid structure.
Optionally, described first semiconductor layer is identical with the distance of the distance from top semiconductor substrate surface of the second semiconductor layer.
Optionally, mobility chemical vapor deposition method is adopted to form described second dielectric layer.
Optionally, the method forming described second dielectric layer comprises: on described first medium layer, form mobility layer of dielectric material, and described mobility layer of dielectric material covers the first fin and the second fin; Annealing in process is carried out to described mobility layer of dielectric material, forms second dielectric layer.
Optionally, spin coating proceeding is adopted to form described mobility layer of dielectric material.
Optionally, the material of described mobility layer of dielectric material at least comprises the one in silane, disilane, methyl-monosilane, dimethylsilane, trimethyl silane, tetramethylsilane, tetraethoxysilane, triethoxysilane, octamethylcy-clotetrasiloxane, tetramethyl disiloxane, tetramethyl-ring tetrasiloxane, trimethylsilyl amine, dimethyl silanyl amine.
Optionally, described annealing in process is at O 2, O 3, NO, H 2o steam, N 2, carry out under one or more gases in He, Ar, at least there is in described gas a kind of gas containing O.
Optionally, the temperature of described annealing in process is 200 DEG C ~ 1200 DEG C.
Optionally, also comprise: after the top surface exposing described first fin, remove described first fin, form groove at described semiconductor substrate surface, in described groove, form the first semiconductor layer, and the surface of described first semiconductor layer is higher than the surface of second dielectric layer.
Optionally, also comprise, before described second semiconductor layer of formation, adopt oxidation technology or atom layer deposition process to form oxide layer in the first semiconductor layer surface.
Optionally, the material of described oxide layer is silica.
Optionally, adopt selective epitaxial process to form described first semiconductor layer, described first semiconductor layer has compression.
Optionally, the material of described first semiconductor layer is SiGe.
Optionally, the shape of described first semiconductor layer is regular octahedron shape.
Optionally, adopt selective epitaxial process to form described second semiconductor layer, described second semiconductor layer has tensile stress.
Optionally, the material of described second semiconductor layer is silicon or carborundum.
Optionally, the shape of described second semiconductor layer is regular octahedron shape.
Optionally, be also included in described grid structure surface and the first fin and the second fin portion surface and form etching barrier layer.
Optionally, in the process forming described first semiconductor layer, carry out first in-situ doped to described first semiconductor layer, described first in-situ doped Doped ions is P type ion.
Optionally, in the process forming described second semiconductor layer, carry out second in-situ doped to described second semiconductor layer, described second in-situ doped Doped ions is N-type ion.
Optionally, also comprise: carry out light dope ion implantation and heavy doping ion injection in the second fin to described grid structure both sides, the Doped ions that described light dope ion implantation and heavy doping ion are injected is N-type ion.
Compared with prior art, technical scheme of the present invention has the following advantages:
Technical scheme of the present invention, after semiconductor substrate surface forms first medium, described first medium layer forms second dielectric layer, then removes the second dielectric layer at described first fin top, form the second semiconductor layer in described first fin portion surface; Remove the second dielectric layer at the second fin top, the second semiconductor layer is formed at the second fin top, height due to described first semiconductor layer and the second semiconductor layer is less than the height of grid structure, and described first semiconductor layer and the second semiconductor layer are positioned at above second dielectric layer, described second dielectric layer reduces the size of the first semiconductor layer and second semiconductor layer that can be formed, thus can avoid, between the first adjacent semiconductor layer and the second semiconductor layer, bridging phenomenon occurs, produce the problem such as electric leakage and affect the performance of device.
Further, form second dielectric layer by mobility chemical vapor deposition method on first medium layer, described mobility chemical vapor deposition method has higher deposition quality, can avoid forming cavity between the first adjacent fin and the second fin.
Further; technical scheme of the present invention is after described first semiconductor layer of formation; oxide layer is formed in described first semiconductor layer surface; can in the process of follow-up formation second semiconductor layer; protect described first semiconductor layer, avoid the material forming the second semiconductor layer in described first semiconductor layer surface extension.
Accompanying drawing explanation
Fig. 1 is the structural representation of the fin formula field effect transistor that prior art of the present invention is formed;
Fig. 2 to Figure 14 is the structural representation of the forming process of the fin formula field effect transistor of embodiments of the invention.
Embodiment
As described in the background art, the performance of the fin formula field effect transistor of prior art formation needs further to be improved.
Research finds, ion implantation is carried out to the source electrode of described fin formula field effect transistor and drain region, form source electrode and drain and easily cause more defect in described source electrode and drain region, and because the fin size of described fin field effect pipe is all less, the performance of the easier fin formula field effect transistor to being formed impacts.
The source electrode adopting in-situ doped technique to be formed on described fin formula field effect transistor fin and drain electrode can reduce the damage that ion implantation causes fin, but because the size of fin formula field effect transistor reduces gradually, spacing between the fin of adjacent N-type fin formula field effect transistor and P type fin formula field effect transistor is less, may bridging be there is between epitaxial loayer on the fin of described N-type fin formula field effect transistor and P type fin formula field effect transistor, cause producing electric leakage between described N-type fin formula field effect transistor and P type fin formula field effect transistor.
In embodiments of the invention, form described source electrode and drain electrode by epitaxy technique, the distance between described source electrode and drain electrode is comparatively large, can not produce bridging, affect the performance of device.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
Please refer to Fig. 2, provide Semiconductor substrate 100, described Semiconductor substrate has NMOS area and PMOS area.
The material of described Semiconductor substrate 100 comprises the semi-conducting materials such as silicon, germanium, SiGe, GaAs, can be body material also can be that composite construction is as silicon-on-insulator.Those skilled in the art can select the type of described Semiconductor substrate 100 according to the semiconductor device that Semiconductor substrate 100 is formed, therefore the type of described Semiconductor substrate should not limit the scope of the invention.
Described Semiconductor substrate 100 comprises: NMOS area and PMOS area, and described NMOS area is used for forming N-type fin formula field effect transistor within it, and described PMOS area is used for forming P type fin formula field effect transistor within it.
Be formed with P trap in described NMOS area, in described PMOS area, be formed with N trap.
Please refer to Fig. 3, the PMOS area of described Semiconductor substrate 100 is formed the first fin 110, forms the second fin 120 on an nmos area.
In the present embodiment, form Patterned masking layer on described Semiconductor substrate 100 surface, described Patterned masking layer defines position and the size of described first fin 110 and the second fin 120; With described Patterned masking layer for mask, etch described Semiconductor substrate 100, form the first fin 110 and the second fin 120.
In other embodiments of the invention, after described Semiconductor substrate 100 surface forms epitaxial loayer, described epitaxial loayer can also be etched and forms the first fin and the second fin.
Please refer to Fig. 4, described Semiconductor substrate 100 forms first medium layer 200, the surface of described first medium layer 200 is lower than the top surface of described first fin 110 and the second fin 120.
The material of described first medium layer 200 can be the insulating dielectric materials such as silica, silicon oxynitride, silicon oxide carbide.The method forming described first medium layer 200 comprises: at Semiconductor substrate 100 surface deposition first medium material, makes described first medium material cover described first fin 110 and the second fin 120; With the surface of described first fin 110 and the second fin 120 for stop-layer, carry out planarization to described first medium material, form first medium material layer, the surface of described first medium material layer flushes with the surface of the first fin 110 and the second fin 120; Etching is carried out back to described first medium material layer, makes the surface of described first medium material layer lower than the top surface of described first fin 110 and the second fin 120, form first medium layer 200.
Described first medium layer 200 is as the isolation structure between the first adjacent fin 110 or the second fin 120, and described first medium layer 200 can also as the isolation structure between the grid structure of follow-up formation and Semiconductor substrate 100.
Please refer to Fig. 5, form the grid structure 210 across described first fin 110 and the second fin 120 on described first medium layer 200 surface.
Described grid structure 210 comprises the gate dielectric layer 211 being positioned at described first medium layer 200 and the first fin 110, second fin 120 surface and the grid 212 being positioned at described gate dielectric layer 211 surface.
The material of described gate dielectric layer 211 can be SiO 2, HfO 2, La 2o 3, HfSiON, HfAlO 2.ZrO 2, Al 2o 3, HfSiO 4in one several.
The material of described grid 212 can be polysilicon, Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, WSi one or more.
After the described grid structure 210 of formation, form side wall, to protect described grid structure 210 in described grid structure 210 both sides.
Please refer to Fig. 6, for forming the schematic top plan view after described grid structure 210.
Described side wall 213 is positioned at the both sides of grid structure 210, owing to protecting described grid structure 210 in subsequent technique.
The first fin 110 that the part being positioned at grid structure 210 both sides is not capped and the second fin 120 are as the region of follow-up formation source electrode and drain electrode.
Please refer to Fig. 7, is the generalized section along the secant AA in described Fig. 6.
The first fin 110a shown in described Fig. 7 and the second fin 120a is respectively grid structure 210(and please refer to Fig. 6) not capped part first fin 110 of both sides and part second fin 120(please refer to Fig. 6).
Please refer to Fig. 8, form the etching barrier layer 201 covering described first fin 110a, the second fin 120a and grid structure 120 surface at described dielectric layer surface.
Described etching barrier layer 201 can adopt chemical vapor deposition method to be formed; described etching barrier layer 201 is for connecting described grid structure 210(please refer to Fig. 6 follow-up formation) and the through hole of source electrode or drain electrode time as etching barrier layer, protect the surface of described grid structure 210.
The material of described etching barrier layer 201 is silicon nitride.
Before the described etching barrier layer 201 of formation or afterwards, light dope ion implantation and middle Doped ions can be carried out to the second fin 120a of the grid structure both sides of described NMOS area and inject.The ionic type that described light dope ion implantation and heavy doping ion are injected is N-type ion, can be one or more in P, As or Sb.
Described light dope ion implantation and heavy doping ion are injected and can be introduced tensile stress in the injection zone of described second fin 120a, thus improve the mobility of the electronic carrier in described second fin 120a.The mobility of the tensile stress that described ion implantation technology produces to the holoe carrier of PMOS district P type fin formula field effect transistor to be formed is not then improved, so do not need carrying out light dope ion implantation in described first fin 110 and heavy doping ion is injected.
In other embodiments of the invention, also can not form described etching barrier layer, after waiting follow-up formation source electrode and drain electrode, form described etching barrier layer again.
Please refer to Fig. 9, form second dielectric layer 400 on described etching barrier layer 201 surface.
Flowable chemical vapor deposition method is adopted to form described second dielectric layer 400.
First, adopt spin coating proceeding to form mobility layer of dielectric material on etching barrier layer 201, the material of the layer of dielectric material of described mobility at least comprises the one in silane, disilane, methyl-monosilane, dimethylsilane, trimethyl silane, tetramethylsilane, tetraethoxysilane, triethoxysilane, octamethylcy-clotetrasiloxane, tetramethyl disiloxane, tetramethyl-ring tetrasiloxane, trimethylsilyl amine, dimethyl silanyl amine.
Because the integrated level of existing semiconductor chip is higher, the spacing before described first fin 110a and the second fin 120a is less, thus described groove has higher depth-to-width ratio.Because described mobility dielectric material has flowable, the groove between described adjacent first fin 110a and the second fin 120a can be filled preferably, avoid forming cavity in described groove.
In the present embodiment, the groove of the described mobility dielectric material filling part degree of depth, because described mobility dielectric material also has certain viscosity, can also on the sidewall of the top surface of described etching barrier layer 201 and the upper part groove be not filled the mobility layer of dielectric material of the surface adhesion layer of the first semiconductor layer 311.And general chemical meteorology deposition technique is in the groove process of filling described high-aspect-ratio, forms cavity in easy described groove, thus the isolation effect between adjacent transistor can be affected.
After the described mobility layer of dielectric material of formation, annealing in process is carried out to described mobility layer of dielectric material, form second dielectric layer 400.Described annealing is at O 2, O 3, NO, H 2o steam, N 2, carry out under one or more gases in He, Ar, at least there is in described gas a kind of gas containing O.Annealing region is 200 DEG C ~ 1200 DEG C, and pressure is 0.1T ~ 100T.
In annealing process, oxygen element and described mobility dielectric material form Si-O-Si key and replace the chemical bonds such as-Si-H-,-Si-N-,-Si-H-N-, form second dielectric layer 400.Described annealing in process makes the mobility layer of dielectric material originally with mobility and viscosity solidify to form second dielectric layer 400.
Described annealing in process makes the structure of the dielectric material in second dielectric layer 400 tightr, and removes the impurity such as part N, the H in material, repairs the defect in described second dielectric layer 400, improves isolation effect.
In other embodiments of the invention, also first thermal oxidation or wet process oxidation technology can be carried out to described mobility layer of dielectric material, described mobility dielectric material is made first to change into silica or silicon oxynitride, carry out annealing in process again, the gas of annealing process now can not have O atom, described annealing process can repair the fault of construction in second dielectric layer 400, improve the intensity of Si-O-Si key, remove the chemical bond such as the more weak-Si-H-of remaining chemical bond strength ,-Si-N-,-Si-H-N-simultaneously, reduce the impurity in second dielectric layer 400.
In the present embodiment, described second dielectric layer 400 is positioned at etching barrier layer 201 surface, fills the partial depth of the groove between adjacent first fin 110a and the second fin 120a, and the sidewall of the groove be not filled described in covering.
The thickness of the second dielectric layer 400 in described groove can be 1/3 ~ 3/4 of the first fin 110a or the second fin 120a height, to reduce the follow-up amount being positioned at the second dielectric layer 400 at the first fin 110a or the second fin 120a top needing to remove.
In other embodiments of the invention, described second dielectric layer 400 can also fill the groove between completely described adjacent first fin 110a and the second fin 120a.Described second dielectric layer 400 can also adopt the method such as chemical vapour deposition (CVD) or high-density plasma deposition process to be formed.
Please refer to Figure 10, described NMOS area is formed the first mask layer 301, with described first mask layer 301 for mask removes partial etching barrier layer 201 and the part second dielectric layer 400 at the first fin 110a top in described PMOS area, expose the top surface of described first fin 110a.
Described first mask layer 301 also covers the grid structure in described PMOS area, to protect the etching barrier layer on the grid structure surface in PMOS area.
Wet-etching technology can be adopted to remove the etching barrier layer 201 of described first fin 110a top surface, expose the first fin 110a top surface.In the present embodiment, the partial sidewall of part first fin 110a is also exposed.
Please refer to Figure 11, remove described first mask layer 301(and please refer to Figure 10), form the first semiconductor layer 311 at described first fin 110a top, the overhead height of described first semiconductor layer 311 is less than the overhead height of grid structure.
In the present embodiment, the material of described first semiconductor layer 311 is SiGe, there is compression, action of compressive stress can be produced to the first fin 110 as channel region below described grid structure by the first fin 110a, thus improve the mobility of the holoe carrier of the P type fin formula field effect transistor that described PMOS area is formed, thus improve described P type fin formula field effect transistor performance.
Selective epitaxial process can be adopted to form described first semiconductor layer 311.Concrete, the reaction temperature forming the selective epitaxial process of the first semiconductor layer 311 is 600 DEG C ~ 1100 DEG C, and pressure is that 1 holder ~ 500 are held in the palm, and silicon source gas is SiH 4or SiH 2cl 2, germanium source gas is GeH 4, also comprise HCl gas and H 2, wherein the flow of silicon source gas, germanium source gas, HCl is 1sccm ~ 1000sccm, H 2flow be 0.1slm ~ 50slm.
Because the lattice structure of described first semiconductor 311 according to the first fin 110a surface grows, due in described epitaxial process, different crystal orientations has different extension speed, so described first semiconductor layer 311 formed is regular octahedron shape.
Because the second fin 120a surface in described NMOS area has etching resistance layer 201 and second dielectric layer 400, so 311 meetings of described first semiconductor layer are formed on described first fin 110a surface.
Formed in the process of described first semiconductor layer 311 at employing epitaxy technique, described first semiconductor layer 311 is carried out first in-situ doped, described first in-situ doped Doped ions is P type ion, can be one or more ions in B, Ga or In, the doping content of described P type ion be 1E17atom/cm 3~ 1E20atom/cm 3, make described first semiconductor layer 311 as the source electrode of the P type fin formula field effect transistor that described PMOS area is formed or drain region.Adopt in-situ doped technique can avoid producing defect in described first semiconductor layer 311.
After described first semiconductor layer 311 of formation, annealing in process can also be carried out to described first semiconductor layer 311, to eliminate the defect that described first semiconductor layer 311 produces in epitaxial process, and activate described first in-situ doped P type Doped ions.
In other embodiments of the invention, can also after the surface exposing described first fin 110a, remove described first fin 110a and form groove, and then extension forms described first semiconductor layer 311 in described groove, and make the surface of surface higher than second dielectric layer 400 of described first semiconductor layer 311.Described like this first semiconductor layer 311 directly can contact with the first fin as channel region below grid structure, larger action of compressive stress is produced to described channel region, improves the mobility of the holoe carrier of P type fin formula field effect transistor to be formed further.
Please refer to Figure 12, form oxide layer 321 on described first semiconductor layer 311 surface.
Oxidation technology can be adopted to form described oxide layer 321 on described first semiconductor layer 311 surface.The material of described oxide layer 321 is silica.
In the present embodiment, adopt the rapid thermal anneal process under oxygen atmosphere, by described first semiconductor layer 311 surface oxidation, form described oxide layer 321.
In other embodiments of the invention, can also adopt atom layer deposition process, in described first semiconductor layer 311 surface deposition oxide layer 321, described oxide layer 321 also covers second dielectric layer 400 surface in NMOS area simultaneously.
Described oxide layer 321 for protecting the surface of described first semiconductor layer 311 in subsequent technique.
Please refer to Figure 13, described PMOS area is formed the second mask layer 302, with described second mask layer 302 for mask, remove the part second dielectric layer 400 and the etching barrier layer 201 that are positioned at described second fin 120a top, expose the top surface of described second fin 120a.
Described second mask layer 302 also covers the grid structure in described NMOS area, to protect the etching barrier layer on the grid structure surface in NMOS area.
Wet-etching technology can be adopted to remove the etching barrier layer 201 of described second fin 120a top surface, expose and be positioned at the second fin 120a top surface.In the present embodiment, the partial sidewall of part second fin 120a is also exposed.
Please refer to Figure 14, remove described second mask layer 302(and please refer to Figure 13), form the second semiconductor layer 312 at described second fin 120a top, the overhead height of described second semiconductor layer 312 is less than the overhead height of grid structure.
The material of described second semiconductor layer 312 can be silicon or carborundum.
In the present embodiment, the material of described second semiconductor layer 312 is carborundum, has tensile stress.Adopt carborundum can produce action of pulling stress by the second fin 120a below it to part second fin as channel region covered by described grid structure as the second semiconductor layer 312, thus improve the electronic carrier mobility of the N-type fin formula field effect transistor formed on an nmos area, thus improve the performance of described N-type fin formula field effect transistor.
Selective epitaxial process is adopted to form described insulated epitaxial silicon carbide layer as the second semiconductor layer 312 on described second fin 120a surface.Concrete, the reaction temperature of described selective epitaxial process is 600 DEG C ~ 1100 DEG C, and pressure is that 1 holder ~ 500 are held in the palm, and silicon source gas is SiH 4or SiH 2cl 2, carbon-source gas is CH 4, also comprise HCl gas and H 2, wherein the flow of silicon source gas, carbon-source gas, HCl is 1sccm ~ 1000sccm, H 2flow be 0.1slm ~ 50slm.
Because the lattice structure of described second semiconductor 312 according to the second fin 120a surface grows, due in described epitaxial process, different crystal orientations has different extension speed, so described second semiconductor layer 312 formed is regular octahedron shape.
Because the first semiconductor layer 311 surface in described PMOS area has oxide layer 321, so 312 meetings of described second semiconductor layer are formed on described second fin 120a surface and can not form described second semiconductor layer on described first semiconductor layer 311 surface.
Formed in the process of described second semiconductor layer 312 at employing selective epitaxial process, the second in-situ doped technique can also be adopted, doped N-type ion in described second semiconductor layer 312, such as, one or more ions in P, Ga or As, the doping content of described N-type ion is 1E17atom/cm 3~ 1E20atom/cm 3, make the second fin 120a of described second semiconductor layer 312 and below thereof become source electrode and the drain electrode of the N-type fin formula field effect transistor that described NMOS area is formed.Adopt in-situ doped technique, can avoid producing defect in described second semiconductor layer 312.
In other embodiments of the invention, can also after the surface exposing described second fin 120a, remove described second fin 120a and form groove, and then extension forms described second semiconductor layer 312 in described groove, and make the surface of surface higher than second dielectric layer 400 of described second semiconductor layer 312.Described like this second semiconductor layer 312 directly can contact with the second fin as channel region below grid structure, larger tensile stress effect is produced to described channel region, improves the mobility of the electronic carrier of N-type fin formula field effect transistor to be formed further.
The overhead height of described second semiconductor layer 312 is identical with the height of described first semiconductor layer 311, and namely described first semiconductor layer 311 is identical with the distance on distance from top Semiconductor substrate 100 surface of the second semiconductor layer 312.Metal plug can be formed on described first semiconductor layer 311 and the second semiconductor layer 312 so that follow-up simultaneously, be reduced in the difficulty of described first semiconductor layer 311 and the second semiconductor layer 312 surface formation metal plug.
The overhead height of described first semiconductor layer 311 and the second semiconductor layer 312 is less than the overhead height of grid structure, dielectric layer between subsequently formed layer can be avoided to carry out in the process of planarization, damage is caused to described first semiconductor layer 311 and the second semiconductor layer 312.
Because described first semiconductor layer 311 is identical with the overhead height of the second semiconductor layer 312, so described first semiconductor layer 311 is identical or close with the length of side of the second semiconductor layer 312.Because described first medium layer 200 surface is formed with diffusion impervious layer 201 and second dielectric layer 400, described first semiconductor layer 311 and the second semiconductor layer 312 are positioned at above described second dielectric layer 400, overhead height due to described first semiconductor layer 311 and the second semiconductor layer 312 is less than the height of grid structure, so the size of the first semiconductor layer 311 above described second dielectric layer and the second semiconductor layer 312 is less, can not make to produce bridging between described the first adjacent semiconductor layer 311 and the second semiconductor layer 312 layers.
Due to the first fin 110a of finally being formed and the second fin 120a be octagon due to described first semiconductor layer 311 and the second semiconductor layer 312 part be positioned at above second dielectric layer 400, the time of described first semiconductor layer 311 and the second semiconductor layer 312 can be formed by extension, control described first semiconductor layer 311 and the second semiconductor layer 312 and be positioned at size above second dielectric layer 400, avoid producing bridging between the first adjacent semiconductor layer 311 and the second semiconductor layer 312, the performance of the device that impact is formed.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.

Claims (20)

1. a formation method for fin formula field effect transistor, is characterized in that, comprising:
Semiconductor substrate is provided, described Semiconductor substrate has NMOS area and PMOS area, and be positioned at the first fin in described PMOS area and the second fin in NMOS area, described Semiconductor substrate also has the first medium layer of surface lower than the top surface of the first fin and the second fin;
The grid structure across described first fin and the second fin is formed on described first medium layer surface;
First medium layer is formed the second dielectric layer of covering first fin and the second fin;
Remove the second dielectric layer at the first fin top of grid structure both sides, expose the top surface of described first fin;
Form the first semiconductor layer in described first fin portion surface, the overhead height of described first semiconductor layer is less than the height of grid structure;
Remove the second dielectric layer at the second fin top of grid structure both sides, expose the top surface of the second fin;
Form the second semiconductor layer in described second fin portion surface, the height of described second semiconductor layer is less than the height of grid structure.
2. the formation method of fin formula field effect transistor according to claim 1, is characterized in that, described first semiconductor layer is identical with the distance of the distance from top semiconductor substrate surface of the second semiconductor layer.
3. the formation method of fin formula field effect transistor according to claim 1, is characterized in that, adopts mobility chemical vapor deposition method to form described second dielectric layer.
4. the formation method of fin formula field effect transistor according to claim 3, it is characterized in that, the method forming described second dielectric layer comprises: on described first medium layer, form mobility layer of dielectric material, and described mobility layer of dielectric material covers the first fin and the second fin; Annealing in process is carried out to described mobility layer of dielectric material, forms second dielectric layer.
5. the formation method of fin formula field effect transistor according to claim 4, it is characterized in that, the material of described mobility layer of dielectric material at least comprises the one in silane, disilane, methyl-monosilane, dimethylsilane, trimethyl silane, tetramethylsilane, tetraethoxysilane, triethoxysilane, octamethylcy-clotetrasiloxane, tetramethyl disiloxane, tetramethyl-ring tetrasiloxane, trimethylsilyl amine, dimethyl silanyl amine.
6. the formation method of fin formula field effect transistor according to claim 5, is characterized in that, described annealing in process is at O 2, O 3, NO, H 2o steam, N 2, carry out under one or more gases in He, Ar, at least there is in described gas a kind of gas containing O.
7. the formation method of fin formula field effect transistor according to claim 6, is characterized in that, the temperature of described annealing in process is 200 DEG C ~ 1200 DEG C.
8. the formation method of fin formula field effect transistor according to claim 7, it is characterized in that, also comprise: after the top surface exposing described first fin, remove described first fin, groove is formed at described semiconductor substrate surface, in described groove, form the first semiconductor layer, and the surface of described first semiconductor layer is higher than the surface of second dielectric layer.
9. the formation method of fin formula field effect transistor according to claim 1, is characterized in that, also comprise: before described second semiconductor layer of formation, adopts oxidation technology or atom layer deposition process to form oxide layer in the first semiconductor layer surface.
10. the formation method of fin formula field effect transistor according to claim 9, is characterized in that, the material of described oxide layer is silica.
The formation method of 11. fin formula field effect transistors according to claim 1, is characterized in that, adopt selective epitaxial process to form described first semiconductor layer, described first semiconductor layer has compression.
The formation method of 12. fin formula field effect transistors according to claim 11, is characterized in that, the material of described first semiconductor layer is SiGe.
The formation method of 13. fin formula field effect transistors according to claim 12, is characterized in that, the shape of described first semiconductor layer is regular octahedron shape.
The formation method of 14. fin formula field effect transistors according to claim 1, is characterized in that, adopt selective epitaxial process to form described second semiconductor layer, described second semiconductor layer has tensile stress.
The formation method of 15. fin formula field effect transistors according to claim 14, is characterized in that, the material of described second semiconductor layer is silicon or carborundum.
The formation method of 16. fin formula field effect transistors according to claim 15, is characterized in that, the shape of described second semiconductor layer is regular octahedron shape.
The formation method of 17. fin formula field effect transistors according to claim 1, is characterized in that, is also included in described grid structure surface and the first fin and the second fin portion surface and forms etching barrier layer.
The formation method of 18. fin formula field effect transistors according to claim 1, it is characterized in that, in the process forming described first semiconductor layer, carry out first in-situ doped to described first semiconductor layer, described first in-situ doped Doped ions is P type ion.
The formation method of 19. fin formula field effect transistors according to claim 1, it is characterized in that, in the process forming described second semiconductor layer, carry out second in-situ doped to described second semiconductor layer, described second in-situ doped Doped ions is N-type ion.
The formation method of 20. fin formula field effect transistors according to claim 1, it is characterized in that, also comprise: carry out light dope ion implantation and heavy doping ion injection in the second fin to described grid structure both sides, the Doped ions that described light dope ion implantation and heavy doping ion are injected is N-type ion.
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Application publication date: 20150624