CN109411539B

CN109411539B - Semiconductor device, method of manufacturing the same, and electronic apparatus including the same

Info

Publication number: CN109411539B
Application number: CN201811264731.1A
Authority: CN
Inventors: 朱慧珑
Original assignee: Institute of Microelectronics of CAS
Current assignee: Institute of Microelectronics of CAS
Priority date: 2018-10-26
Filing date: 2018-10-26
Publication date: 2022-04-19
Anticipated expiration: 2038-10-26
Also published as: CN109411539A

Abstract

The present disclosure provides a semiconductor device, a method of manufacturing the same, and an electronic apparatus including the semiconductor device. According to an embodiment, a semiconductor device includes: a substrate; a semiconductor nanostructure spaced apart from the substrate and extending laterally over the surface of the substrate; a gate stack formed around an outer periphery of the semiconductor nanostructure. The portion of the gate stack below the semiconductor nanostructure includes a first sidewall and a second sidewall opposite each other, and the portion of the gate stack above the semiconductor nanostructure includes a third sidewall and a fourth sidewall opposite each other. At least a portion of the first sidewall is substantially coplanar with at least a portion of the third sidewall, and/or at least a portion of the second sidewall is substantially coplanar with at least a portion of the fourth sidewall.

Description

Semiconductor device, method of manufacturing the same, and electronic apparatus including the same

Technical Field

The present disclosure relates to the field of semiconductors, and in particular, to semiconductor nanostructure-based semiconductor devices, methods of manufacturing the same, and electronic devices including such semiconductor devices.

Background

Semiconductor devices based on semiconductor nanostructures such as nanowires or nanoplates, for example Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), especially devices with all around gate (AAWG), have good short channel effects and enable further scaling of the device dimensions. However, when manufacturing a semiconductor device having an AAWG, it is very difficult to align upper and lower portions of the AAWG. Furthermore, in such devices, it is difficult to apply strong stress to the channel to enhance the performance of the device.

Disclosure of Invention

In view of the above, it is an object of the present disclosure, at least in part, to provide a semiconductor nanostructure-based semiconductor device with improved performance, a method of manufacturing the same, and an electronic device including such a semiconductor device.

According to an aspect of the present disclosure, there is provided a semiconductor device including: a substrate; a semiconductor nanostructure spaced apart from the substrate and extending laterally over the surface of the substrate; and a gate stack formed around an outer periphery of the semiconductor nanostructure. The portion of the gate stack below the semiconductor nanostructure includes a first sidewall and a second sidewall opposite each other, and the portion of the gate stack above the semiconductor nanostructure includes a third sidewall and a fourth sidewall opposite each other. At least a portion of the first sidewall is substantially coplanar with at least a portion of the third sidewall, and/or at least a portion of the second sidewall is substantially coplanar with at least a portion of the fourth sidewall.

According to another aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device, including: forming a preliminary semiconductor nanostructure on a substrate suspended relative to the substrate; forming a preliminary dummy gate layer on a substrate, the preliminary dummy gate layer surrounding an outer periphery of a suspended preliminary semiconductor nanostructure; patterning the prepared pseudo gate layer and the prepared semiconductor nano structure to form a self-aligned pseudo gate layer and a self-aligned semiconductor nano structure, wherein the pseudo gate layer still surrounds the periphery of the semiconductor nano structure; forming a gate side wall surrounding the semiconductor nano structure on the side wall of the pseudo gate layer; at least partially removing the pseudo gate layer to leave a space around the periphery of the semiconductor nano structure on the inner side of the gate side wall; a gate stack is formed in the space.

According to another aspect of the present disclosure, there is provided an electronic device comprising an integrated circuit formed at least in part by the aforementioned semiconductor device.

According to an embodiment of the present disclosure, a self-aligned wrap-around gate (SWAG) is formed. The gate length of the SWAG can be well controlled, which is advantageous for large scale manufacturing.

Drawings

The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments of the present disclosure with reference to the accompanying drawings, in which:

fig. 1 to 16(c) are schematic diagrams showing a middle-stage of a flow of manufacturing a semiconductor device according to an embodiment of the present disclosure.

Throughout the drawings, the same or similar reference numerals denote the same or similar components.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.

Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.

According to an embodiment of the present disclosure, a semiconductor device based on semiconductor nanostructures such as nanowires or nanoplatelets is provided. The semiconductor nanostructure may be a laterally extending structure spaced apart from the substrate. In this way, a four-perimeter all-around gate (AAWG) structure can be formed around the periphery of the semiconductor nanostructure. The gate stack may be formed in a self-aligned manner. More specifically, the portion of the gate stack below the semiconductor nanostructure may include a first sidewall and a second sidewall opposite to each other, and the portion of the gate stack above the semiconductor nanostructure may include a third sidewall and a fourth sidewall opposite to each other. By "self-aligned," it may be meant that at least a portion of the first sidewall is substantially coplanar with at least a portion of the third sidewall, and/or at least a portion of the second sidewall is substantially coplanar with at least a portion of the fourth sidewall. For example, the first and third sidewalls may constitute a continuously extending first plane that surrounds one end of the semiconductor nanostructure, and/or the second and fourth sidewalls may constitute a continuously extending second plane that surrounds the other end of the semiconductor nanostructure. The first plane and the second plane may be substantially parallel to each other and may extend in, for example, a vertical direction (e.g., a direction substantially perpendicular to the surface of the substrate).

The semiconductor nanostructure is surrounded by a gate stack and can thus serve as a channel of the device. Source and drain regions may be formed at both ends of the semiconductor nanostructure, i.e., the channel. Electrical communication between the source region and the drain region may be through the channel. The source and drain regions may be doped semiconductor layers, which may be the same material as the semiconductor nanostructures. The source and drain regions may extend in a fin-like manner, and a longitudinal extension direction thereof may substantially coincide with a longitudinal extension direction of the semiconductor nanostructure.

The end portions of the source and drain regions, each of which is close to the semiconductor nanostructure, i.e., the side of the channel, may assume a tapered shape as approaching the semiconductor nanostructure. A gate sidewall may be formed on the sidewalls of the gate stack. The tapered ends of each of the source and drain regions may be surrounded by gate sidewalls. This structure is advantageous in reducing parasitic resistance.

For the source and drain regions, stress engineering may be applied. For example, a stress layer may be formed on the surface of the source and drain regions.

Such a semiconductor nanostructure device can be manufactured, for example, as follows. In particular, a preliminary semiconductor nanostructure suspended relative to a substrate may be formed on the substrate. For example, the preliminary semiconductor nanostructure may be formed in the form of a suspended beam anchored at both ends. Due to the suspended form, a preliminary dummy gate layer may be formed around the outer circumference of the preliminary semiconductor nanostructure. Due to the presence of the preliminary dummy gate layer, the preliminary semiconductor nanostructure may no longer be in a suspended form, but rather supported by the preliminary dummy gate layer. The anchor portion of the beam may then be removed, leaving the beam (which then acts as a channel) to facilitate the subsequent formation of source and drain regions at both ends thereof. That is, the preliminary semiconductor nanostructure may be patterned, leaving a portion (e.g., the middle portion) thereof to serve as a channel, referred to as a semiconductor nanostructure. Such patterning may also be performed on the preliminary dummy gate layer and in a self-aligned manner, so that the resulting dummy gate layer may be self-aligned to the semiconductor nanostructure. For example, self-aligned patterning can be achieved by using the same mask. Subsequently, a self-aligned gate stack may be formed by replacing the dummy gate layer with a gate stack.

In order to facilitate the definition of the gate stacking position, a gate sidewall may be formed on the sidewall of the dummy gate layer. In order to avoid forming a gate side wall on the side wall of the semiconductor nano structure, epitaxial growth can be performed on the end part of the semiconductor nano structure, so that the end part is relatively extended out. Due to such protruding end portions, gate sidewalls may be formed on sidewalls of the dummy gate layer around the relatively protruded end portions, but not on sidewalls of the end portions. In addition, the portion of the end portion protruding with respect to the gate sidewall may be removed. And then, removing the pseudo gate layer, and forming a gate stack in a space left by the removal of the pseudo gate layer on the inner side of the gate side wall. The dummy gate layer need not be completely removed, but only the periphery of the nanowire is exposed.

The present disclosure may be presented in various forms, some examples of which are described below.

As shown in fig. 1, a substrate 1001 is provided. The substrate 1001 may be a substrate of various forms including, but not limited to, a bulk semiconductor material substrate such as a bulk Si substrate, a semiconductor-on-insulator (SOI) substrate, a compound semiconductor substrate such as a SiGe substrate, and the like. In the following description, a bulk Si substrate is described as an example for convenience of explanation. Here, a silicon wafer is provided as the substrate 1001.

In substrate 1001, well region 1001-w may be formed, for example, by ion implantation. The conductivity type of well region 1001-w may be selected according to the type of device to be formed. For example, if the device to be formed is a p-type device (e.g., pMOSFET), then n-type well regions 1001-w may be formed. The n-type well region 1001-w may be formed by implanting an n-type impurity such As phosphorus (P) or arsenic (As) into the substrate 1001 and activating the implanted impurity by annealing. On the other hand, if the device to be formed is an n-type device (e.g., nMOSFET), p-type well region 1001-w may be formed. The p-type well region 1001-w may be formed by implanting a p-type impurity such as boron (B) into the substrate 1001 and activating the implanted impurity by annealing.

On the substrate 1001, a sacrificial layer 1003 and a preliminary semiconductor nanostructure layer 1005 may be sequentially formed by, for example, epitaxial growth.

The sacrificial layer 1003 may have a desired etch selectivity, e.g., relative to the underlying substrate 1001 and overlying preliminary semiconductor nanostructure layer 1005, so that it may be selectively etched. In addition, the sacrificial layer 1003 may include a semiconductor material in consideration of the growth quality of the preliminary semiconductor nanostructure layer 1005. The sacrificial layer 1003 may have the same or substantially the same crystal structure as the underlying substrate 1001 and the overlying preliminary semiconductor nanostructure layer 1005. For example, the sacrificial layer 1003 may include SiGe, and the atomic percent of Ge may be about 10-30%. The thickness of the sacrificial layer 1003 may be determined according to the size of a surrounding gate to be formed later, for example, about 30-60 nm.

The preliminary semiconductor nanostructure layer 1005 may comprise a semiconductor material, such as Si, and the channel of the device may be subsequently formed. The size of the preliminary semiconductor nanostructure layer 1005, in particular its thickness (dimension in the vertical direction in the figure), may be determined according to the channel size of the device. For example, the thickness of the preliminary semiconductor nanostructure layer 1005 is about 5-15 nm.

A desired channel form, such as a nanowire or nanoplatelet, may be defined in the preliminary semiconductor nanostructure layer 1005. This may be achieved by patterning the preliminary semiconductor nanostructure layer 1005. This may be done, for example, as follows.

As shown in fig. 2, a mask layer 1007 such as photoresist may be formed on the preliminary semiconductor nanostructure layer 1005. The photoresist 1007 may be patterned by photolithography to define a desired channel form. In this example, the middle portion of the photoresist 1007 is line-shaped to subsequently define a nanowire in the preliminary semiconductor nanostructure layer 1005. However, the present disclosure is not limited thereto. For example, the photoresist may define a rectangle or square shape to define nanoplatelets in the preliminary semiconductor nanostructure layer 1005. In addition, both ends of the photoresist 1007 are covered with the preliminary semiconductor nanostructure layer 1005 so as to define a support portion to support the nanowire to be separated from the substrate 1001 in a subsequent process.

The pattern of photoresist 1007 may then be transferred into the preliminary semiconductor nanostructure layer 1005. As shown in fig. 3(a), 3(B), 3(c) and 3(d) (fig. 3(a) is a top view, fig. 3(B) is a sectional view taken along line AA ' in fig. 3(a), fig. 3(c) is a sectional view taken along line B1B1 ' in fig. 3(a), and fig. 3(d) is a sectional view taken along line B2B2 ' in fig. 3 (a)), the preliminary semiconductor nanostructure layer 1005 may be selectively etched, such as by Reactive Ion Etching (RIE), using the photoresist 1007 as an etching mask. The RIE may be performed in a vertical direction (e.g., a direction substantially perpendicular to the substrate surface). Thus, the preliminary semiconductor nanostructure layer 1005 may exhibit substantially the same pattern as the photoresist 1007. In addition, the sacrificial layer 1003 may be selectively etched such as RIE. Also, during the etching process, undercuts may be caused to occur in the sacrificial layer 1003 below the preliminary semiconductor nanostructure layer 1005, so that the preliminary semiconductor nanostructure layer 1005 may be separated from the substrate 1001. Thus, a preliminary nanowire (the middle of the preliminary semiconductor nanostructure layer 1005) suspended with respect to the substrate 1001 is formed, which is supported on the substrate 1001 at both ends by the sacrificial layer 1003. After that, the photoresist 1007 may be removed.

The suspension structure is formed above by the sacrificial layer. Since the sacrificial layer can be formed by epitaxial growth, its dimensional control is good. However, the present disclosure is not limited thereto. There are a number of ways in the art to form the suspension structure. For example, a surface portion of the substrate 1001 may be denatured to have etch selectivity with respect to its lower portion, and the denatured portion of the surface may function similarly to the above-described coefficient layer 1003.

To form a gate stack with self-aligned features, the location of the gate stack may be defined. The dummy gate structure may be used to occupy the position of the gate stack and be replaced with the gate stack after a series of processes. This may be done, for example, as follows.

As shown in fig. 4, a dummy gate layer 1011 surrounding the suspended preliminary nanowires described above may be formed, for example by deposition, on the structures shown in fig. 3(a), 3(b), 3(c) and 3 (d). The dummy gate layer 1011 may comprise a material, such as an oxide (e.g., silicon oxide), that provides the desired etch selectivity. In this example, the dummy gate layer 1011 fills the space in the sacrificial layer 1003 under the preliminary nanowire and also covers substantially all of the top surface of the preliminary semiconductor nanostructure layer 1005. The dummy gate layer 1011 may be subjected to a planarization process such as Chemical Mechanical Polishing (CMP).

In addition, in order to protect the preliminary nanowire, a protective layer 1009 may be formed around the outer circumference of the preliminary nanowire before the dummy gate layer 1011 is formed. The protective layer 1009 may include a material that provides a desired etch selectivity, such as HfO₂. The protection layer 1009 may be a thin film, for example, formed substantially conformally.

Here, the term "desired etching selectivity" is used to mean a value that can be understood by those skilled in the art from the context. For example, when describing "selectively etching a layer," the layer may have an etch selectivity relative to other layers exposed to an etch recipe used to etch the layer.

The dummy gate layer 1011 may be patterned into a dummy gate structure. For example, the dummy gate structure may intersect the nanowire that will ultimately serve as a channel (e.g., with respective longitudinal extension directions substantially perpendicular to each other) so as to define a channel region in the nanowire.

For example, as shown in fig. 5, a mask layer 1013 such as a photoresist may be formed on the dummy gate layer 1011. The photoresist 1013 may be patterned by photolithography to define a desired gate pattern, for example, a bar shape having a longitudinal direction extending in a direction (vertical direction in fig. 5) intersecting (e.g., substantially perpendicular) to a longitudinal extending direction (horizontal direction in fig. 5) of the preliminary nanowire.

Then, the pattern of the photoresist 1013 may be transferred into the dummy gate layer 1011 to form a dummy gate structure. As shown in fig. 6(a) and 6(b) (fig. 6(a) is a top view, fig. 6(b) is a cross-sectional view, and the cut position is the previously shown AA' line), the dummy gate layer 1011 may be selectively etched, such as RIE, using the photoresist 1013 as an etching mask. The RIE may be performed in a vertical direction (e.g., a direction substantially perpendicular to the substrate surface). Thus, the dummy gate layer 1011 assumes substantially the same rod shape as the photoresist 1013 in a top view and surrounds the preliminary nanowire.

In addition, the protective layer 1009, the preliminary semiconductor nanostructure layer 1005, and the sacrificial layer 1003 may be selectively etched, such as RIE, in this order. RIE may also be performed in a vertical direction (e.g., a direction substantially perpendicular to the substrate surface). Thus, the portion of the preliminary semiconductor nanostructure layer 1005 left behind forms a nanowire (still labeled "1005") surrounded by the dummy gate layer 1011 and supported on the substrate 1001 by the dummy gate layer 1011. In addition, the sacrificial layer 1003 has been completely removed. After that, the photoresist 1013 may be removed.

Since the etching is performed using the same mask layer 1013 as an etching mask, a portion of the dummy gate layer 1011 above the nanowire 1005 and a portion below the nanowire 1005 can be self-aligned. That is, at least some of the sidewalls of the upper and lower portions may be substantially aligned or coplanar in the vertical direction. Furthermore, the dummy gate layer 1011 may be self-aligned to the nanowire 1005 (which will subsequently form a channel). Thus, a self-aligned wrapped around gate (SWAG) structure can be obtained. Since such a SWAG structure is obtained by photolithography, the size thereof (particularly, the size in the horizontal direction in the drawing) can be well controlled, and thus the gate length of the device can be well controlled, which is advantageous for mass production.

By the above process, a self-aligned channel and (dummy) gate structure is obtained. Next, source/drain regions may be formed at both ends of the channel, i.e., the nanowire 1005. For example, source/drain regions may be formed by forming doped semiconductor material across the nanowire 1005. To facilitate the formation of the source/drain regions and the subsequent replacement of the dummy gate structure, spacers may be formed on sidewalls of the dummy gate layer 1011. In order to form sidewalls on the sidewalls of the dummy gate layer 1011 and not on the sidewalls of the nanowire 1005, lateral extensions may be provided at both ends of the nanowire 1005. Because the sidewalls may be formed on the vertical sidewalls, but not on the lateral surfaces, according to the sidewall formation process. Due to the laterally extending portions at the two ends of the nanowire 1005, the sidewall may not be formed on the sidewall of the nanowire 1005.

For example, as shown in fig. 7, an epitaxial layer 1015 may be grown from the sidewalls of the nanowire 1005 by selective epitaxial growth. The growth may be seeded with the exposed surfaces of the nanowire 1005 (here, Si) and the substrate 1001 (here, also Si). The epitaxial layer 1015 may comprise the same semiconductor material as the nanowires 1005, e.g., Si. Of course, the present disclosure is not limited thereto. For example, epitaxial layer 1015 may include a different semiconductor material than nanowire 1005, e.g., a different semiconductor material with a different lattice constant in order to apply stress into nanowire 1005. The epitaxial layer 1015 may be grown to a thickness, for example, of about 10-30 nm. The epitaxial layer 1015 grown at both ends of the nanowire 1005 may assume a spindle shape due to its surface orientation. Specifically, the epitaxial layer 1015 is in a shape that first expands and then tapers toward the outside.

Epitaxial layer 1015 may then be used to form extension regions (extensions). To this end, the epitaxial layer 1015 may be doped with a certain conductivity type. For example, for an n-type device, n-type doping may be performed with an n-type impurity such As P or As, while for a P-type device, P-type doping may be performed with a P-type impurity such As B. In-situ doping may be performed while growing epitaxial layer 1015.

Next, a sidewall formation process may be performed.

For example, as shown in fig. 8, a layer 1017 of sidewall material is formed in a substantially conformal manner on the structure shown in fig. 7, for example, by deposition. For example, the layer of spacer material 1017 may comprise a material having a desired etch selectivity, such as a nitride (e.g., silicon nitride), having a thickness of about 5-20 nm. The sidewall material layer 1017 may be subjected to a selective etch such as RIE. The RIE may be performed in a vertical direction (e.g., a direction substantially perpendicular to the substrate surface) to remove laterally extending portions of the sidewall material layer 1017, while leaving vertically extending portions thereof. The sidewall material layer 1017 on the upper surface of the epitaxial layer 1015 at the two ends of the nanowire 1005 may be removed, and the sidewall material layer 1017 on the vertical sidewall may even be completely removed due to the low height, but the sidewall material layer 1017 on the lower surface may remain. The epitaxial layer 1015 may be selectively etched, such as RIE, which may be performed in a vertical direction (e.g., a direction substantially perpendicular to the substrate surface). The portion of the epitaxial layer 1015 close to the end surface of the nanowire 1015 can be retained because it is shielded by the upper side wall material layer 1017, and the portion of the epitaxial layer 1015 far from the end surface of the nanowire 1015 can be removed because it is exposed, and thus the side wall material layer 1017 below is exposed. Then, RIE in the vertical direction is further performed on the sidewall material layer 1017. In this way, a sidewall is obtained as shown in fig. 9, again here indicated with 1017. A portion of epitaxial layer 1015 may still remain on the surface of substrate 1001.

According to the above process, the sidewall 1017 is self-aligned to the dummy gate structure, and surrounds the epitaxial layer 1015 at the end of the nanowire 1005. That is, the self-aligned surrounding sidewall 1017 is formed. In addition, the portion of the sidewall 1017 above the nanowire epitaxial layer 1015 and the portion below the epitaxial layer 1015 may also be self-aligned with each other. The epitaxial layer 1015 may have a shape expanding toward the outside and is surrounded by the sidewall 1017, which helps to reduce parasitic resistance.

Thereafter, source/drain regions may be further formed outside the epitaxial layer 1015 (serving as an extension region). It is noted here that the extension regions may also be considered as part of the source/drain regions.

For example, as shown in fig. 10(a) and 10(b) (fig. 10(a) is a top view, fig. 10(b) is a cross-sectional view, taken along the previously shown AA' line), an epitaxial layer 1019 may be grown from the sidewalls of epitaxial layer 1015 by selective epitaxial growth. The growth may be seeded with an epitaxial layer 1015 (here Si) at both ends of the nanowire 1005 and the substrate 1001 (here also Si) or with an exposed surface of the epitaxial layer 1015 left on the substrate 1001. The epitaxial layer 1019 can comprise the same semiconductor material as the nanowires 1005, e.g., Si. Of course, the present disclosure is not limited thereto. For example, epitaxial layer 1019 may comprise a different semiconductor material than nanowire 1005, e.g., a different semiconductor material with a different lattice constant in order to impart stress into nanowire 1005.

Epitaxial layer 1019 may be doped to form source/drain regions. For example, for an n-type device, n-type doping may be performed with an n-type impurity such As P or As, while for a P-type device, P-type doping may be performed with a P-type impurity such As B. In-situ doping may be performed while the epitaxial layer 1019 is grown.

Here, more growth is performed, and a larger epitaxial layer 1019 is obtained for subsequent processing. In this example, the epitaxial layer 1019 grown from the epitaxial layers 1015 at both ends of the nanowire 1005 and the epitaxial layer 1019 grown from the surface of the substrate 1001 may be fused to each other. In addition, the top surface of the epitaxial layer 1019 may be lower than the top surface of the sidewall 1017 for subsequent processing.

By now, the fabrication of the device has been substantially completed. Here, stressor/drain techniques may also be applied.

The epitaxial layer 1019 may be patterned into fins for better stress application. For example, as shown in fig. 11, a mask layer 1031 such as a photoresist may be formed on the structure shown in fig. 10(a) and 10 (b). The photoresist 1031 may be patterned into a fin shape by photolithography. In this example, a longitudinal extension direction of the fin-shaped photoresist 1031 may substantially coincide with a longitudinal extension direction (horizontal direction in the drawing) of the nanowire 1005. In addition, in a top view, the photoresist 1031 overlaps the nanowire 1005 and the epitaxial layers 1015 at both ends of the nanowire. In this way, the source/drain regions subsequently defined by the photoresist 1031 may interface with the epitaxial layers 1015 at the ends of the nanowires 1005. Then, as shown in fig. 12(a), 12(B) and 12(c) (fig. 12(a) is a top view, fig. 12(B) and 12(c) are cross-sectional views, taken at the previously shown AA 'line and B2B 2' line, respectively), selective etching such as Reactive Ion Etching (RIE) may be performed on the epitaxial layer 1019 with the photoresist 1031 as an etching mask. The RIE may be performed in a vertical direction (e.g., a direction substantially perpendicular to the substrate surface). Thus, the epitaxial layer 1019 may exhibit substantially the same pattern as the photoresist 1031, here a fin. In addition, when etching the epitaxial layer 1019, the etching may not proceed to the bottom surface of the epitaxial layer 1019, so that a certain thickness of the epitaxial layer 1019 remains on the surface of the substrate 1001, as shown in fig. 12 (c). After that, the photoresist 1031 may be removed.

A stress layer may be formed on the epitaxial layer 1019 to apply stress to the nanowire 1005. For example, as shown in fig. 13(a), 13(B) and 13(c) (fig. 13(a) is a top view, fig. 13(B) and 13(c) are cross-sectional views, taken at the respective previously shown AA 'line and B2B 2' line), a stress layer 1021 may be formed on the epitaxial layer 1019 by epitaxial growth. For example, the stress layer 1021 may comprise a semiconductor material having a different lattice constant than the epitaxial layer 1019. For a p-type device, stress layer 1021 may apply a compressive stress. For example, where epitaxial layer 1019 is Si, stress layer 1021 may comprise SiGe, and the atomic percent of Ge may be about 10-70%. On the other hand, stress layer 1021 may apply tensile stress for an n-type device. For example, where epitaxial layer 1019 is Si, stress layer 1021 may comprise Si: the atomic percent of C, C is about 0.3-2%.

Fig. 13(d) (a cross-sectional view along line B2B 2') shows another example of a grown stress layer 1021.

It can be seen that since the epitaxial layer 1019 is formed in a fin shape, the stress layer can be formed around the top surface and sidewalls thereof, so that stress can be applied more effectively. For subsequent processing, the top surface of the stress layer 1021 may be lower than the top surface of the sidewall spacer 1017.

Next, the dummy gate structure may be replaced with a gate stack.

For example, as shown in fig. 14(a) and 14(b) (fig. 14(a) is a top view, fig. 14(b) is a cross-sectional view, and the cut position is the previously shown AA' line), a dielectric layer 1023 may be formed on the structure shown in fig. 13(a), 13(b), and 13(c) (or 13(d)), for example, by deposition. The dielectric layer 1023 may cover the epitaxial layer 1021 to protect the epitaxial layer 1021 in subsequent processes. In addition, the dielectric layer 1023 may occupy a space outside the sidewall 1017 to prevent the gate stack from being formed outside the sidewall 1017. For example, dielectric layer 1023 may comprise nitride (here sidewall spacer 1017 is shown as one piece with dielectric layer 1023 since sidewall spacer 1017 comprises the same material). The deposited dielectric layer 1023 may extend above the top surfaces of the sidewall spacers 1017 and the deposited dielectric layer 1023 may be subjected to a planarization process such as CMP, which may stop at the sidewall spacers 1017, thereby exposing the dummy gate layer 1011.

Thereafter, the dummy gate layer 1011 may be removed, and a gate stack may be formed in a space left inside the sidewall due to the removal of the dummy gate layer 1011. As shown in fig. 15(a) and 15(b) (fig. 15(a) is a top view, fig. 15(b) is a cross-sectional view, and the cut position is the previously shown AA' line), the dummy gate layer 1011 may be removed by selective etching such as RIE. Here, for the purpose of electrical isolation between the gate stack and the substrate 1001, a dummy gate layer 1011 (here, an oxide) may be left at the bottom (the side close to the substrate 1001) to a certain thickness. The dummy gate layer 1011 under the nanowire 1005 can be formed by isotropyAnd etching to remove. Similarly, the protective layer 1009 can be removed by selective etching such as RIE. Thus, the nanowire 1005 is exposed. Then, as shown in fig. 16(a), 16(B) and 16(c) (fig. 16(a) is a top view, fig. 16(B) and 16(c) are cross-sectional views taken at the previously shown AA 'line and B2B 2' line, respectively), a gate dielectric layer 1025 and a gate conductor layer 1027 may be sequentially deposited. For example, gate dielectric layer 1025 may comprise a high-K gate dielectric such as HfO₂(ii) a The gate conductor layer 1027 may include a metal gate conductor. Preferably, gate dielectric layer 1025 may have a thickness of 2-5 nm. An interfacial layer (not shown), such as an oxide, may also be formed prior to forming gate dielectric layer 1025, and may be between 0.3nm and 1nm thick. Additionally, a work function adjusting layer (not shown) may also be present between the gate dielectric layer 1025 and the gate conductor layer 1027. Gate dielectric layer 1025 may be formed in a substantially conformal manner, and gate conductor layer 1027 may fill the space inside the sidewall spacers. Thereafter, a planarization process, such as CMP, may be performed on the gate conductor layer 1027 and the gate dielectric layer 1025, and the CMP may stop at the dielectric layer 1023, so as to remove the gate conductor layer 1027 and the gate dielectric layer 1025 outside the sidewall spacers.

As shown in fig. 16(a), 16(b), and 16(c), the semiconductor device according to the present embodiment may include a semiconductor nanostructure 1005 (in this example, a nanowire) and a gate stack formed around the periphery of the semiconductor nanostructure 1005. As described above, since the dummy gate layer is formed in a self-aligned manner, the gate stack occupying the position of the dummy gate layer is also self-aligned, thereby forming SWAG.

Although a single nanowire device is described in the above embodiments, the present disclosure is not limited thereto. For example, by alternately stacking sacrificial layers 1003 and semiconductor nanostructure layers 1005 on a substrate. After removing the sacrificial layer 1003, a plurality of semiconductor nanostructure layers 1005 separated from each other at the middle may be formed and thus a plurality of semiconductor nanostructures such as nanowires or nanosheets spaced apart from each other may be obtained. A dummy gate layer may be formed in the same manner, and the dummy gate layer may surround the plurality of semiconductor nanostructures. Subsequently, the dummy gate layer may be replaced with a gate stack as well.

The semiconductor device according to the embodiment of the present disclosure can be applied to various electronic devices. For example, by integrating a plurality of such semiconductor devices and other devices (e.g., other forms of transistors, etc.), an Integrated Circuit (IC) can be formed, and an electronic apparatus can be constructed therefrom. Accordingly, the present disclosure also provides an electronic device including the above semiconductor device. The electronic device may also include components such as a display screen that cooperates with the integrated circuit and a wireless transceiver that cooperates with the integrated circuit. Such electronic devices are for example smart phones, computers, tablets (PCs), artificial intelligence, wearable devices, mobile power supplies etc.

In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.

The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims

1. A semiconductor device, comprising:

a substrate;

a semiconductor nanostructure spaced apart from the substrate and extending laterally over the surface of the substrate;

a gate stack formed around a periphery of the semiconductor nanostructure, wherein a portion of the gate stack below the semiconductor nanostructure includes a first sidewall and a second sidewall opposite each other, and a portion of the gate stack above the semiconductor nanostructure includes a third sidewall and a fourth sidewall opposite each other, wherein at least a portion of the first sidewall is substantially coplanar with at least a portion of the third sidewall, and/or at least a portion of the second sidewall is substantially coplanar with at least a portion of the fourth sidewall;

the semiconductor source region and the semiconductor drain region are respectively positioned at two opposite sides of the semiconductor nano structure, wherein the end part of each semiconductor source region and the end part of each semiconductor drain region close to one side of the nano structure are in a tapered shape along with the approach of the semiconductor nano structure; and

and the grid side wall is formed on the side wall of the grid stack and is a dielectric medium, wherein the grid side wall is separated from the semiconductor source region and the semiconductor drain region through the grid side wall, and the parts of the grid side wall, which are respectively connected with the end parts of the semiconductor source region and the semiconductor drain region, are in an inclined shape, so that the end parts are in a tapered shape.

2. The semiconductor device of claim 1, wherein the first sidewall and the third sidewall of the gate stack constitute a continuously extending first plane surrounding the semiconductor nanostructure and/or the second sidewall and the fourth sidewall of the gate stack constitute a continuously extending second plane surrounding the semiconductor nanostructure.

3. The semiconductor device of claim 2, wherein the first plane and the second plane are substantially parallel to each other.

4. The semiconductor device of claim 2, wherein the first plane and the second plane are both substantially perpendicular to the substrate surface.

5. The semiconductor device of claim 1, wherein the semiconductor source region and the semiconductor drain region are each formed as a fin shape interfacing with the semiconductor nanostructure.

6. The semiconductor device of claim 5, wherein the fin extends along substantially the same longitudinal direction as the semiconductor nanostructure.

7. The semiconductor device of claim 5, wherein the semiconductor source region and the semiconductor drain region are contiguous with the substrate.

8. The semiconductor device of claim 5, wherein the semiconductor source region, the semiconductor drain region, and the semiconductor nanostructure are formed of the same semiconductor material.

9. The semiconductor device of claim 5, further comprising:

and a stress layer formed on the surface of the semiconductor source region and the semiconductor drain region.

10. The semiconductor device of claim 1, further comprising:

an isolation layer between the gate stack and the substrate, wherein the isolation layer is self-aligned to the gate stack.

11. The semiconductor device of claim 1, wherein the semiconductor nanostructure comprises one or more nanowires or one or more nanoplatelets.

12. A method of manufacturing a semiconductor device, comprising:

forming a preliminary semiconductor nanostructure on a substrate suspended relative to the substrate;

forming a preliminary dummy gate layer on a substrate, the preliminary dummy gate layer surrounding an outer periphery of a suspended preliminary semiconductor nanostructure;

patterning the prepared pseudo gate layer and the prepared semiconductor nano structure to form a self-aligned pseudo gate layer and a self-aligned semiconductor nano structure, wherein the pseudo gate layer still surrounds the periphery of the semiconductor nano structure;

carrying out epitaxial growth on the end part of the semiconductor nano structure to form an epitaxial layer which extends out relatively;

forming a gate side wall surrounding the semiconductor nano structure on the side wall of the pseudo gate layer around the epitaxial layer which relatively extends out, wherein the part of the gate side wall connected with the epitaxial layer is in an inclined shape;

removing the part of the epitaxial layer extending out relative to the gate side wall, so that the rest epitaxial layer is surrounded by the gate side wall and is in a shape gradually reduced along with approaching the semiconductor nano structure;

forming a fin-shaped semiconductor source region and a fin-shaped semiconductor drain region on the substrate, wherein the semiconductor source region and the semiconductor drain region are connected with the epitaxial layer and are separated from the pseudo gate layer through the gate side wall;

at least partially removing the pseudo gate layer to leave a space around the periphery of the semiconductor nano structure on the inner side of the gate side wall; and

a gate stack is formed in the space.

13. The method of claim 12, wherein patterning the preliminary dummy gate layer and the preliminary semiconductor nanostructure comprises:

the preliminary dummy gate layer and the preliminary semiconductor nanostructure are patterned using the same mask.

14. The method of claim 13, wherein patterning the preliminary dummy gate layer and the preliminary semiconductor nanostructure comprises:

the anisotropic etching is performed in a direction substantially perpendicular to the substrate surface.

15. The method of claim 12, wherein at least partially removing the dummy gate layer comprises:

removing the upper portion of the dummy gate layer, leaving the lower portion of the dummy gate layer below the semiconductor nanostructure, wherein the top surface of the portion of the dummy gate layer left is lower than the bottom surface of the semiconductor nanostructure.

16. The method of claim 12, further comprising:

and forming stress layers on the surfaces of the semiconductor source region and the semiconductor drain region.

17. The method of claim 12, wherein the semiconductor nanostructure comprises a nanowire or nanoplatelet.

18. An electronic device comprising an integrated circuit formed at least in part by the semiconductor device as claimed in any one of claims 1 to 11.

19. The electronic device of claim 18, further comprising: a display cooperating with the integrated circuit and a wireless transceiver cooperating with the integrated circuit.

20. The electronic device of claim 18, comprising a smartphone, a computer, a tablet, an artificial intelligence, a wearable device, or a mobile power source.