CN105374683A - Semiconductor device and manufacturing method thereof, and electronic device - Google Patents
Semiconductor device and manufacturing method thereof, and electronic device Download PDFInfo
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- CN105374683A CN105374683A CN201410438323.9A CN201410438323A CN105374683A CN 105374683 A CN105374683 A CN 105374683A CN 201410438323 A CN201410438323 A CN 201410438323A CN 105374683 A CN105374683 A CN 105374683A
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Abstract
The invention provides a semiconductor device and a manufacturing method thereof, and an electronic device. The method includes: a semiconductor substrate is provided, a pseudo grid electrode structure is formed on the semiconductor substrate, and sidewall structures are formed at two sides of the pseudo grid electrode structure; after an interlayer dielectric layer is deposited on the semiconductor substrate, the pseudo grid electrode structure is removed, and the semiconductor substrate is exposed; the exposed semiconductor substrate is etched in order to form a groove; a stress material layer with high stress is formed so that the groove is partly filled; and an epitaxial layer as a channel is formed at the top of the stress material layer. According to the semiconductor device and the manufacturing method thereof, and the electronic device, the stress acting on a device channel region can be further increased, and the threshold voltage of the channel region is improved.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of semiconductor device and manufacture method, electronic installation.
Background technology
Along with the continuous reduction of the characteristic size of MOS device, in its manufacture process, the control for the enough effective channel length of MOS device becomes more challenging.For this reason, adopt the method forming for ultra-shallow junctions and abrupt junction in MOS device, the short-channel effect of core devices can be improved.But, in the process forming for ultra-shallow junctions and abrupt junction, how to suppress to find more rational equilibrium point to be also extremely bear challenging task between short-channel effect and the performance promoting MOS device.
In order to overcome an above-mentioned difficult problem, prior art is by multiple method, and such as pre-amorphous ion implantation, stress technique etc., promote the performance of MOS device further.But, these methods come with some shortcomings part, such as pre-amorphous ion implantation can not control the doping form of the source/drain region of MOS device well, and stress technique is just by providing extra stress to promote its carrier mobility in the channel region of MOS device.Above-mentioned weak point further limit in the technological progress space suppressing to determine between short-channel effect and the performance promoting MOS device more excellent equilibrium point.
Therefore, need to propose a kind of method, to solve the problem.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of manufacture method of semiconductor device, comprising: Semiconductor substrate is provided, be formed with dummy gate structure on the semiconductor substrate, be formed with side wall construction in the both sides of described dummy gate structure; On the semiconductor substrate after interlevel dielectric deposition, remove described dummy gate structure, to expose described Semiconductor substrate; The Semiconductor substrate exposed described in etching, to form groove; Formation has heavily stressed stress material layer, to be partially filled described groove; The epitaxial loayer as raceway groove is formed at the top of described stress material layer.
In one example, the degree of depth of described groove is 30nm-330nm.
In one example, wet etching or dry etching is etched to the described Semiconductor substrate exposed.
In one example, described formation has heavily stressed stress material layer, to be partially filled described groove, is specially: have heavily stressed stress material layer described in being formed by depositing operation, fill described groove while covering described interlayer dielectric layer; Implement cmp to grind described stress material layer, until expose the top of described interlayer dielectric layer; Etch described stress material layer, until the top of described stress material layer is lower than the upper surface of described Semiconductor substrate.
In one example, for the nmos area in described Semiconductor substrate, described stress material layer is germanium silicon layer; For the PMOS district in described Semiconductor substrate, described stress material layer is carbon silicon layer.
In one example, described stress material layer has the stress of 1.7GPa-3.5GPa.
In one example, for the nmos area in described Semiconductor substrate, described epitaxial loayer is carbon silicon layer or silicon layer; For the PMOS district in described Semiconductor substrate, described epitaxial loayer is germanium silicon layer or silicon layer.
In one example, implement extension form described epitaxial loayer while or afterwards, also comprise perform Doped ions inject and the step of annealing, to regulate the threshold voltage of described epitaxial loayer.
In one embodiment, the present invention also provides a kind of semiconductor device adopting said method to manufacture.
In one embodiment, the present invention also provides a kind of electronic installation, and described electronic installation comprises described semiconductor device.
According to the present invention, humidification in the stress of device channel region, the threshold voltage of channel region can be improved further.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
Figure 1A-Fig. 1 F for according to an exemplary embodiment of the present one the schematic cross sectional view of device that obtains respectively of the step implemented successively of method;
Fig. 2 is the flow chart of step implemented successively of method of according to an exemplary embodiment of the present.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, by following description, detailed step is proposed, to explain semiconductor device and manufacture method, the electronic installation of the present invention's proposition.Obviously, the specific details that the technical staff that execution of the present invention is not limited to semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Should be understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not get rid of existence or additional other features one or more, entirety, step, operation, element, assembly and/or their combination.
[exemplary embodiment one]
With reference to Figure 1A-Fig. 1 F, the schematic cross sectional view of the device that the step that the method that illustrated therein is according to an exemplary embodiment of the present is implemented successively obtains respectively.
First, as shown in Figure 1A, there is provided Semiconductor substrate 100, the constituent material of Semiconductor substrate 100 can to adopt on unadulterated monocrystalline silicon, monocrystalline silicon doped with impurity, silicon-on-insulator (SOI), insulator stacked SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc. on stacked silicon (SSOI), insulator.Exemplarily, in the present embodiment, the constituent material of Semiconductor substrate 100 selects monocrystalline silicon.In Semiconductor substrate 100, be formed with isolation structure 101, exemplarily, isolation structure 101 is that shallow trench isolation is from (STI) structure or selective oxidation silicon (LOCOS) isolation structure.Also be formed with various trap (well) structure in Semiconductor substrate 100, in order to simplify, be omitted in diagram.
Be formed with dummy gate structure 102 on a semiconductor substrate 100, exemplarily, dummy gate structure 102 comprises the gate dielectric 102a and gate material layers 102b that stack gradually.Gate dielectric 102a comprises oxide skin(coating), such as silicon dioxide (SiO2) layer.Gate material layers 102b comprises polysilicon layer, amorphous carbon layer etc.Any prior art that the formation method of dummy gate structure 102 can adopt those skilled in the art to have the knack of, preferred chemical vapour deposition technique (CVD), as low temperature chemical vapor deposition (LTCVD), low-pressure chemical vapor deposition (LPCVD), fast thermal chemical vapor deposition (RTCVD), plasma enhanced chemical vapor deposition (PECVD).
In addition, exemplarily, be also formed on a semiconductor substrate 100 and be positioned at dummy gate structure 102 both sides and near the side wall construction 103 of dummy gate structure 102.Wherein, side wall construction 103 is made up of oxide, nitride or the combination of the two.
Next, perform low-doped ion implantation, to form low-doped source/drain region 104 in Semiconductor substrate 100.
For the nmos area in Semiconductor substrate 100, the Doped ions of described low-doped ion implantation can be phosphonium ion or arsenic ion etc.Exemplarily, when the Doped ions of described low-doped ion implantation is phosphonium ion, the energy range of ion implantation is 1-20keV, and the dosage of ion implantation is 1.0 × e
14-1.0 × e
15cm
-2; When the Doped ions of described low-doped ion implantation is arsenic ion, the energy range of ion implantation is 2-35keV, and the dosage of ion implantation is 1.0 × e
14-1.0 × e
15cm
-2.
For the PMOS district in Semiconductor substrate 100, the Doped ions of described low-doped ion implantation can be boron ion or indium ion etc.Exemplarily, when the Doped ions of described low-doped ion implantation is boron ion, the energy range of ion implantation is 0.5-10keV, and the dosage of ion implantation is 1.0 × e
14-1.0 × e
15cm
-2; When the Doped ions of described low-doped ion implantation is indium ion, the energy range of ion implantation is 10-70keV, and the dosage of ion implantation is 1.0 × e
14-1.0 × e
15cm
-2.
Before the low-doped ion implantation of enforcement or simultaneously, alternatively, pre-amorphous injection (PAI) is implemented, to reduce short-channel effect.The injection ion of pre-amorphous injection comprises III race and V race's ion such as germanium, carbon.
Next, perform bag-like region ion implantation, to form bag-like region in Semiconductor substrate 100, in order to simplify, be omitted in diagram.
For the nmos area in Semiconductor substrate 100, the degree of depth of described bag-like region ion implantation is slightly larger than the degree of depth of described low-doped ion implantation, and the ion of described bag-like region ion implantation is contrary with the ionic conduction type of described low-doped ion implantation, therefore, the Doped ions of described bag-like region ion implantation can be boron ion or indium ion etc.
When the Doped ions of described bag-like region ion implantation is boron ion, the energy range of ion implantation is 3-20keV, and the dosage of ion implantation is 1.0 × e
13-9.0 × e
13cm
-2, the incident direction of ion implantation offsets certain angle relative to the direction perpendicular with Semiconductor substrate 100, and the scope of described angle is 0-45 degree.
When the Doped ions of described bag-like region ion implantation is indium ion, the energy range of ion implantation is 100-150keV, and the dosage of ion implantation is 1.0 × e
13-9.0 × e
13cm
-2, the incident direction of ion implantation offsets certain angle relative to the direction perpendicular with Semiconductor substrate 100, and the scope of described angle is 0-45 degree.
Under selected ion implantation angle, carry out rotation to inject, can shadow effect be reduced and form symmetrical Impurity Distribution, energy, dosage, the corresponding coupling of angle of its ion implantation energy, dosage, angle and described low-doped ion implantation, its Implantation Energy guarantees that low-doped source/drain region 104 wraps by the bag-like region formed, thus effectively restrains and cause potential barrier by leakage and reduce (DIBL) short-channel effect of causing.
For the PMOS district in Semiconductor substrate 100, the Doped ions of described bag-like region ion implantation can be phosphonium ion or arsenic ion etc.
When the Doped ions of described bag-like region ion implantation is phosphonium ion, the energy range of ion implantation is 5-35keV, and the dosage of ion implantation is 1.0 × e
13-1.0 × e
14cm
-2, the incident direction of ion implantation offsets certain angle relative to the direction perpendicular with Semiconductor substrate 100, and the scope of described angle is 0-45 degree.
When the Doped ions of described bag-like region ion implantation is arsenic ion, the energy range of ion implantation is 10-50keV, and the dosage of ion implantation is 1.0 × e
13-1.0 × e
14cm
-2, the incident direction of ion implantation offsets certain angle relative to the direction perpendicular with Semiconductor substrate 100, and the scope of described angle is 0-45 degree.
Next, perform rapid thermal anneal process, with the Doped ions activated in low-doped source/drain region 104 and described bag-like region and eliminate above-mentioned ion implantation produce defect.In other embodiments, also can adopt other annealing way, similar effect should be able to be reached.
In the present embodiment, described rapid thermal anneal step is carried out after described low-doped ion implantation and described bag-like region ion implantation step, but not as limit, in other embodiments, described rapid thermal anneal step also can be carried out at twice, after described low-doped ion implantation step, namely carry out first time rapid thermal anneal step and carry out second time rapid thermal anneal step after described bag-like region ion implantation step.
Next, in Semiconductor substrate 100, form the heavy doping source/drain region 105 with stress.
For the nmos area in Semiconductor substrate 100, described stress is tension stress; For the PMOS district in Semiconductor substrate 100, described stress is compression.Described stress can be realized by following technical process: in Semiconductor substrate 100, form the groove with non-vertical side wall profile by the technique of first dry etching wet etching again, exemplarily, the shape of the section obtained along the direction perpendicular with Semiconductor substrate 100 of described groove can be ∑ shape or del; In described groove, formed the material layer that can produce described stress by selective epitaxial growth process, such as, produce the carbon silicon layer of tension stress or produce the germanium silicon layer of compression.Implement described epitaxially grown while or afterwards, perform heavy doping ion inject and anneal, complete the making of the heavy doping source/drain region 105 with stress.
Then, as shown in Figure 1B, dummy gate structure 102 is removed, to expose Semiconductor substrate 100.The processing step implementing described removal comprises: interlevel dielectric deposition 106 on a semiconductor substrate 100, to cover dummy gate structure 102 and side wall construction 103; Perform cmp to grind interlayer dielectric layer 106, until expose the top of dummy gate structure 102; Form the mask layer of patterning on a semiconductor substrate 100, expose the top of dummy gate structure 102; Implement dry etching and remove dummy gate structure 102, the etching gas of described dry etching can be fluorine-containing hydrocarbon, hydrogen bromide etc.; Enforcement wet etching or another dry etching remove the mask layer of described patterning.After the mask layer removing described patterning, wet clean process is adopted to remove etch residues and the impurity of the generation of described dry etching.In order to realize the object removing dummy gate structure 102 completely, above-mentioned technical process can produce etching excessively to a certain degree, and then removes a part of Semiconductor substrate 100 exposed.
Then, as shown in Figure 1 C, the Semiconductor substrate 100 exposed is etched, to form groove 107.Exemplarily, the degree of depth of groove 107 is 30nm-330nm.Exemplarily, described in be etched to wet etching or dry etching, the corrosive liquid of described wet etching can be hydrofluoric acid, hydrobromic acid, acetic acid etc., and the etching gas of described dry etching can be fluorine-containing hydrocarbon, Nitrogen trifluoride, ammonia etc.
Then, as shown in figure ip, formation has heavily stressed stress material layer 108, with filling groove 107.The processing step forming stress material layer 108 comprises: formed by depositing operation and have heavily stressed stress material layer 108, filling groove 107 while covering interlayer dielectric layer 106, exemplarily, the one in low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum CVD (UHVCVD), rapid thermal CVD (RTCVD), physical vapour deposition (PVD) (PVD), ald (ALD) and molecular beam epitaxy (MBE) is deposited as described in; Implement cmp, until expose the top of interlayer dielectric layer 106.By controlling the technological parameter of described deposition, stress material layer 108 can be made to have heavily stressed, described heavily stressed number range can be 1.7GPa-3.5GPa.For the nmos area in Semiconductor substrate 100, stress material layer 108 can be germanium silicon layer; For the PMOS district in Semiconductor substrate 100, stress material layer 108 can be carbon silicon layer.
Then, as referring to figure 1e, etching stress material layer 108, until the top of stress material layer 108 is lower than the upper surface of Semiconductor substrate 100.Exemplarily, described in be etched to wet etching or dry etching, the corrosive liquid of described wet etching can be hydrofluoric acid, hydrobromic acid, acetic acid etc., and the etching gas of described dry etching can be fluorine-containing hydrocarbon, Nitrogen trifluoride, ammonia etc.
It should be noted that, by above-mentioned for described by Fig. 1 D and Fig. 1 E in groove 107, form the implementation process with heavily stressed stress material layer 108 be a kind of example, other execution mode can also be adopted to be formed in groove 107 and to there is heavily stressed stress material layer 108, such as selective epitaxial growth process.
Then, as shown in fig. 1f, the epitaxial loayer 109 as raceway groove is formed at the top of stress material layer 108.Exemplarily, described epitaxy technique can adopt the one in low-pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, ultra-high vacuum CVD, rapid thermal CVD and molecular beam epitaxy.For the nmos area in Semiconductor substrate 100, epitaxial loayer 109 can be carbon silicon layer or silicon layer; For the PMOS district in Semiconductor substrate 100, epitaxial loayer 109 can be germanium silicon layer or silicon layer.While implementing described extension or afterwards, perform Doped ions inject and anneal, to regulate the threshold voltage of epitaxial loayer 109.For the nmos area in Semiconductor substrate 100, described Doped ions belongs to p-type impurity; For the PMOS district in Semiconductor substrate 100, described Doped ions belongs to N-shaped impurity.
So far, the processing step that the method completing according to an exemplary embodiment of the present is implemented.According to the present invention, humidification in the stress of device channel region, the threshold voltage of channel region can be improved further.
With reference to Fig. 2, the flow chart of the step that the method that illustrated therein is according to an exemplary embodiment of the present is implemented successively, for schematically illustrating the flow process of manufacturing process.
In step 201, provide Semiconductor substrate, be formed with dummy gate structure on a semiconductor substrate, be formed with side wall construction in the both sides of dummy gate structure;
In step 202., on a semiconductor substrate after interlevel dielectric deposition, remove dummy gate structure, to expose Semiconductor substrate;
In step 203, the Semiconductor substrate exposed is etched, to form groove;
In step 204, formation has heavily stressed stress material layer, to be partially filled described groove;
In step 205, the epitaxial loayer as raceway groove is formed at the top of described stress material layer.
[exemplary embodiment two]
Next, the making of whole semiconductor device can be completed by subsequent technique, comprise: on epitaxial loayer 109, form high k-metal gate structure, exemplarily, described high k-metal gate structure comprises the boundary layer stacked gradually, high k dielectric layer, cover layer, workfunction setting metal layer and metal gate material layer; Interlayer dielectric layer 106 is formed another interlayer dielectric layer, covers the top of described high k-metal gate structure; In described interlayer dielectric layer, form contact hole, expose the described top of high k-metal gate structure and the top of heavy doping source/drain region 105; Self-aligned silicide is formed at the top of the top of the described high k-metal gate structure exposed and heavy doping source/drain region 105; Fill metal (being generally tungsten) in described contact hole, form the connection interconnecting metal layer of follow-up formation and the contact plug of described self-aligned silicide; Form multiple interconnecting metal layer, usually adopt dual damascene process; Form metal pad, for wire bonding during subsequent implementation device package.
[exemplary embodiment three]
The present invention also provides a kind of electronic installation, the semiconductor device that it method comprising according to an exemplary embodiment of the present two manufactures.Described electronic installation can be mobile phone, panel computer, notebook computer, net book, game machine, television set, VCD, DVD, navigator, camera, video camera, recording pen, any electronic product such as MP3, MP4, PSP or equipment, also can be any intermediate products comprising described semiconductor device.Described electronic installation, owing to employing described semiconductor device, thus has better performance.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (10)
1. a manufacture method for semiconductor device, comprising:
Semiconductor substrate is provided, is formed with dummy gate structure on the semiconductor substrate, be formed with side wall construction in the both sides of described dummy gate structure;
On the semiconductor substrate after interlevel dielectric deposition, remove described dummy gate structure, to expose described Semiconductor substrate;
The Semiconductor substrate exposed described in etching, to form groove;
Formation has heavily stressed stress material layer, to be partially filled described groove;
The epitaxial loayer as raceway groove is formed at the top of described stress material layer.
2. method according to claim 1, is characterized in that, the degree of depth of described groove is 30nm-330nm.
3. method according to claim 1, is characterized in that, is etched to wet etching or dry etching to the described Semiconductor substrate exposed.
4. method according to claim 1, it is characterized in that, described formation has heavily stressed stress material layer, to be partially filled described groove, be specially: described in being formed by depositing operation, there is heavily stressed stress material layer, while covering described interlayer dielectric layer, fill described groove; Implement cmp to grind described stress material layer, until expose the top of described interlayer dielectric layer; Etch described stress material layer, until the top of described stress material layer is lower than the upper surface of described Semiconductor substrate.
5. method according to claim 1, is characterized in that, for the nmos area in described Semiconductor substrate, described stress material layer is germanium silicon layer; For the PMOS district in described Semiconductor substrate, described stress material layer is carbon silicon layer.
6. method according to claim 5, is characterized in that, described stress material layer has the stress of 1.7GPa-3.5GPa.
7. method according to claim 1, is characterized in that, for the nmos area in described Semiconductor substrate, described epitaxial loayer is carbon silicon layer or silicon layer; For the PMOS district in described Semiconductor substrate, described epitaxial loayer is germanium silicon layer or silicon layer.
8. method according to claim 1, is characterized in that, implement extension form described epitaxial loayer while or afterwards, also comprise perform Doped ions inject and the step of annealing, to regulate the threshold voltage of described epitaxial loayer.
9. the semiconductor device of the method manufacture adopting one of claim 1-8 described.
10. an electronic installation, described electronic installation comprises semiconductor device according to claim 9.
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| CN201410438323.9A CN105374683A (en) | 2014-08-29 | 2014-08-29 | Semiconductor device and manufacturing method thereof, and electronic device |
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|---|---|---|---|
| CN201410438323.9A CN105374683A (en) | 2014-08-29 | 2014-08-29 | Semiconductor device and manufacturing method thereof, and electronic device |
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| US20080116482A1 (en) * | 2006-11-21 | 2008-05-22 | Chartered Semiconductor Manufacturing Ltd. | Method to form selective strained si using lateral epitaxy |
| US20090085125A1 (en) * | 2007-09-28 | 2009-04-02 | Samsung Electronics Co., Ltd. | MOS transistor and CMOS transistor having strained channel epi layer and methods of fabricating the transistors |
| CN103715092A (en) * | 2012-09-29 | 2014-04-09 | 中芯国际集成电路制造(上海)有限公司 | MOS tube and forming method thereof |
-
2014
- 2014-08-29 CN CN201410438323.9A patent/CN105374683A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6943087B1 (en) * | 2003-12-17 | 2005-09-13 | Advanced Micro Devices, Inc. | Semiconductor on insulator MOSFET having strained silicon channel |
| US20080116482A1 (en) * | 2006-11-21 | 2008-05-22 | Chartered Semiconductor Manufacturing Ltd. | Method to form selective strained si using lateral epitaxy |
| US20090085125A1 (en) * | 2007-09-28 | 2009-04-02 | Samsung Electronics Co., Ltd. | MOS transistor and CMOS transistor having strained channel epi layer and methods of fabricating the transistors |
| CN103715092A (en) * | 2012-09-29 | 2014-04-09 | 中芯国际集成电路制造(上海)有限公司 | MOS tube and forming method thereof |
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Application publication date: 20160302 |